sim/mips/mips.igen

   1 //    <insn> ::=
   2 //        <insn-word> { "+" <insn-word> }
   3 //        ":" <format-name>
   4 //        ":" <filter-flags>
   5 //        ":" <options>
   6 //        ":" <name>
   7 //        <nl>
   8 //        { <insn-model> }
   9 //        { <insn-mnemonic> }
  10 //        <code-block>
  11 //
  12
  13
  14 // IGEN config - mips16
  15 :option:16::insn-bit-size:16
  16 :option:16::hi-bit-nr:15
  17 :option:16::insn-specifying-widths:true
  18 :option:16::gen-delayed-branch:false
  19
  20 // IGEN config - mips32/64..
  21 :option:32::insn-bit-size:32
  22 :option:32::hi-bit-nr:31
  23 :option:32::insn-specifying-widths:true
  24 :option:32::gen-delayed-branch:false
  25
  26
  27 // Generate separate simulators for each target
  28 // :option:::multi-sim:true
  29
  30
  31 // Models known by this simulator
  32 :model:::mipsI:mipsI:
  33 :model:::mipsII:mipsII:
  34 :model:::mipsIII:mipsIII:
  35 :model:::mipsIV:mipsIV:
  36 :model:::mips16:mips16:
  37 // start-sanitize-r5900
  38 :model:::r5900:r5900:
  39 // end-sanitize-r5900
  40 :model:::r3900:r3900:
  41 // start-sanitize-tx19
  42 :model:::tx19:tx19:
  43 // end-sanitize-tx19
  44 // start-sanitize-vr5400
  45 :model:::vr5400:vr5400:
  46 :model:::mdmx:mdmx:
  47 // end-sanitize-vr5400
  48 :model:::vr5000:vr5000:
  49
  50
  51
  52 // Pseudo instructions known by IGEN
  53 :internal::::illegal:
  54 {
  55   SignalException (ReservedInstruction, 0);
  56 }
  57
  58
  59 // Pseudo instructions known by interp.c
  60 // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
  61 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
  62 "rsvd <OP>"
  63 {
  64   SignalException (ReservedInstruction, instruction_0);
  65 }
  66
  67
  68
  69 //
  70 // Mips Architecture:
  71 //
  72 //        CPU Instruction Set (mipsI - mipsIV)
  73 //
  74
  75
  76 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
  77 "add r<RD>, r<RS>, r<RT>"
  78 *mipsI,mipsII,mipsIII,mipsIV:
  79 *vr5000:
  80 // start-sanitize-vr5400
  81 *vr5400:
  82 // end-sanitize-vr5400
  83 // start-sanitize-r5900
  84 *r5900:
  85 // end-sanitize-r5900
  86 *r3900:
  87 // start-sanitize-tx19
  88 *tx19:
  89 // end-sanitize-tx19
  90 {
  91   ALU32_BEGIN (GPR[RS]);
  92   ALU32_ADD (GPR[RT]);
  93   ALU32_END (GPR[RD]);
  94 }
  95
  96
  97 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
  98 "addi r<RT>, r<RS>, IMMEDIATE"
  99 *mipsI,mipsII,mipsIII,mipsIV:
 100 *vr5000:
 101 // start-sanitize-vr5400
 102 *vr5400:
 103 // end-sanitize-vr5400
 104 // start-sanitize-r5900
 105 *r5900:
 106 // end-sanitize-r5900
 107 *r3900:
 108 // start-sanitize-tx19
 109 *tx19:
 110 // end-sanitize-tx19
 111 {
 112   ALU32_BEGIN (GPR[RS]);
 113   ALU32_ADD (EXTEND16 (IMMEDIATE));
 114   ALU32_END (GPR[RT]);
 115 }
 116
 117
 118 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
 119 "add r<RT>, r<RS>, <IMMEDIATE>"
 120 *mipsI,mipsII,mipsIII,mipsIV:
 121 *vr5000:
 122 // start-sanitize-vr5400
 123 *vr5400:
 124 // end-sanitize-vr5400
 125 // start-sanitize-r5900
 126 *r5900:
 127 // end-sanitize-r5900
 128 *r3900:
 129 // start-sanitize-tx19
 130 *tx19:
 131 // end-sanitize-tx19
 132 {
 133   signed32 temp = GPR[RS] + EXTEND16 (IMMEDIATE);
 134   GPR[RT] = EXTEND32 (temp);
 135 }
 136
 137
 138 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
 139 *mipsI,mipsII,mipsIII,mipsIV:
 140 *vr5000:
 141 // start-sanitize-vr5400
 142 *vr5400:
 143 // end-sanitize-vr5400
 144 // start-sanitize-r5900
 145 *r5900:
 146 // end-sanitize-r5900
 147 *r3900:
 148 // start-sanitize-tx19
 149 *tx19:
 150 // end-sanitize-tx19
 151 {
 152   signed32 temp = GPR[RS] + GPR[RT];
 153   GPR[RD] = EXTEND32 (temp);
 154 }
 155
 156
 157 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
 158 "and r<RD>, r<RS>, r<RT>"
 159 *mipsI,mipsII,mipsIII,mipsIV:
 160 *vr5000:
 161 // start-sanitize-vr5400
 162 *vr5400:
 163 // end-sanitize-vr5400
 164 // start-sanitize-r5900
 165 *r5900:
 166 // end-sanitize-r5900
 167 *r3900:
 168 // start-sanitize-tx19
 169 *tx19:
 170 // end-sanitize-tx19
 171 {
 172   GPR[RD] = GPR[RS] & GPR[RT];
 173 }
 174
 175
 176 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
 177 "and r<RT>, r<RS>, <IMMEDIATE>"
 178 *mipsI,mipsII,mipsIII,mipsIV:
 179 *vr5000:
 180 // start-sanitize-vr5400
 181 *vr5400:
 182 // end-sanitize-vr5400
 183 // start-sanitize-r5900
 184 *r5900:
 185 // end-sanitize-r5900
 186 *r3900:
 187 // start-sanitize-tx19
 188 *tx19:
 189 // end-sanitize-tx19
 190 {
 191   GPR[RT] = GPR[RS] & IMMEDIATE;
 192 }
 193
 194
 195 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
 196 "beq r<RS>, r<RT>, <OFFSET>"
 197 *mipsI,mipsII,mipsIII,mipsIV:
 198 *vr5000:
 199 // start-sanitize-vr5400
 200 *vr5400:
 201 // end-sanitize-vr5400
 202 // start-sanitize-r5900
 203 *r5900:
 204 // end-sanitize-r5900
 205 *r3900:
 206 // start-sanitize-tx19
 207 *tx19:
 208 // end-sanitize-tx19
 209 {
 210   address_word offset = EXTEND16 (OFFSET) << 2;
 211   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 212     DELAY_SLOT (NIA + offset);
 213 }
 214
 215
 216 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
 217 "beql r<RS>, r<RT>, <OFFSET>"
 218 *mipsII:
 219 *mipsIII:
 220 *mipsIV:
 221 *vr5000:
 222 // start-sanitize-vr5400
 223 *vr5400:
 224 // end-sanitize-vr5400
 225 // start-sanitize-r5900
 226 *r5900:
 227 // end-sanitize-r5900
 228 *r3900:
 229 // start-sanitize-tx19
 230 *tx19:
 231 // end-sanitize-tx19
 232 {
 233   address_word offset = EXTEND16 (OFFSET) << 2;
 234   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 235     DELAY_SLOT (NIA + offset);
 236   else
 237     NULLIFY_NEXT_INSTRUCTION ();
 238 }
 239
 240
 241 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
 242 "bgez r<RS>, <OFFSET>"
 243 *mipsI,mipsII,mipsIII,mipsIV:
 244 *vr5000:
 245 // start-sanitize-vr5400
 246 *vr5400:
 247 // end-sanitize-vr5400
 248 // start-sanitize-r5900
 249 *r5900:
 250 // end-sanitize-r5900
 251 *r3900:
 252 // start-sanitize-tx19
 253 *tx19:
 254 // end-sanitize-tx19
 255 {
 256   address_word offset = EXTEND16 (OFFSET) << 2;
 257   if ((signed_word) GPR[RS] >= 0)
 258     DELAY_SLOT (NIA + offset);
 259 }
 260
 261
 262 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
 263 "bgezal r<RS>, <OFFSET>"
 264 *mipsI,mipsII,mipsIII,mipsIV:
 265 *vr5000:
 266 // start-sanitize-vr5400
 267 *vr5400:
 268 // end-sanitize-vr5400
 269 // start-sanitize-r5900
 270 *r5900:
 271 // end-sanitize-r5900
 272 *r3900:
 273 // start-sanitize-tx19
 274 *tx19:
 275 // end-sanitize-tx19
 276 {
 277   address_word offset = EXTEND16 (OFFSET) << 2;
 278   RA = (CIA + 8);
 279   if ((signed_word) GPR[RS] >= 0)
 280     DELAY_SLOT (NIA + offset);
 281 }
 282
 283
 284 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
 285 "bgezall r<RS>, <OFFSET>"
 286 *mipsII:
 287 *mipsIII:
 288 *mipsIV:
 289 *vr5000:
 290 // start-sanitize-vr5400
 291 *vr5400:
 292 // end-sanitize-vr5400
 293 // start-sanitize-r5900
 294 *r5900:
 295 // end-sanitize-r5900
 296 *r3900:
 297 // start-sanitize-tx19
 298 *tx19:
 299 // end-sanitize-tx19
 300 {
 301   address_word offset = EXTEND16 (OFFSET) << 2;
 302   RA = (CIA + 8);
 303   /* NOTE: The branch occurs AFTER the next instruction has been
 304      executed */
 305   if ((signed_word) GPR[RS] >= 0)
 306     DELAY_SLOT (NIA + offset);
 307   else
 308     NULLIFY_NEXT_INSTRUCTION ();
 309 }
 310
 311
 312 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
 313 "bgezl r<RS>, <OFFSET>"
 314 *mipsII:
 315 *mipsIII:
 316 *mipsIV:
 317 *vr5000:
 318 // start-sanitize-vr5400
 319 *vr5400:
 320 // end-sanitize-vr5400
 321 // start-sanitize-r5900
 322 *r5900:
 323 // end-sanitize-r5900
 324 *r3900:
 325 // start-sanitize-tx19
 326 *tx19:
 327 // end-sanitize-tx19
 328 {
 329   address_word offset = EXTEND16 (OFFSET) << 2;
 330   if ((signed_word) GPR[RS] >= 0)
 331     DELAY_SLOT (NIA + offset);
 332   else
 333     NULLIFY_NEXT_INSTRUCTION ();
 334 }
 335
 336
 337 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
 338 "bgtz r<RS>, <OFFSET>"
 339 *mipsI,mipsII,mipsIII,mipsIV:
 340 *vr5000:
 341 // start-sanitize-vr5400
 342 *vr5400:
 343 // end-sanitize-vr5400
 344 // start-sanitize-r5900
 345 *r5900:
 346 // end-sanitize-r5900
 347 *r3900:
 348 // start-sanitize-tx19
 349 *tx19:
 350 // end-sanitize-tx19
 351 {
 352   address_word offset = EXTEND16 (OFFSET) << 2;
 353   if ((signed_word) GPR[RS] > 0)
 354     DELAY_SLOT (NIA + offset);
 355 }
 356
 357
 358 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
 359 "bgtzl r<RS>, <OFFSET>"
 360 *mipsII:
 361 *mipsIII:
 362 *mipsIV:
 363 *vr5000:
 364 // start-sanitize-vr5400
 365 *vr5400:
 366 // end-sanitize-vr5400
 367 // start-sanitize-r5900
 368 *r5900:
 369 // end-sanitize-r5900
 370 *r3900:
 371 // start-sanitize-tx19
 372 *tx19:
 373 // end-sanitize-tx19
 374 {
 375   address_word offset = EXTEND16 (OFFSET) << 2;
 376   /* NOTE: The branch occurs AFTER the next instruction has been
 377      executed */
 378   if ((signed_word) GPR[RS] > 0)
 379     DELAY_SLOT (NIA + offset);
 380   else
 381     NULLIFY_NEXT_INSTRUCTION ();
 382 }
 383
 384
 385 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
 386 "blez r<RS>, <OFFSET>"
 387 *mipsI,mipsII,mipsIII,mipsIV:
 388 *vr5000:
 389 // start-sanitize-vr5400
 390 *vr5400:
 391 // end-sanitize-vr5400
 392 // start-sanitize-r5900
 393 *r5900:
 394 // end-sanitize-r5900
 395 *r3900:
 396 // start-sanitize-tx19
 397 *tx19:
 398 // end-sanitize-tx19
 399 {
 400   address_word offset = EXTEND16 (OFFSET) << 2;
 401   /* NOTE: The branch occurs AFTER the next instruction has been
 402      executed */
 403   if ((signed_word) GPR[RS] <= 0)
 404     DELAY_SLOT (NIA + offset);
 405 }
 406
 407
 408 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
 409 "bgezl r<RS>, <OFFSET>"
 410 *mipsII:
 411 *mipsIII:
 412 *mipsIV:
 413 *vr5000:
 414 // start-sanitize-vr5400
 415 *vr5400:
 416 // end-sanitize-vr5400
 417 // start-sanitize-r5900
 418 *r5900:
 419 // end-sanitize-r5900
 420 *r3900:
 421 // start-sanitize-tx19
 422 *tx19:
 423 // end-sanitize-tx19
 424 {
 425   address_word offset = EXTEND16 (OFFSET) << 2;
 426   if ((signed_word) GPR[RS] <= 0)
 427     DELAY_SLOT (NIA + offset);
 428   else
 429     NULLIFY_NEXT_INSTRUCTION ();
 430 }
 431
 432
 433 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
 434 "bltz r<RS>, <OFFSET>"
 435 *mipsI,mipsII,mipsIII,mipsIV:
 436 *vr5000:
 437 // start-sanitize-vr5400
 438 *vr5400:
 439 // end-sanitize-vr5400
 440 // start-sanitize-r5900
 441 *r5900:
 442 // end-sanitize-r5900
 443 *r3900:
 444 // start-sanitize-tx19
 445 *tx19:
 446 // end-sanitize-tx19
 447 {
 448   address_word offset = EXTEND16 (OFFSET) << 2;
 449   if ((signed_word) GPR[RS] < 0)
 450     DELAY_SLOT (NIA + offset);
 451 }
 452
 453
 454 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
 455 "bltzal r<RS>, <OFFSET>"
 456 *mipsI,mipsII,mipsIII,mipsIV:
 457 *vr5000:
 458 // start-sanitize-vr5400
 459 *vr5400:
 460 // end-sanitize-vr5400
 461 // start-sanitize-r5900
 462 *r5900:
 463 // end-sanitize-r5900
 464 *r3900:
 465 // start-sanitize-tx19
 466 *tx19:
 467 // end-sanitize-tx19
 468 {
 469   address_word offset = EXTEND16 (OFFSET) << 2;
 470   RA = (CIA + 8);
 471   /* NOTE: The branch occurs AFTER the next instruction has been
 472      executed */
 473   if ((signed_word) GPR[RS] < 0)
 474     DELAY_SLOT (NIA + offset);
 475 }
 476
 477
 478 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
 479 "bltzall r<RS>, <OFFSET>"
 480 *mipsII:
 481 *mipsIII:
 482 *mipsIV:
 483 *vr5000:
 484 // start-sanitize-vr5400
 485 *vr5400:
 486 // end-sanitize-vr5400
 487 // start-sanitize-r5900
 488 *r5900:
 489 // end-sanitize-r5900
 490 *r3900:
 491 // start-sanitize-tx19
 492 *tx19:
 493 // end-sanitize-tx19
 494 {
 495   address_word offset = EXTEND16 (OFFSET) << 2;
 496   RA = (CIA + 8);
 497   if ((signed_word) GPR[RS] < 0)
 498     DELAY_SLOT (NIA + offset);
 499   else
 500     NULLIFY_NEXT_INSTRUCTION ();
 501 }
 502
 503
 504 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
 505 "bltzl r<RS>, <OFFSET>"
 506 *mipsII:
 507 *mipsIII:
 508 *mipsIV:
 509 *vr5000:
 510 // start-sanitize-vr5400
 511 *vr5400:
 512 // end-sanitize-vr5400
 513 // start-sanitize-r5900
 514 *r5900:
 515 // end-sanitize-r5900
 516 *r3900:
 517 // start-sanitize-tx19
 518 *tx19:
 519 // end-sanitize-tx19
 520 {
 521   address_word offset = EXTEND16 (OFFSET) << 2;
 522   /* NOTE: The branch occurs AFTER the next instruction has been
 523      executed */
 524   if ((signed_word) GPR[RS] < 0)
 525     DELAY_SLOT (NIA + offset);
 526   else
 527     NULLIFY_NEXT_INSTRUCTION ();
 528 }
 529
 530
 531 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
 532 "bne r<RS>, r<RT>, <OFFSET>"
 533 *mipsI,mipsII,mipsIII,mipsIV:
 534 *vr5000:
 535 // start-sanitize-vr5400
 536 *vr5400:
 537 // end-sanitize-vr5400
 538 // start-sanitize-r5900
 539 *r5900:
 540 // end-sanitize-r5900
 541 *r3900:
 542 // start-sanitize-tx19
 543 *tx19:
 544 // end-sanitize-tx19
 545 {
 546   address_word offset = EXTEND16 (OFFSET) << 2;
 547   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
 548     DELAY_SLOT (NIA + offset);
 549 }
 550
 551
 552 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
 553 "bnel r<RS>, r<RT>, <OFFSET>"
 554 *mipsII:
 555 *mipsIII:
 556 *mipsIV:
 557 *vr5000:
 558 // start-sanitize-vr5400
 559 *vr5400:
 560 // end-sanitize-vr5400
 561 // start-sanitize-r5900
 562 *r5900:
 563 // end-sanitize-r5900
 564 *r3900:
 565 // start-sanitize-tx19
 566 *tx19:
 567 // end-sanitize-tx19
 568 {
 569   address_word offset = EXTEND16 (OFFSET) << 2;
 570   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
 571     DELAY_SLOT (NIA + offset);
 572   else
 573     NULLIFY_NEXT_INSTRUCTION ();
 574 }
 575
 576
 577 000000,20.CODE,001101:SPECIAL:32::BREAK
 578 "break"
 579 *mipsI,mipsII,mipsIII,mipsIV:
 580 *vr5000:
 581 // start-sanitize-vr5400
 582 *vr5400:
 583 // end-sanitize-vr5400
 584 // start-sanitize-r5900
 585 *r5900:
 586 // end-sanitize-r5900
 587 *r3900:
 588 // start-sanitize-tx19
 589 *tx19:
 590 // end-sanitize-tx19
 591 {
 592   SignalException(BreakPoint, instruction_0);
 593 }
 594
 595
 596 0100,ZZ!0!1!3,26.COP_FUN:NORMAL:32::COPz
 597 "cop<ZZ> <COP_FUN>"
 598 *mipsI,mipsII,mipsIII,mipsIV:
 599 // start-sanitize-r5900
 600 *r5900:
 601 // end-sanitize-r5900
 602 *r3900:
 603 // start-sanitize-tx19
 604 *tx19:
 605 // end-sanitize-tx19
 606 {
 607   DecodeCoproc (instruction_0);
 608 }
 609
 610
 611 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
 612 "dadd r<RD>, r<RS>, r<RT>"
 613 *mipsIII:
 614 *mipsIV:
 615 *vr5000:
 616 // start-sanitize-vr5400
 617 *vr5400:
 618 // end-sanitize-vr5400
 619 // start-sanitize-r5900
 620 *r5900:
 621 // end-sanitize-r5900
 622 *r3900:
 623 // start-sanitize-tx19
 624 *tx19:
 625 // end-sanitize-tx19
 626 {
 627   ALU64_BEGIN (GPR[RS]);
 628   ALU64_ADD (GPR[RT]);
 629   ALU64_END (GPR[RT]);
 630 }
 631
 632
 633 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
 634 "daddi r<RT>, r<RS>, <IMMEDIATE>"
 635 *mipsIII:
 636 *mipsIV:
 637 *vr5000:
 638 // start-sanitize-vr5400
 639 *vr5400:
 640 // end-sanitize-vr5400
 641 // start-sanitize-r5900
 642 *r5900:
 643 // end-sanitize-r5900
 644 *r3900:
 645 // start-sanitize-tx19
 646 *tx19:
 647 // end-sanitize-tx19
 648 {
 649   ALU64_BEGIN (GPR[RS]);
 650   ALU64_ADD (EXTEND16 (IMMEDIATE));
 651   ALU64_END (GPR[RT]);
 652 }
 653
 654
 655 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
 656 "daddu r<RT>, r<RS>, <IMMEDIATE>"
 657 *mipsIII:
 658 *mipsIV:
 659 *vr5000:
 660 // start-sanitize-vr5400
 661 *vr5400:
 662 // end-sanitize-vr5400
 663 // start-sanitize-r5900
 664 *r5900:
 665 // end-sanitize-r5900
 666 *r3900:
 667 // start-sanitize-tx19
 668 *tx19:
 669 // end-sanitize-tx19
 670 {
 671   GPR[RT] = GPR[RS] + EXTEND16 (IMMEDIATE);
 672 }
 673
 674
 675 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
 676 "daddu r<RD>, r<RS>, r<RT>"
 677 *mipsIII:
 678 *mipsIV:
 679 *vr5000:
 680 // start-sanitize-vr5400
 681 *vr5400:
 682 // end-sanitize-vr5400
 683 // start-sanitize-r5900
 684 *r5900:
 685 // end-sanitize-r5900
 686 *r3900:
 687 // start-sanitize-tx19
 688 *tx19:
 689 // end-sanitize-tx19
 690 {
 691   GPR[RD] = GPR[RS] + GPR[RT];
 692 }
 693
 694
 695 000000,5.RS,5.RT,0000000000011110:SPECIAL:64::DDIV
 696 "ddiv r<RS>, r<RT>"
 697 *mipsIII:
 698 *mipsIV:
 699 *vr5000:
 700 // start-sanitize-vr5400
 701 *vr5400:
 702 // end-sanitize-vr5400
 703 // start-sanitize-r5900
 704 *r5900:
 705 // end-sanitize-r5900
 706 *r3900:
 707 // start-sanitize-tx19
 708 *tx19:
 709 // end-sanitize-tx19
 710 {
 711   CHECKHILO ("Division");
 712   {
 713     signed64 n = GPR[RS];
 714     signed64 d = GPR[RT];
 715     if (d == 0)
 716       {
 717         LO = SIGNED64 (0x8000000000000000);
 718         HI = 0;
 719       }
 720     else if (d == -1 && n == SIGNED64 (0x8000000000000000))
 721       {
 722         LO = SIGNED64 (0x8000000000000000);
 723         HI = 0;
 724       }
 725     else
 726       {
 727         LO = (n / d);
 728         HI = (n % d);
 729       }
 730   }
 731 }
 732
 733
 734
 735 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
 736 "ddivu r<RS>, r<RT>"
 737 *mipsIII:
 738 *mipsIV:
 739 *r3900:
 740 *vr5000:
 741 // start-sanitize-vr5400
 742 *vr5400:
 743 // end-sanitize-vr5400
 744 // start-sanitize-tx19
 745 *tx19:
 746 // end-sanitize-tx19
 747 {
 748   CHECKHILO ("Division");
 749   {
 750     unsigned64 n = GPR[RS];
 751     unsigned64 d = GPR[RT];
 752     if (d == 0)
 753       {
 754         LO = SIGNED64 (0x8000000000000000);
 755         HI = 0;
 756       }
 757     else
 758       {
 759         LO = (n / d);
 760         HI = (n % d);
 761       }
 762   }
 763 }
 764
 765
 766 000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV
 767 "div r<RS>, r<RT>"
 768 *mipsI,mipsII,mipsIII,mipsIV:
 769 *vr5000:
 770 // start-sanitize-vr5400
 771 *vr5400:
 772 // end-sanitize-vr5400
 773 // start-sanitize-r5900
 774 *r5900:
 775 // end-sanitize-r5900
 776 *r3900:
 777 // start-sanitize-tx19
 778 *tx19:
 779 // end-sanitize-tx19
 780 {
 781   CHECKHILO("Division");
 782   {
 783     signed32 n = GPR[RS];
 784     signed32 d = GPR[RT];
 785     if (d == 0)
 786       {
 787         LO = EXTEND32 (0x80000000);
 788         HI = EXTEND32 (0);
 789       }
 790     else if (d == -1 && d == 0x80000000)
 791       {
 792         LO = EXTEND32 (0x80000000);
 793         HI = EXTEND32 (0);
 794       }
 795     else
 796       {
 797         LO = EXTEND32 (n / d);
 798         HI = EXTEND32 (n % d);
 799       }
 800   }
 801 }
 802
 803
 804 000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU
 805 "divu r<RS>, r<RT>"
 806 *mipsI,mipsII,mipsIII,mipsIV:
 807 *vr5000:
 808 // start-sanitize-vr5400
 809 *vr5400:
 810 // end-sanitize-vr5400
 811 // start-sanitize-r5900
 812 *r5900:
 813 // end-sanitize-r5900
 814 *r3900:
 815 // start-sanitize-tx19
 816 *tx19:
 817 // end-sanitize-tx19
 818 {
 819   CHECKHILO ("Division");
 820   {
 821     unsigned32 n = GPR[RS];
 822     unsigned32 d = GPR[RT];
 823     if (d == 0)
 824       {
 825         LO = EXTEND32 (0x80000000);
 826         HI = EXTEND32 (0);
 827       }
 828    else
 829      {
 830        LO = EXTEND32 (n / d);
 831        HI = EXTEND32 (n % d);
 832      }
 833   }
 834 }
 835
 836
 837 :function:::void:do_dmult:int rs, int rt, int rd, int signed_p
 838 {
 839   unsigned64 lo;
 840   unsigned64 hi;
 841   unsigned64 m00;
 842   unsigned64 m01;
 843   unsigned64 m10;
 844   unsigned64 m11;
 845   unsigned64 mid;
 846   int sign;
 847   unsigned64 op1 = GPR[rs];
 848   unsigned64 op2 = GPR[rt];
 849   CHECKHILO ("Multiplication");
 850   /* make signed multiply unsigned */
 851   sign = 0;
 852   if (signed_p)
 853     {
 854       if (op1 < 0)
 855         {
 856           op1 = - op1;
 857           ++sign;
 858         }
 859       if (op2 < 0)
 860         {
 861           op2 = - op2;
 862           ++sign;
 863         }
 864     }
 865   /* multuply out the 4 sub products */
 866   m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
 867   m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
 868   m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
 869   m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
 870   /* add the products */
 871   mid = ((unsigned64) VH4_8 (m00)
 872          + (unsigned64) VL4_8 (m10)
 873          + (unsigned64) VL4_8 (m01));
 874   lo = U8_4 (mid, m00);
 875   hi = (m11
 876         + (unsigned64) VH4_8 (mid)
 877         + (unsigned64) VH4_8 (m01)
 878         + (unsigned64) VH4_8 (m10));
 879   /* fix the sign */
 880   if (sign & 1)
 881     {
 882       lo = -lo;
 883       if (lo == 0)
 884         hi = -hi;
 885       else
 886         hi = -hi - 1;
 887     }
 888   /* save the result HI/LO (and a gpr) */
 889   LO = lo;
 890   HI = hi;
 891   if (rd != 0)
 892     GPR[rd] = lo;
 893 }
 894
 895
 896 000000,5.RS,5.RT,0000000000011100:SPECIAL:64::DMULT
 897 "dmult r<RS>, r<RT>"
 898 *mipsIII,mipsIV:
 899 *r3900:
 900 // start-sanitize-tx19
 901 *tx19:
 902 // end-sanitize-tx19
 903 {
 904   do_dmult (SD_, RS, RT, 0, 1);
 905 }
 906
 907 000000,5.RS,5.RT,5.RD,00000011100:SPECIAL:64::DMULT
 908 "dmult r<RS>, r<RT>":RD == 0
 909 "dmult r<RD>, r<RS>, r<RT>"
 910 *vr5000:
 911 // start-sanitize-vr5400
 912 *vr5400:
 913 // end-sanitize-vr5400
 914 {
 915   do_dmult (SD_, RS, RT, RD, 1);
 916 }
 917
 918
 919
 920 000000,5.RS,5.RT,0000000000011101:SPECIAL:64::DMULTU
 921 "dmultu r<RS>, r<RT>"
 922 *mipsIII,mipsIV:
 923 *r3900:
 924 // start-sanitize-tx19
 925 *tx19:
 926 // end-sanitize-tx19
 927 {
 928   do_dmult (SD_, RS, RT, 0, 0);
 929 }
 930
 931 000000,5.RS,5.RT,5.RD,00000011101:SPECIAL:64::DMULTU
 932 "dmultu r<RD>, r<RS>, r<RT>":RD == 0
 933 "dmultu r<RS>, r<RT>"
 934 *vr5000:
 935 // start-sanitize-vr5400
 936 *vr5400:
 937 // end-sanitize-vr5400
 938 {
 939   do_dmult (SD_, RS, RT, RD, 0);
 940 }
 941
 942
 943
 944 00000000000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
 945 "dsll r<RD>, r<RT>, <SHIFT>"
 946 *mipsIII:
 947 *mipsIV:
 948 *vr5000:
 949 // start-sanitize-vr5400
 950 *vr5400:
 951 // end-sanitize-vr5400
 952 // start-sanitize-r5900
 953 *r5900:
 954 // end-sanitize-r5900
 955 *r3900:
 956 // start-sanitize-tx19
 957 *tx19:
 958 // end-sanitize-tx19
 959 {
 960   int s = SHIFT;
 961   GPR[RD] = GPR[RT] << s;
 962 }
 963
 964
 965 00000000000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
 966 "dsll32 r<RD>, r<RT>, <SHIFT>"
 967 *mipsIII:
 968 *mipsIV:
 969 *vr5000:
 970 // start-sanitize-vr5400
 971 *vr5400:
 972 // end-sanitize-vr5400
 973 // start-sanitize-r5900
 974 *r5900:
 975 // end-sanitize-r5900
 976 *r3900:
 977 // start-sanitize-tx19
 978 *tx19:
 979 // end-sanitize-tx19
 980 {
 981   int s = 32 + SHIFT;
 982   GPR[RD] = GPR[RT] << s;
 983 }
 984
 985
 986 000000,5.RS,5.RT,5.RD,00000010100:SPECIAL:64::DSLLV
 987 "dsllv r<RD>, r<RT>, r<RS>"
 988 *mipsIII:
 989 *mipsIV:
 990 *vr5000:
 991 // start-sanitize-vr5400
 992 *vr5400:
 993 // end-sanitize-vr5400
 994 // start-sanitize-r5900
 995 *r5900:
 996 // end-sanitize-r5900
 997 *r3900:
 998 // start-sanitize-tx19
 999 *tx19:
1000 // end-sanitize-tx19
1001 {
1002   int s = MASKED64 (GPR[RS], 5, 0);
1003   GPR[RD] = GPR[RT] << s;
1004 }
1005
1006
1007 00000000000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
1008 "dsra r<RD>, r<RT>, <SHIFT>"
1009 *mipsIII:
1010 *mipsIV:
1011 *vr5000:
1012 // start-sanitize-vr5400
1013 *vr5400:
1014 // end-sanitize-vr5400
1015 // start-sanitize-r5900
1016 *r5900:
1017 // end-sanitize-r5900
1018 *r3900:
1019 // start-sanitize-tx19
1020 *tx19:
1021 // end-sanitize-tx19
1022 {
1023   int s = SHIFT;
1024   GPR[RD] = ((signed64) GPR[RT]) >> s;
1025 }
1026
1027
1028 00000000000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
1029 "dsra32 r<RT>, r<RD>, <SHIFT>"
1030 *mipsIII:
1031 *mipsIV:
1032 *vr5000:
1033 // start-sanitize-vr5400
1034 *vr5400:
1035 // end-sanitize-vr5400
1036 // start-sanitize-r5900
1037 *r5900:
1038 // end-sanitize-r5900
1039 *r3900:
1040 // start-sanitize-tx19
1041 *tx19:
1042 // end-sanitize-tx19
1043 {
1044   int s = 32 + SHIFT;
1045   GPR[RD] = ((signed64) GPR[RT]) >> s;
1046 }
1047
1048
1049 000000,5.RS,5.RT,5.RD,00000010111:SPECIAL:64::DSRAV
1050 "dsra32 r<RT>, r<RD>, r<RS>"
1051 *mipsIII:
1052 *mipsIV:
1053 *vr5000:
1054 // start-sanitize-vr5400
1055 *vr5400:
1056 // end-sanitize-vr5400
1057 // start-sanitize-r5900
1058 *r5900:
1059 // end-sanitize-r5900
1060 *r3900:
1061 // start-sanitize-tx19
1062 *tx19:
1063 // end-sanitize-tx19
1064 {
1065   int s = MASKED64 (GPR[RS], 5, 0);
1066   GPR[RD] = ((signed64) GPR[RT]) >> s;
1067 }
1068
1069
1070 00000000000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
1071 "dsrav r<RD>, r<RT>, <SHIFT>"
1072 *mipsIII:
1073 *mipsIV:
1074 *vr5000:
1075 // start-sanitize-vr5400
1076 *vr5400:
1077 // end-sanitize-vr5400
1078 // start-sanitize-r5900
1079 *r5900:
1080 // end-sanitize-r5900
1081 *r3900:
1082 // start-sanitize-tx19
1083 *tx19:
1084 // end-sanitize-tx19
1085 {
1086   int s = SHIFT;
1087   GPR[RD] = (unsigned64) GPR[RT] >> s;
1088 }
1089
1090
1091 00000000000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
1092 "dsrl32 r<RD>, r<RT>, <SHIFT>"
1093 *mipsIII:
1094 *mipsIV:
1095 *vr5000:
1096 // start-sanitize-vr5400
1097 *vr5400:
1098 // end-sanitize-vr5400
1099 // start-sanitize-r5900
1100 *r5900:
1101 // end-sanitize-r5900
1102 *r3900:
1103 // start-sanitize-tx19
1104 *tx19:
1105 // end-sanitize-tx19
1106 {
1107   int s = 32 + SHIFT;
1108   GPR[RD] = (unsigned64) GPR[RT] >> s;
1109 }
1110
1111
1112 000000,5.RS,5.RT,5.RD,00000010110:SPECIAL:64::DSRLV
1113 "dsrl32 r<RD>, r<RT>, r<RS>"
1114 *mipsIII:
1115 *mipsIV:
1116 *vr5000:
1117 // start-sanitize-vr5400
1118 *vr5400:
1119 // end-sanitize-vr5400
1120 // start-sanitize-r5900
1121 *r5900:
1122 // end-sanitize-r5900
1123 *r3900:
1124 // start-sanitize-tx19
1125 *tx19:
1126 // end-sanitize-tx19
1127 {
1128   int s = MASKED64 (GPR[RS], 5, 0);
1129   GPR[RD] = (unsigned64) GPR[RT] >> s;
1130 }
1131
1132
1133 000000,5.RS,5.RT,5.RD,00000101110:SPECIAL:64::DSUB
1134 "dsub r<RD>, r<RS>, r<RT>"
1135 *mipsIII:
1136 *mipsIV:
1137 *vr5000:
1138 // start-sanitize-vr5400
1139 *vr5400:
1140 // end-sanitize-vr5400
1141 // start-sanitize-r5900
1142 *r5900:
1143 // end-sanitize-r5900
1144 *r3900:
1145 // start-sanitize-tx19
1146 *tx19:
1147 // end-sanitize-tx19
1148 {
1149   ALU64_BEGIN (GPR[RS]);
1150   ALU64_SUB (GPR[RT]);
1151   ALU64_END (GPR[RD]);
1152 }
1153
1154
1155 000000,5.RS,5.RT,5.RD,00000101111:SPECIAL:64::DSUBU
1156 "dsubu r<RD>, r<RS>, r<RT>"
1157 *mipsIII:
1158 *mipsIV:
1159 *vr5000:
1160 // start-sanitize-vr5400
1161 *vr5400:
1162 // end-sanitize-vr5400
1163 // start-sanitize-r5900
1164 *r5900:
1165 // end-sanitize-r5900
1166 *r3900:
1167 // start-sanitize-tx19
1168 *tx19:
1169 // end-sanitize-tx19
1170 {
1171   GPR[RD] = GPR[RS] - GPR[RT];
1172 }
1173
1174
1175 000010,26.INSTR_INDEX:NORMAL:32::J
1176 "j <INSTR_INDEX>"
1177 *mipsI,mipsII,mipsIII,mipsIV:
1178 *vr5000:
1179 // start-sanitize-vr5400
1180 *vr5400:
1181 // end-sanitize-vr5400
1182 // start-sanitize-r5900
1183 *r5900:
1184 // end-sanitize-r5900
1185 *r3900:
1186 // start-sanitize-tx19
1187 *tx19:
1188 // end-sanitize-tx19
1189 {
1190   /* NOTE: The region used is that of the delay slot NIA and NOT the
1191      current instruction */
1192   address_word region = (NIA & MASK (63, 28));
1193   DELAY_SLOT (region | (INSTR_INDEX << 2));
1194 }
1195
1196
1197 000011,26.INSTR_INDEX:NORMAL:32::JAL
1198 "jal <INSTR_INDEX>"
1199 *mipsI,mipsII,mipsIII,mipsIV:
1200 *vr5000:
1201 // start-sanitize-vr5400
1202 *vr5400:
1203 // end-sanitize-vr5400
1204 // start-sanitize-r5900
1205 *r5900:
1206 // end-sanitize-r5900
1207 *r3900:
1208 // start-sanitize-tx19
1209 *tx19:
1210 // end-sanitize-tx19
1211 {
1212   /* NOTE: The region used is that of the delay slot and NOT the
1213      current instruction */
1214   address_word region = (NIA & MASK (63, 28));
1215   GPR[31] = CIA + 8;
1216   DELAY_SLOT (region | (INSTR_INDEX << 2));
1217 }
1218
1219
1220 000000,5.RS,00000,5.RD,00000001001:SPECIAL:32::JALR
1221 "jalr r<RS>":RD == 31
1222 "jalr r<RD>, r<RS>"
1223 *mipsI,mipsII,mipsIII,mipsIV:
1224 *vr5000:
1225 // start-sanitize-vr5400
1226 *vr5400:
1227 // end-sanitize-vr5400
1228 // start-sanitize-r5900
1229 *r5900:
1230 // end-sanitize-r5900
1231 *r3900:
1232 // start-sanitize-tx19
1233 *tx19:
1234 // end-sanitize-tx19
1235 {
1236   address_word temp = GPR[RS];
1237   GPR[RD] = CIA + 8;
1238   DELAY_SLOT (temp);
1239 }
1240
1241
1242 000000,5.RS,000000000000000001000:SPECIAL:32::JR
1243 "jr r<RS>"
1244 *mipsI,mipsII,mipsIII,mipsIV:
1245 *vr5000:
1246 // start-sanitize-vr5400
1247 *vr5400:
1248 // end-sanitize-vr5400
1249 // start-sanitize-r5900
1250 *r5900:
1251 // end-sanitize-r5900
1252 *r3900:
1253 // start-sanitize-tx19
1254 *tx19:
1255 // end-sanitize-tx19
1256 {
1257   DELAY_SLOT (GPR[RS]);
1258 }
1259
1260
1261 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
1262 "lb r<RT>, <OFFSET>(r<BASE>)"
1263 *mipsI,mipsII,mipsIII,mipsIV:
1264 *vr5000:
1265 // start-sanitize-vr5400
1266 *vr5400:
1267 // end-sanitize-vr5400
1268 // start-sanitize-r5900
1269 *r5900:
1270 // end-sanitize-r5900
1271 *r3900:
1272 // start-sanitize-tx19
1273 *tx19:
1274 // end-sanitize-tx19
1275 {
1276   unsigned32 instruction = instruction_0;
1277   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1278   int destreg = ((instruction >> 16) & 0x0000001F);
1279   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1280   {
1281     address_word vaddr = ((uword64)op1 + offset);
1282     address_word paddr;
1283     int uncached;
1284     {
1285       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1286         {
1287           uword64 memval = 0;
1288           uword64 memval1 = 0;
1289           uword64 mask = 0x7;
1290           unsigned int shift = 0;
1291           unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1292           unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1293           unsigned int byte;
1294           paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1295           LoadMemory(&memval,&memval1,uncached,AccessLength_BYTE,paddr,vaddr,isDATA,isREAL);
1296           byte = ((vaddr & mask) ^ (bigend << shift));
1297           GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0x000000FF),8));
1298         }
1299     }
1300   }
1301 }
1302
1303
1304 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
1305 "lbu r<RT>, <OFFSET>(r<BASE>)"
1306 *mipsI,mipsII,mipsIII,mipsIV:
1307 *vr5000:
1308 // start-sanitize-vr5400
1309 *vr5400:
1310 // end-sanitize-vr5400
1311 // start-sanitize-r5900
1312 *r5900:
1313 // end-sanitize-r5900
1314 *r3900:
1315 // start-sanitize-tx19
1316 *tx19:
1317 // end-sanitize-tx19
1318 {
1319   unsigned32 instruction = instruction_0;
1320   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1321   int destreg = ((instruction >> 16) & 0x0000001F);
1322   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1323   {
1324     address_word vaddr = ((unsigned64)op1 + offset);
1325     address_word paddr;
1326     int uncached;
1327     {
1328       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1329         {
1330           unsigned64 memval = 0;
1331           unsigned64 memval1 = 0;
1332           unsigned64 mask = 0x7;
1333           unsigned int shift = 0;
1334           unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1335           unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1336           unsigned int byte;
1337           paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1338           LoadMemory(&memval,&memval1,uncached,AccessLength_BYTE,paddr,vaddr,isDATA,isREAL);
1339           byte = ((vaddr & mask) ^ (bigend << shift));
1340           GPR[destreg] = (((memval >> (8 * byte)) & 0x000000FF));
1341         }
1342     }
1343   }
1344 }
1345
1346
1347 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
1348 "ld r<RT>, <OFFSET>(r<BASE>)"
1349 *mipsIII:
1350 *mipsIV:
1351 *vr5000:
1352 // start-sanitize-vr5400
1353 *vr5400:
1354 // end-sanitize-vr5400
1355 // start-sanitize-r5900
1356 *r5900:
1357 // end-sanitize-r5900
1358 *r3900:
1359 // start-sanitize-tx19
1360 *tx19:
1361 // end-sanitize-tx19
1362 {
1363   unsigned32 instruction = instruction_0;
1364   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1365   int destreg = ((instruction >> 16) & 0x0000001F);
1366   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1367   {
1368     address_word vaddr = ((unsigned64)op1 + offset);
1369     address_word paddr;
1370     int uncached;
1371     if ((vaddr & 7) != 0)
1372       SignalExceptionAddressLoad();
1373     else
1374       {
1375         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1376           {
1377             unsigned64 memval = 0;
1378             unsigned64 memval1 = 0;
1379             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
1380             GPR[destreg] = memval;
1381           }
1382       }
1383   }
1384 }
1385
1386
1387 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
1388 "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1389 *mipsII:
1390 *mipsIII:
1391 *mipsIV:
1392 *vr5000:
1393 // start-sanitize-vr5400
1394 *vr5400:
1395 // end-sanitize-vr5400
1396 // start-sanitize-r5900
1397 *r5900:
1398 // end-sanitize-r5900
1399 *r3900:
1400 // start-sanitize-tx19
1401 *tx19:
1402 // end-sanitize-tx19
1403 {
1404   unsigned32 instruction = instruction_0;
1405   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1406   int destreg = ((instruction >> 16) & 0x0000001F);
1407   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1408   {
1409     address_word vaddr = ((unsigned64)op1 + offset);
1410     address_word paddr;
1411     int uncached;
1412     if ((vaddr & 7) != 0)
1413       SignalExceptionAddressLoad();
1414     else
1415       {
1416         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1417           {
1418             unsigned64 memval = 0;
1419             unsigned64 memval1 = 0;
1420             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
1421             COP_LD(((instruction >> 26) & 0x3),destreg,memval);;
1422           }
1423       }
1424   }
1425 }
1426
1427
1428 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
1429 "ldl r<RT>, <OFFSET>(r<BASE>)"
1430 *mipsIII:
1431 *mipsIV:
1432 *vr5000:
1433 // start-sanitize-vr5400
1434 *vr5400:
1435 // end-sanitize-vr5400
1436 // start-sanitize-r5900
1437 *r5900:
1438 // end-sanitize-r5900
1439 *r3900:
1440 // start-sanitize-tx19
1441 *tx19:
1442 // end-sanitize-tx19
1443 {
1444   unsigned32 instruction = instruction_0;
1445   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1446   int destreg = ((instruction >> 16) & 0x0000001F);
1447   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1448   {
1449     address_word vaddr = ((unsigned64)op1 + offset);
1450     address_word paddr;
1451     int uncached;
1452     {
1453       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1454         {
1455           unsigned64 memval = 0;
1456           unsigned64 memval1 = 0;
1457           unsigned64 mask = 7;
1458           unsigned int reverse = (ReverseEndian ? mask : 0);
1459           unsigned int bigend = (BigEndianCPU ? mask : 0);
1460           int byte;
1461           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
1462           byte = ((vaddr & mask) ^ bigend);
1463           if (!BigEndianMem)
1464             paddr &= ~mask;
1465           LoadMemory(&memval,&memval1,uncached,byte,paddr,vaddr,isDATA,isREAL);
1466           GPR[destreg] = ((memval << ((7 - byte) * 8)) | (GPR[destreg] & (((unsigned64)1 << ((7 - byte) * 8)) - 1)));
1467         }
1468     }
1469   }
1470 }
1471
1472
1473 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
1474 "ldr r<RT>, <OFFSET>(r<BASE>)"
1475 *mipsIII:
1476 *mipsIV:
1477 *vr5000:
1478 // start-sanitize-vr5400
1479 *vr5400:
1480 // end-sanitize-vr5400
1481 // start-sanitize-r5900
1482 *r5900:
1483 // end-sanitize-r5900
1484 *r3900:
1485 // start-sanitize-tx19
1486 *tx19:
1487 // end-sanitize-tx19
1488 {
1489   unsigned32 instruction = instruction_0;
1490   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1491   int destreg = ((instruction >> 16) & 0x0000001F);
1492   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1493   {
1494     address_word vaddr = ((unsigned64)op1 + offset);
1495     address_word paddr;
1496     int uncached;
1497     {
1498       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1499         {
1500           unsigned64 memval = 0;
1501           unsigned64 memval1 = 0;
1502           unsigned64 mask = 7;
1503           unsigned int reverse = (ReverseEndian ? mask : 0);
1504           unsigned int bigend = (BigEndianCPU ? mask : 0);
1505           int byte;
1506           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
1507           byte = ((vaddr & mask) ^ bigend);
1508           if (BigEndianMem)
1509             paddr &= ~mask;
1510           LoadMemory(&memval,&memval1,uncached,(7 - byte),paddr,vaddr,isDATA,isREAL);
1511           {
1512             unsigned64 srcmask;
1513             if (byte == 0)
1514               srcmask = 0;
1515             else
1516               srcmask = ((unsigned64)-1 << (8 * (8 - byte)));
1517             GPR[destreg] = ((GPR[destreg] & srcmask) | (memval >> (8 * byte)));
1518           }
1519         }
1520     }
1521   }
1522 }
1523
1524
1525 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
1526 "lh r<RT>, <OFFSET>(r<BASE>)"
1527 *mipsI,mipsII,mipsIII,mipsIV:
1528 *vr5000:
1529 // start-sanitize-vr5400
1530 *vr5400:
1531 // end-sanitize-vr5400
1532 // start-sanitize-r5900
1533 *r5900:
1534 // end-sanitize-r5900
1535 *r3900:
1536 // start-sanitize-tx19
1537 *tx19:
1538 // end-sanitize-tx19
1539 {
1540   unsigned32 instruction = instruction_0;
1541   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1542   int destreg = ((instruction >> 16) & 0x0000001F);
1543   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1544   {
1545     address_word vaddr = ((unsigned64)op1 + offset);
1546     address_word paddr;
1547     int uncached;
1548     if ((vaddr & 1) != 0)
1549       SignalExceptionAddressLoad();
1550     else
1551       {
1552         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1553           {
1554             unsigned64 memval = 0;
1555             unsigned64 memval1 = 0;
1556             unsigned64 mask = 0x7;
1557             unsigned int shift = 1;
1558             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1559             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1560             unsigned int byte;
1561             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1562             LoadMemory(&memval,&memval1,uncached,AccessLength_HALFWORD,paddr,vaddr,isDATA,isREAL);
1563             byte = ((vaddr & mask) ^ (bigend << shift));
1564             GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0x0000FFFF),16));
1565           }
1566       }
1567   }
1568 }
1569
1570
1571 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
1572 "lhu r<RT>, <OFFSET>(r<BASE>)"
1573 *mipsI,mipsII,mipsIII,mipsIV:
1574 *vr5000:
1575 // start-sanitize-vr5400
1576 *vr5400:
1577 // end-sanitize-vr5400
1578 // start-sanitize-r5900
1579 *r5900:
1580 // end-sanitize-r5900
1581 *r3900:
1582 // start-sanitize-tx19
1583 *tx19:
1584 // end-sanitize-tx19
1585 {
1586   unsigned32 instruction = instruction_0;
1587   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1588   int destreg = ((instruction >> 16) & 0x0000001F);
1589   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1590   {
1591     address_word vaddr = ((unsigned64)op1 + offset);
1592     address_word paddr;
1593     int uncached;
1594     if ((vaddr & 1) != 0)
1595       SignalExceptionAddressLoad();
1596     else
1597       {
1598         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1599           {
1600             unsigned64 memval = 0;
1601             unsigned64 memval1 = 0;
1602             unsigned64 mask = 0x7;
1603             unsigned int shift = 1;
1604             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1605             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1606             unsigned int byte;
1607             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1608             LoadMemory(&memval,&memval1,uncached,AccessLength_HALFWORD,paddr,vaddr,isDATA,isREAL);
1609             byte = ((vaddr & mask) ^ (bigend << shift));
1610             GPR[destreg] = (((memval >> (8 * byte)) & 0x0000FFFF));
1611           }
1612       }
1613   }
1614 }
1615
1616
1617 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
1618 "ll r<RT>, <OFFSET>(r<BASE>)"
1619 *mipsII:
1620 *mipsIII:
1621 *mipsIV:
1622 *vr5000:
1623 // start-sanitize-vr5400
1624 *vr5400:
1625 // end-sanitize-vr5400
1626 // start-sanitize-r5900
1627 *r5900:
1628 // end-sanitize-r5900
1629 *r3900:
1630 // start-sanitize-tx19
1631 *tx19:
1632 // end-sanitize-tx19
1633 {
1634   unsigned32 instruction = instruction_0;
1635   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1636   int destreg = ((instruction >> 16) & 0x0000001F);
1637   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1638   {
1639     address_word vaddr = ((unsigned64)op1 + offset);
1640     address_word paddr;
1641     int uncached;
1642     if ((vaddr & 3) != 0)
1643       SignalExceptionAddressLoad();
1644     else
1645       {
1646         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1647           {
1648             unsigned64 memval = 0;
1649             unsigned64 memval1 = 0;
1650             unsigned64 mask = 0x7;
1651             unsigned int shift = 2;
1652             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1653             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1654             unsigned int byte;
1655             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1656             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
1657             byte = ((vaddr & mask) ^ (bigend << shift));
1658             GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
1659             LLBIT = 1;
1660           }
1661       }
1662   }
1663 }
1664
1665
1666 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
1667 "lld r<RT>, <OFFSET>(r<BASE>)"
1668 *mipsIII:
1669 *mipsIV:
1670 *vr5000:
1671 // start-sanitize-vr5400
1672 *vr5400:
1673 // end-sanitize-vr5400
1674 // start-sanitize-r5900
1675 *r5900:
1676 // end-sanitize-r5900
1677 *r3900:
1678 // start-sanitize-tx19
1679 *tx19:
1680 // end-sanitize-tx19
1681 {
1682   unsigned32 instruction = instruction_0;
1683   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1684   int destreg = ((instruction >> 16) & 0x0000001F);
1685   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1686   {
1687     address_word vaddr = ((unsigned64)op1 + offset);
1688     address_word paddr;
1689     int uncached;
1690     if ((vaddr & 7) != 0)
1691       SignalExceptionAddressLoad();
1692     else
1693       {
1694         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1695           {
1696             unsigned64 memval = 0;
1697             unsigned64 memval1 = 0;
1698             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
1699             GPR[destreg] = memval;
1700             LLBIT = 1;
1701           }
1702       }
1703   }
1704 }
1705
1706
1707 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
1708 "lui r<RT>, <IMMEDIATE>"
1709 *mipsI,mipsII,mipsIII,mipsIV:
1710 *vr5000:
1711 // start-sanitize-vr5400
1712 *vr5400:
1713 // end-sanitize-vr5400
1714 // start-sanitize-r5900
1715 *r5900:
1716 // end-sanitize-r5900
1717 *r3900:
1718 // start-sanitize-tx19
1719 *tx19:
1720 // end-sanitize-tx19
1721 {
1722   GPR[RT] = EXTEND32 (IMMEDIATE << 16);
1723 }
1724
1725
1726 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
1727 "lw r<RT>, <OFFSET>(r<BASE>)"
1728 *mipsI,mipsII,mipsIII,mipsIV:
1729 *vr5000:
1730 // start-sanitize-vr5400
1731 *vr5400:
1732 // end-sanitize-vr5400
1733 // start-sanitize-r5900
1734 *r5900:
1735 // end-sanitize-r5900
1736 *r3900:
1737 // start-sanitize-tx19
1738 *tx19:
1739 // end-sanitize-tx19
1740 {
1741   unsigned32 instruction = instruction_0;
1742   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1743   int destreg = ((instruction >> 16) & 0x0000001F);
1744   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1745   {
1746     address_word vaddr = ((unsigned64)op1 + offset);
1747     address_word paddr;
1748     int uncached;
1749     if ((vaddr & 3) != 0)
1750       SignalExceptionAddressLoad();
1751     else
1752       {
1753         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1754           {
1755             unsigned64 memval = 0;
1756             unsigned64 memval1 = 0;
1757             unsigned64 mask = 0x7;
1758             unsigned int shift = 2;
1759             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1760             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1761             unsigned int byte;
1762             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1763             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
1764             byte = ((vaddr & mask) ^ (bigend << shift));
1765             GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
1766           }
1767       }
1768   }
1769 }
1770
1771
1772 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
1773 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1774 *mipsI,mipsII,mipsIII,mipsIV:
1775 *vr5000:
1776 // start-sanitize-vr5400
1777 *vr5400:
1778 // end-sanitize-vr5400
1779 // start-sanitize-r5900
1780 *r5900:
1781 // end-sanitize-r5900
1782 *r3900:
1783 // start-sanitize-tx19
1784 *tx19:
1785 // end-sanitize-tx19
1786 {
1787   unsigned32 instruction = instruction_0;
1788   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1789   int destreg = ((instruction >> 16) & 0x0000001F);
1790   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1791   {
1792     address_word vaddr = ((unsigned64)op1 + offset);
1793     address_word paddr;
1794     int uncached;
1795     if ((vaddr & 3) != 0)
1796       SignalExceptionAddressLoad();
1797     else
1798       {
1799         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1800           {
1801             unsigned64 memval = 0;
1802             unsigned64 memval1 = 0;
1803             unsigned64 mask = 0x7;
1804             unsigned int shift = 2;
1805             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1806             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1807             unsigned int byte;
1808             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1809             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
1810             byte = ((vaddr & mask) ^ (bigend << shift));
1811             COP_LW(((instruction >> 26) & 0x3),destreg,(unsigned int)((memval >> (8 * byte)) & 0xFFFFFFFF));
1812           }
1813       }
1814   }
1815 }
1816
1817
1818 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
1819 "lwl r<RT>, <OFFSET>(r<BASE>)"
1820 *mipsI,mipsII,mipsIII,mipsIV:
1821 *vr5000:
1822 // start-sanitize-vr5400
1823 *vr5400:
1824 // end-sanitize-vr5400
1825 // start-sanitize-r5900
1826 *r5900:
1827 // end-sanitize-r5900
1828 *r3900:
1829 // start-sanitize-tx19
1830 *tx19:
1831 // end-sanitize-tx19
1832 {
1833   unsigned32 instruction = instruction_0;
1834   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1835   int destreg = ((instruction >> 16) & 0x0000001F);
1836   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1837   {
1838     address_word vaddr = ((unsigned64)op1 + offset);
1839     address_word paddr;
1840     int uncached;
1841     {
1842       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1843         {
1844           unsigned64 memval = 0;
1845           unsigned64 memval1 = 0;
1846           unsigned64 mask = 3;
1847           unsigned int reverse = (ReverseEndian ? mask : 0);
1848           unsigned int bigend = (BigEndianCPU ? mask : 0);
1849           int byte;
1850           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
1851           byte = ((vaddr & mask) ^ bigend);
1852           if (!BigEndianMem)
1853             paddr &= ~mask;
1854           LoadMemory(&memval,&memval1,uncached,byte,paddr,vaddr,isDATA,isREAL);
1855           if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
1856             memval >>= 32;
1857           }
1858           GPR[destreg] = ((memval << ((3 - byte) * 8)) | (GPR[destreg] & (((unsigned64)1 << ((3 - byte) * 8)) - 1)));
1859           GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
1860         }
1861     }
1862   }
1863 }
1864
1865
1866 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
1867 "lwr r<RT>, <OFFSET>(r<BASE>)"
1868 *mipsI,mipsII,mipsIII,mipsIV:
1869 *vr5000:
1870 // start-sanitize-vr5400
1871 *vr5400:
1872 // end-sanitize-vr5400
1873 // start-sanitize-r5900
1874 *r5900:
1875 // end-sanitize-r5900
1876 *r3900:
1877 // start-sanitize-tx19
1878 *tx19:
1879 // end-sanitize-tx19
1880 {
1881   unsigned32 instruction = instruction_0;
1882   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1883   int destreg = ((instruction >> 16) & 0x0000001F);
1884   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1885   {
1886     address_word vaddr = ((unsigned64)op1 + offset);
1887     address_word paddr;
1888     int uncached;
1889     {
1890       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1891         {
1892           unsigned64 memval = 0;
1893           unsigned64 memval1 = 0;
1894           unsigned64 mask = 3;
1895           unsigned int reverse = (ReverseEndian ? mask : 0);
1896           unsigned int bigend = (BigEndianCPU ? mask : 0);
1897           int byte;
1898           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
1899           byte = ((vaddr & mask) ^ bigend);
1900           if (BigEndianMem)
1901             paddr &= ~mask;
1902           LoadMemory(&memval,&memval1,uncached,(3 - byte),paddr,vaddr,isDATA,isREAL);
1903           if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
1904             memval >>= 32;
1905           }
1906           {
1907             unsigned64 srcmask;
1908             if (byte == 0)
1909               srcmask = 0;
1910             else
1911               srcmask = ((unsigned64)-1 << (8 * (4 - byte)));
1912             GPR[destreg] = ((GPR[destreg] & srcmask) | (memval >> (8 * byte)));
1913           }
1914           GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
1915         }
1916     }
1917   }
1918 }
1919
1920
1921 100111,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWU
1922 "lwu r<RT>, <OFFSET>(r<BASE>)"
1923 *mipsIII:
1924 *mipsIV:
1925 *vr5000:
1926 // start-sanitize-vr5400
1927 *vr5400:
1928 // end-sanitize-vr5400
1929 // start-sanitize-r5900
1930 *r5900:
1931 // end-sanitize-r5900
1932 *r3900:
1933 // start-sanitize-tx19
1934 *tx19:
1935 // end-sanitize-tx19
1936 {
1937   unsigned32 instruction = instruction_0;
1938   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1939   int destreg = ((instruction >> 16) & 0x0000001F);
1940   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1941   {
1942     address_word vaddr = ((unsigned64)op1 + offset);
1943     address_word paddr;
1944     int uncached;
1945     if ((vaddr & 3) != 0)
1946       SignalExceptionAddressLoad();
1947     else
1948       {
1949         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1950           {
1951             unsigned64 memval = 0;
1952             unsigned64 memval1 = 0;
1953             unsigned64 mask = 0x7;
1954             unsigned int shift = 2;
1955             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1956             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1957             unsigned int byte;
1958             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1959             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
1960             byte = ((vaddr & mask) ^ (bigend << shift));
1961             GPR[destreg] = (((memval >> (8 * byte)) & 0xFFFFFFFF));
1962           }
1963       }
1964   }
1965 }
1966
1967
1968 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
1969 "mfhi r<RD>"
1970 *mipsI,mipsII,mipsIII,mipsIV:
1971 *vr5000:
1972 // start-sanitize-vr5400
1973 *vr5400:
1974 // end-sanitize-vr5400
1975 // start-sanitize-r5900
1976 *r5900:
1977 // end-sanitize-r5900
1978 *r3900:
1979 // start-sanitize-tx19
1980 *tx19:
1981 // end-sanitize-tx19
1982 {
1983   GPR[RD] = HI;
1984 #if 0
1985   HIACCESS = 3;
1986 #endif
1987 }
1988
1989
1990 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
1991 "mflo r<RD>"
1992 *mipsI,mipsII,mipsIII,mipsIV:
1993 *vr5000:
1994 // start-sanitize-vr5400
1995 *vr5400:
1996 // end-sanitize-vr5400
1997 // start-sanitize-r5900
1998 *r5900:
1999 // end-sanitize-r5900
2000 *r3900:
2001 // start-sanitize-tx19
2002 *tx19:
2003 // end-sanitize-tx19
2004 {
2005   GPR[RD] = LO;
2006 #if 0
2007   LOACCESS = 3; /* 3rd instruction will be safe */
2008 #endif
2009 }
2010
2011
2012 000000,5.RS,5.RT,5.RD,00000001011:SPECIAL:32::MOVN
2013 "movn r<RD>, r<RS>, r<RT>"
2014 *mipsIV:
2015 *vr5000:
2016 // start-sanitize-vr5400
2017 *vr5400:
2018 // end-sanitize-vr5400
2019 // start-sanitize-r5900
2020 *r5900:
2021 // end-sanitize-r5900
2022 {
2023   if (GPR[RT] != 0)
2024     GPR[RD] = GPR[RS];
2025 }
2026
2027
2028 000000,5.RS,5.RT,5.RD,00000001010:SPECIAL:32::MOVZ
2029 "movz r<RD>, r<RS>, r<RT>"
2030 *mipsIV:
2031 *vr5000:
2032 // start-sanitize-vr5400
2033 *vr5400:
2034 // end-sanitize-vr5400
2035 // start-sanitize-r5900
2036 *r5900:
2037 // end-sanitize-r5900
2038 {
2039   if (GPR[RT] == 0)
2040     GPR[RD] = GPR[RS];
2041 }
2042
2043
2044 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
2045 "mthi r<RS>"
2046 *mipsI,mipsII,mipsIII,mipsIV:
2047 *vr5000:
2048 // start-sanitize-vr5400
2049 *vr5400:
2050 // end-sanitize-vr5400
2051 // start-sanitize-r5900
2052 *r5900:
2053 // end-sanitize-r5900
2054 *r3900:
2055 // start-sanitize-tx19
2056 *tx19:
2057 // end-sanitize-tx19
2058 {
2059 #if 0
2060   if (HIACCESS != 0)
2061     sim_io_eprintf (sd, "MT (move-to) over-writing HI register value\n");
2062 #endif
2063   HI = GPR[RS];
2064 #if 0
2065   HIACCESS = 3; /* 3rd instruction will be safe */
2066 #endif
2067 }
2068
2069
2070 000000,5.RS,000000000000000010011:SPECIAL:32::MTLO
2071 "mtlo r<RS>"
2072 *mipsI,mipsII,mipsIII,mipsIV:
2073 *vr5000:
2074 // start-sanitize-vr5400
2075 *vr5400:
2076 // end-sanitize-vr5400
2077 // start-sanitize-r5900
2078 *r5900:
2079 // end-sanitize-r5900
2080 *r3900:
2081 // start-sanitize-tx19
2082 *tx19:
2083 // end-sanitize-tx19
2084 {
2085 #if 0
2086   if (LOACCESS != 0)
2087     sim_io_eprintf (sd, "MT (move-to) over-writing LO register value\n");
2088 #endif
2089   LO = GPR[RS];
2090 #if 0
2091   LOACCESS = 3; /* 3rd instruction will be safe */
2092 #endif
2093 }
2094
2095
2096 000000,5.RS,5.RT,00000,00000011000:SPECIAL:32::MULT
2097 "mult r<RS>, r<RT>"
2098 *mipsI,mipsII,mipsIII,mipsIV:
2099 {
2100   signed64 prod;
2101   CHECKHILO ("Multiplication");
2102   prod = (((signed64)(signed32) GPR[RS])
2103           * ((signed64)(signed32) GPR[RT]));
2104   LO = EXTEND32 (VL4_8 (prod));
2105   HI = EXTEND32 (VH4_8 (prod));
2106 }
2107 000000,5.RS,5.RT,5.RD,00000011000:SPECIAL:32::MULT
2108 "mult r<RD>, r<RS>, r<RT>"
2109 *vr5000:
2110 // start-sanitize-vr5400
2111 *vr5400:
2112 // end-sanitize-vr5400
2113 // start-sanitize-r5900
2114 *r5900:
2115 // end-sanitize-r5900
2116 *r3900:
2117 // start-sanitize-tx19
2118 *tx19:
2119 // end-sanitize-tx19
2120 {
2121   signed64 prod;
2122   CHECKHILO ("Multiplication");
2123   prod = (((signed64)(signed32) GPR[RS])
2124           * ((signed64)(signed32) GPR[RT]));
2125   LO = EXTEND32 (VL4_8 (prod));
2126   HI = EXTEND32 (VH4_8 (prod));
2127   if (RD != 0)
2128     GPR[RD] = LO;
2129 }
2130
2131
2132 000000,5.RS,5.RT,00000,00000011001:SPECIAL:32::MULTU
2133 "multu r<RS>, r<RT>"
2134 *mipsI,mipsII,mipsIII,mipsIV:
2135 {
2136   unsigned64 prod;
2137   CHECKHILO ("Multiplication");
2138   prod = (((unsigned64)(unsigned32) GPR[RS])
2139           * ((unsigned64)(unsigned32) GPR[RT]));
2140   LO = EXTEND32 (VL4_8 (prod));
2141   HI = EXTEND32 (VH4_8 (prod));
2142 }
2143 000000,5.RS,5.RT,5.RD,00000011001:SPECIAL:32::MULTU
2144 "multu r<RD>, r<RS>, r<RT>"
2145 *vr5000:
2146 // start-sanitize-vr5400
2147 *vr5400:
2148 // end-sanitize-vr5400
2149 // start-sanitize-r5900
2150 *r5900:
2151 // end-sanitize-r5900
2152 *r3900:
2153 // start-sanitize-tx19
2154 *tx19:
2155 // end-sanitize-tx19
2156 {
2157   unsigned64 prod;
2158   CHECKHILO ("Multiplication");
2159   prod = (((unsigned64)(unsigned32) GPR[RS])
2160           * ((unsigned64)(unsigned32) GPR[RT]));
2161   LO = EXTEND32 (VL4_8 (prod));
2162   HI = EXTEND32 (VH4_8 (prod));
2163   if (RD != 0)
2164     GPR[RD] = LO;
2165 }
2166
2167
2168 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
2169 "nor r<RD>, r<RS>, r<RT>"
2170 *mipsI,mipsII,mipsIII,mipsIV:
2171 *vr5000:
2172 // start-sanitize-vr5400
2173 *vr5400:
2174 // end-sanitize-vr5400
2175 // start-sanitize-r5900
2176 *r5900:
2177 // end-sanitize-r5900
2178 *r3900:
2179 // start-sanitize-tx19
2180 *tx19:
2181 // end-sanitize-tx19
2182 {
2183   GPR[RD] = ~ (GPR[RS] | GPR[RT]);
2184 }
2185
2186
2187 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
2188 "or r<RD>, r<RS>, r<RT>"
2189 *mipsI,mipsII,mipsIII,mipsIV:
2190 *vr5000:
2191 // start-sanitize-vr5400
2192 *vr5400:
2193 // end-sanitize-vr5400
2194 // start-sanitize-r5900
2195 *r5900:
2196 // end-sanitize-r5900
2197 *r3900:
2198 // start-sanitize-tx19
2199 *tx19:
2200 // end-sanitize-tx19
2201 {
2202   GPR[RD] = (GPR[RS] | GPR[RT]);
2203 }
2204
2205
2206 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
2207 "ori r<RT>, r<RS>, <IMMEDIATE>"
2208 *mipsI,mipsII,mipsIII,mipsIV:
2209 *vr5000:
2210 // start-sanitize-vr5400
2211 *vr5400:
2212 // end-sanitize-vr5400
2213 // start-sanitize-r5900
2214 *r5900:
2215 // end-sanitize-r5900
2216 *r3900:
2217 // start-sanitize-tx19
2218 *tx19:
2219 // end-sanitize-tx19
2220 {
2221   GPR[RT] = (GPR[RS] | IMMEDIATE);
2222 }
2223
2224
2225 110011,5.RS,nnnnn,16.OFFSET:NORMAL:32::PREF
2226 *mipsIV:
2227 *vr5000:
2228 // start-sanitize-vr5400
2229 *vr5400:
2230 // end-sanitize-vr5400
2231 // start-sanitize-r5900
2232 *r5900:
2233 // end-sanitize-r5900
2234 {
2235   unsigned32 instruction = instruction_0;
2236   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2237   int hint = ((instruction >> 16) & 0x0000001F);
2238   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2239   {
2240     address_word vaddr = ((unsigned64)op1 + offset);
2241     address_word paddr;
2242     int uncached;
2243     {
2244       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2245         Prefetch(uncached,paddr,vaddr,isDATA,hint);
2246     }
2247   }
2248 }
2249
2250 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
2251 "sb r<RT>, <OFFSET>(r<BASE>)"
2252 *mipsI,mipsII,mipsIII,mipsIV:
2253 *vr5000:
2254 // start-sanitize-vr5400
2255 *vr5400:
2256 // end-sanitize-vr5400
2257 // start-sanitize-r5900
2258 *r5900:
2259 // end-sanitize-r5900
2260 *r3900:
2261 // start-sanitize-tx19
2262 *tx19:
2263 // end-sanitize-tx19
2264 {
2265   unsigned32 instruction = instruction_0;
2266   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2267   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2268   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2269   {
2270     address_word vaddr = ((unsigned64)op1 + offset);
2271     address_word paddr;
2272     int uncached;
2273     {
2274       if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2275         {
2276           unsigned64 memval = 0;
2277           unsigned64 memval1 = 0;
2278           unsigned64 mask = 0x7;
2279           unsigned int shift = 0;
2280           unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2281           unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2282           unsigned int byte;
2283           paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2284           byte = ((vaddr & mask) ^ (bigend << shift));
2285           memval = ((unsigned64) op2 << (8 * byte));
2286           {
2287             StoreMemory(uncached,AccessLength_BYTE,memval,memval1,paddr,vaddr,isREAL);
2288           }
2289         }
2290     }
2291   }
2292 }
2293
2294
2295 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
2296 "sc r<RT>, <OFFSET>(r<BASE>)"
2297 *mipsII:
2298 *mipsIII:
2299 *mipsIV:
2300 *vr5000:
2301 // start-sanitize-vr5400
2302 *vr5400:
2303 // end-sanitize-vr5400
2304 // start-sanitize-r5900
2305 *r5900:
2306 // end-sanitize-r5900
2307 *r3900:
2308 // start-sanitize-tx19
2309 *tx19:
2310 // end-sanitize-tx19
2311 {
2312   unsigned32 instruction = instruction_0;
2313   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2314   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2315   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2316   {
2317     address_word vaddr = ((unsigned64)op1 + offset);
2318     address_word paddr;
2319     int uncached;
2320     if ((vaddr & 3) != 0)
2321       SignalExceptionAddressStore();
2322     else
2323       {
2324         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2325           {
2326             unsigned64 memval = 0;
2327             unsigned64 memval1 = 0;
2328             unsigned64 mask = 0x7;
2329             unsigned int byte;
2330             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2331             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2332             memval = ((unsigned64) op2 << (8 * byte));
2333             if (LLBIT)
2334               {
2335                 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2336               }
2337             GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2338           }
2339       }
2340   }
2341 }
2342
2343
2344 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
2345 "scd r<RT>, <OFFSET>(r<BASE>)"
2346 *mipsIII:
2347 *mipsIV:
2348 *vr5000:
2349 // start-sanitize-vr5400
2350 *vr5400:
2351 // end-sanitize-vr5400
2352 // start-sanitize-r5900
2353 *r5900:
2354 // end-sanitize-r5900
2355 *r3900:
2356 // start-sanitize-tx19
2357 *tx19:
2358 // end-sanitize-tx19
2359 {
2360   unsigned32 instruction = instruction_0;
2361   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2362   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2363   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2364   {
2365     address_word vaddr = ((unsigned64)op1 + offset);
2366     address_word paddr;
2367     int uncached;
2368     if ((vaddr & 7) != 0)
2369       SignalExceptionAddressStore();
2370     else
2371       {
2372         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2373           {
2374             unsigned64 memval = 0;
2375             unsigned64 memval1 = 0;
2376             memval = op2;
2377             if (LLBIT)
2378               {
2379                 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2380               }
2381             GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2382           }
2383       }
2384   }
2385 }
2386
2387
2388 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
2389 "sd r<RT>, <OFFSET>(r<BASE>)"
2390 *mipsIII:
2391 *mipsIV:
2392 *vr5000:
2393 // start-sanitize-vr5400
2394 *vr5400:
2395 // end-sanitize-vr5400
2396 // start-sanitize-r5900
2397 *r5900:
2398 // end-sanitize-r5900
2399 *r3900:
2400 // start-sanitize-tx19
2401 *tx19:
2402 // end-sanitize-tx19
2403 {
2404   unsigned32 instruction = instruction_0;
2405   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2406   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2407   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2408   {
2409     address_word vaddr = ((unsigned64)op1 + offset);
2410     address_word paddr;
2411     int uncached;
2412     if ((vaddr & 7) != 0)
2413       SignalExceptionAddressStore();
2414     else
2415       {
2416         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2417           {
2418             unsigned64 memval = 0;
2419             unsigned64 memval1 = 0;
2420             memval = op2;
2421             {
2422               StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2423             }
2424           }
2425       }
2426   }
2427 }
2428
2429
2430 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
2431 "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2432 *mipsII:
2433 *mipsIII:
2434 *mipsIV:
2435 *vr5000:
2436 // start-sanitize-vr5400
2437 *vr5400:
2438 // end-sanitize-vr5400
2439 // start-sanitize-r5900
2440 *r5900:
2441 // end-sanitize-r5900
2442 *r3900:
2443 // start-sanitize-tx19
2444 *tx19:
2445 // end-sanitize-tx19
2446 {
2447   unsigned32 instruction = instruction_0;
2448   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2449   int destreg = ((instruction >> 16) & 0x0000001F);
2450   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2451   {
2452     address_word vaddr = ((unsigned64)op1 + offset);
2453     address_word paddr;
2454     int uncached;
2455     if ((vaddr & 7) != 0)
2456       SignalExceptionAddressStore();
2457     else
2458       {
2459         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2460           {
2461             unsigned64 memval = 0;
2462             unsigned64 memval1 = 0;
2463             memval = (unsigned64)COP_SD(((instruction >> 26) & 0x3),destreg);
2464             {
2465               StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2466             }
2467           }
2468       }
2469   }
2470 }
2471
2472
2473 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
2474 "sdl r<RT>, <OFFSET>(r<BASE>)"
2475 *mipsIII:
2476 *mipsIV:
2477 *vr5000:
2478 // start-sanitize-vr5400
2479 *vr5400:
2480 // end-sanitize-vr5400
2481 // start-sanitize-r5900
2482 *r5900:
2483 // end-sanitize-r5900
2484 *r3900:
2485 // start-sanitize-tx19
2486 *tx19:
2487 // end-sanitize-tx19
2488 {
2489   unsigned32 instruction = instruction_0;
2490   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2491   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2492   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2493   {
2494     address_word vaddr = ((unsigned64)op1 + offset);
2495     address_word paddr;
2496     int uncached;
2497     {
2498       if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2499         {
2500           unsigned64 memval = 0;
2501           unsigned64 memval1 = 0;
2502           unsigned64 mask = 7;
2503           unsigned int reverse = (ReverseEndian ? mask : 0);
2504           unsigned int bigend = (BigEndianCPU ? mask : 0);
2505           int byte;
2506           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
2507           byte = ((vaddr & mask) ^ bigend);
2508           if (!BigEndianMem)
2509             paddr &= ~mask;
2510           memval = (op2 >> (8 * (7 - byte)));
2511           StoreMemory(uncached,byte,memval,memval1,paddr,vaddr,isREAL);
2512         }
2513     }
2514   }
2515 }
2516
2517
2518 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
2519 "sdr r<RT>, <OFFSET>(r<BASE>)"
2520 *mipsIII:
2521 *mipsIV:
2522 *vr5000:
2523 // start-sanitize-vr5400
2524 *vr5400:
2525 // end-sanitize-vr5400
2526 // start-sanitize-r5900
2527 *r5900:
2528 // end-sanitize-r5900
2529 *r3900:
2530 // start-sanitize-tx19
2531 *tx19:
2532 // end-sanitize-tx19
2533 {
2534   address_word paddr;
2535   int uncached;
2536   unsigned64 memval;
2537   unsigned64 mask = 7;
2538   unsigned int reverse = (ReverseEndian ? mask : 0);
2539   unsigned int bigend = (BigEndianCPU ? mask : 0);
2540   int byte;
2541   address_word vaddr = (GPR[BASE] + EXTEND16 (OFFSET));
2542   AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL);
2543   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
2544   if (BigEndianMem)
2545     paddr &= ~mask;
2546   byte = ((vaddr & mask) ^ bigend);
2547   memval = (GPR[RT] << (byte * 8));
2548   StoreMemory(uncached,(AccessLength_DOUBLEWORD - byte),memval,0,paddr,vaddr,isREAL);
2549 }
2550
2551
2552 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
2553 "sh r<RT>, <OFFSET>(r<BASE>)"
2554 *mipsI,mipsII,mipsIII,mipsIV:
2555 *vr5000:
2556 // start-sanitize-vr5400
2557 *vr5400:
2558 // end-sanitize-vr5400
2559 // start-sanitize-r5900
2560 *r5900:
2561 // end-sanitize-r5900
2562 *r3900:
2563 // start-sanitize-tx19
2564 *tx19:
2565 // end-sanitize-tx19
2566 {
2567   unsigned32 instruction = instruction_0;
2568   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2569   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2570   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2571   {
2572     address_word vaddr = ((unsigned64)op1 + offset);
2573     address_word paddr;
2574     int uncached;
2575     if ((vaddr & 1) != 0)
2576       SignalExceptionAddressStore();
2577     else
2578       {
2579         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2580           {
2581             unsigned64 memval = 0;
2582             unsigned64 memval1 = 0;
2583             unsigned64 mask = 0x7;
2584             unsigned int shift = 1;
2585             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2586             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2587             unsigned int byte;
2588             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2589             byte = ((vaddr & mask) ^ (bigend << shift));
2590             memval = ((unsigned64) op2 << (8 * byte));
2591             {
2592               StoreMemory(uncached,AccessLength_HALFWORD,memval,memval1,paddr,vaddr,isREAL);
2593             }
2594           }
2595       }
2596   }
2597 }
2598
2599
2600 00000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
2601 "sll r<RD>, r<RT>, <SHIFT>"
2602 *mipsI,mipsII,mipsIII,mipsIV:
2603 *vr5000:
2604 // start-sanitize-vr5400
2605 *vr5400:
2606 // end-sanitize-vr5400
2607 // start-sanitize-r5900
2608 *r5900:
2609 // end-sanitize-r5900
2610 *r3900:
2611 // start-sanitize-tx19
2612 *tx19:
2613 // end-sanitize-tx19
2614 {
2615   int s = SHIFT;
2616   unsigned32 temp = (GPR[RT] << s);
2617   GPR[RD] = EXTEND32 (temp);
2618 }
2619
2620
2621 000000,5.RS,5.RT,5.RD,00000000100:SPECIAL:32::SLLV
2622 "sllv r<RD>, r<RT>, r<RS>"
2623 *mipsI,mipsII,mipsIII,mipsIV:
2624 *vr5000:
2625 // start-sanitize-vr5400
2626 *vr5400:
2627 // end-sanitize-vr5400
2628 // start-sanitize-r5900
2629 *r5900:
2630 // end-sanitize-r5900
2631 *r3900:
2632 // start-sanitize-tx19
2633 *tx19:
2634 // end-sanitize-tx19
2635 {
2636   int s = MASKED (GPR[RS], 4, 0);
2637   unsigned32 temp = (GPR[RT] << s);
2638   GPR[RD] = EXTEND32 (temp);
2639 }
2640
2641
2642 000000,5.RS,5.RT,5.RD,00000101010:SPECIAL:32::SLT
2643 "slt r<RD>, r<RS>, r<RT>"
2644 *mipsI,mipsII,mipsIII,mipsIV:
2645 *vr5000:
2646 // start-sanitize-vr5400
2647 *vr5400:
2648 // end-sanitize-vr5400
2649 // start-sanitize-r5900
2650 *r5900:
2651 // end-sanitize-r5900
2652 *r3900:
2653 // start-sanitize-tx19
2654 *tx19:
2655 // end-sanitize-tx19
2656 {
2657   GPR[RD] = ((signed_word) GPR[RS] < (signed_word) GPR[RT]);
2658 }
2659
2660
2661 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
2662 "slti r<RT>, r<RS>, <IMMEDIATE>"
2663 *mipsI,mipsII,mipsIII,mipsIV:
2664 *vr5000:
2665 // start-sanitize-vr5400
2666 *vr5400:
2667 // end-sanitize-vr5400
2668 // start-sanitize-r5900
2669 *r5900:
2670 // end-sanitize-r5900
2671 *r3900:
2672 // start-sanitize-tx19
2673 *tx19:
2674 // end-sanitize-tx19
2675 {
2676   GPR[RT] = ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE));
2677 }
2678
2679
2680 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
2681 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
2682 *mipsI,mipsII,mipsIII,mipsIV:
2683 *vr5000:
2684 // start-sanitize-vr5400
2685 *vr5400:
2686 // end-sanitize-vr5400
2687 // start-sanitize-r5900
2688 *r5900:
2689 // end-sanitize-r5900
2690 *r3900:
2691 // start-sanitize-tx19
2692 *tx19:
2693 // end-sanitize-tx19
2694 {
2695   GPR[RT] = ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE));
2696 }
2697
2698 000000,5.RS,5.RT,5.RD,00000101011:SPECIAL:32::SLTU
2699 "sltu r<RD>, r<RS>, r<RT>"
2700 *mipsI,mipsII,mipsIII,mipsIV:
2701 *vr5000:
2702 // start-sanitize-vr5400
2703 *vr5400:
2704 // end-sanitize-vr5400
2705 // start-sanitize-r5900
2706 *r5900:
2707 // end-sanitize-r5900
2708 *r3900:
2709 // start-sanitize-tx19
2710 *tx19:
2711 // end-sanitize-tx19
2712 {
2713   GPR[RD] = ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT]);
2714 }
2715
2716
2717 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
2718 "sra r<RD>, r<RT>, <SHIFT>"
2719 *mipsI,mipsII,mipsIII,mipsIV:
2720 *vr5000:
2721 // start-sanitize-vr5400
2722 *vr5400:
2723 // end-sanitize-vr5400
2724 // start-sanitize-r5900
2725 *r5900:
2726 // end-sanitize-r5900
2727 *r3900:
2728 // start-sanitize-tx19
2729 *tx19:
2730 // end-sanitize-tx19
2731 {
2732   int s = SHIFT;
2733   signed32 temp = (signed32) GPR[RT] >> s;
2734   GPR[RD] = EXTEND32 (temp);
2735 }
2736
2737
2738 000000,5.RS,5.RT,5.RD,00000000111:SPECIAL:32::SRAV
2739 "srav r<RD>, r<RT>, r<RS>"
2740 *mipsI,mipsII,mipsIII,mipsIV:
2741 *vr5000:
2742 // start-sanitize-vr5400
2743 *vr5400:
2744 // end-sanitize-vr5400
2745 // start-sanitize-r5900
2746 *r5900:
2747 // end-sanitize-r5900
2748 *r3900:
2749 // start-sanitize-tx19
2750 *tx19:
2751 // end-sanitize-tx19
2752 {
2753   int s = MASKED (GPR[RS], 4, 0);
2754   signed32 temp = (signed32) GPR[RT] >> s;
2755   GPR[RD] = EXTEND32 (temp);
2756 }
2757
2758
2759 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
2760 "srl r<RD>, r<RT>, <SHIFT>"
2761 *mipsI,mipsII,mipsIII,mipsIV:
2762 *vr5000:
2763 // start-sanitize-vr5400
2764 *vr5400:
2765 // end-sanitize-vr5400
2766 // start-sanitize-r5900
2767 *r5900:
2768 // end-sanitize-r5900
2769 *r3900:
2770 // start-sanitize-tx19
2771 *tx19:
2772 // end-sanitize-tx19
2773 {
2774   int s = SHIFT;
2775   unsigned32 temp = (unsigned32) GPR[RT] >> s;
2776   GPR[RD] = EXTEND32 (temp);
2777 }
2778
2779
2780 000000,5.RS,5.RT,5.RD,00000000110:SPECIAL:32::SRLV
2781 "srlv r<RD>, r<RT>, r<RS>"
2782 *mipsI,mipsII,mipsIII,mipsIV:
2783 *vr5000:
2784 // start-sanitize-vr5400
2785 *vr5400:
2786 // end-sanitize-vr5400
2787 // start-sanitize-r5900
2788 *r5900:
2789 // end-sanitize-r5900
2790 *r3900:
2791 // start-sanitize-tx19
2792 *tx19:
2793 // end-sanitize-tx19
2794 {
2795   int s = MASKED (GPR[RS], 4, 0);
2796   unsigned32 temp = (unsigned32) GPR[RT] >> s;
2797   GPR[RD] = EXTEND32 (temp);
2798 }
2799
2800
2801 000000,5.RS,5.RT,5.RD,00000100010:SPECIAL:32::SUB
2802 "sub r<RD>, r<RS>, r<RT>"
2803 *mipsI,mipsII,mipsIII,mipsIV:
2804 *vr5000:
2805 // start-sanitize-vr5400
2806 *vr5400:
2807 // end-sanitize-vr5400
2808 // start-sanitize-r5900
2809 *r5900:
2810 // end-sanitize-r5900
2811 *r3900:
2812 // start-sanitize-tx19
2813 *tx19:
2814 // end-sanitize-tx19
2815 {
2816   ALU32_BEGIN (GPR[RS]);
2817   ALU32_SUB (GPR[RT]);
2818   ALU32_END (GPR[RD]);
2819 }
2820
2821
2822 000000,5.RS,5.RT,5.RD,00000100011:SPECIAL:32::SUBU
2823 "subu r<RD>, r<RS>, r<RT>"
2824 *mipsI,mipsII,mipsIII,mipsIV:
2825 *vr5000:
2826 // start-sanitize-vr5400
2827 *vr5400:
2828 // end-sanitize-vr5400
2829 // start-sanitize-r5900
2830 *r5900:
2831 // end-sanitize-r5900
2832 *r3900:
2833 // start-sanitize-tx19
2834 *tx19:
2835 // end-sanitize-tx19
2836 {
2837   GPR[RD] = EXTEND32 (GPR[RS] - GPR[RT]);
2838 }
2839
2840
2841 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
2842 "sw r<RT>, <OFFSET>(r<BASE>)"
2843 *mipsI,mipsII,mipsIII,mipsIV:
2844 *vr5000:
2845 // start-sanitize-vr5400
2846 *vr5400:
2847 // end-sanitize-vr5400
2848 // start-sanitize-r5900
2849 *r5900:
2850 // end-sanitize-r5900
2851 *r3900:
2852 // start-sanitize-tx19
2853 *tx19:
2854 // end-sanitize-tx19
2855 {
2856   unsigned32 instruction = instruction_0;
2857   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2858   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2859   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2860   {
2861     address_word vaddr = ((unsigned64)op1 + offset);
2862     address_word paddr;
2863     int uncached;
2864     if ((vaddr & 3) != 0)
2865       SignalExceptionAddressStore();
2866     else
2867       {
2868         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2869           {
2870             unsigned64 memval = 0;
2871             unsigned64 memval1 = 0;
2872             unsigned64 mask = 0x7;
2873             unsigned int byte;
2874             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2875             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2876             memval = ((unsigned64) op2 << (8 * byte));
2877             {
2878               StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2879             }
2880           }
2881       }
2882   }
2883 }
2884
2885
2886 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
2887 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2888 *mipsI,mipsII,mipsIII,mipsIV:
2889 *vr5000:
2890 // start-sanitize-vr5400
2891 *vr5400:
2892 // end-sanitize-vr5400
2893 // start-sanitize-r5900
2894 *r5900:
2895 // end-sanitize-r5900
2896 *r3900:
2897 // start-sanitize-tx19
2898 *tx19:
2899 // end-sanitize-tx19
2900 {
2901   unsigned32 instruction = instruction_0;
2902   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2903   int destreg = ((instruction >> 16) & 0x0000001F);
2904   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2905   {
2906     address_word vaddr = ((unsigned64)op1 + offset);
2907     address_word paddr;
2908     int uncached;
2909     if ((vaddr & 3) != 0)
2910       SignalExceptionAddressStore();
2911     else
2912       {
2913         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2914           {
2915             unsigned64 memval = 0;
2916             unsigned64 memval1 = 0;
2917             unsigned64 mask = 0x7;
2918             unsigned int byte;
2919             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2920             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2921             memval = (((unsigned64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
2922             {
2923               StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2924             }
2925           }
2926       }
2927   }
2928 }
2929
2930
2931 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
2932 "swl r<RT>, <OFFSET>(r<BASE>)"
2933 *mipsI,mipsII,mipsIII,mipsIV:
2934 *vr5000:
2935 // start-sanitize-vr5400
2936 *vr5400:
2937 // end-sanitize-vr5400
2938 // start-sanitize-r5900
2939 *r5900:
2940 // end-sanitize-r5900
2941 *r3900:
2942 // start-sanitize-tx19
2943 *tx19:
2944 // end-sanitize-tx19
2945 {
2946   unsigned32 instruction = instruction_0;
2947   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2948   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2949   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2950   {
2951     address_word vaddr = ((unsigned64)op1 + offset);
2952     address_word paddr;
2953     int uncached;
2954     {
2955       if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2956         {
2957           unsigned64 memval = 0;
2958           unsigned64 memval1 = 0;
2959           unsigned64 mask = 3;
2960           unsigned int reverse = (ReverseEndian ? mask : 0);
2961           unsigned int bigend = (BigEndianCPU ? mask : 0);
2962           int byte;
2963           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
2964           byte = ((vaddr & mask) ^ bigend);
2965           if (!BigEndianMem)
2966             paddr &= ~mask;
2967           memval = (op2 >> (8 * (3 - byte)));
2968           if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
2969             memval <<= 32;
2970           }
2971           StoreMemory(uncached,byte,memval,memval1,paddr,vaddr,isREAL);
2972         }
2973     }
2974   }
2975 }
2976
2977
2978 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
2979 "swr r<RT>, <OFFSET>(r<BASE>)"
2980 *mipsI,mipsII,mipsIII,mipsIV:
2981 *vr5000:
2982 // start-sanitize-vr5400
2983 *vr5400:
2984 // end-sanitize-vr5400
2985 // start-sanitize-r5900
2986 *r5900:
2987 // end-sanitize-r5900
2988 *r3900:
2989 // start-sanitize-tx19
2990 *tx19:
2991 // end-sanitize-tx19
2992 {
2993   unsigned64 memval = 0;
2994   unsigned64 mask = 3;
2995   unsigned int reverse = (ReverseEndian ? mask : 0);
2996   unsigned int bigend = (BigEndianCPU ? mask : 0);
2997   int byte;
2998   address_word paddr;
2999   int uncached;
3000   address_word vaddr = (GPR[BASE] + EXTEND16 (OFFSET));
3001   AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL);
3002   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
3003   if (BigEndianMem)
3004     paddr &= ~mask;
3005   byte = ((vaddr & mask) ^ bigend);
3006   memval = (GPR[RT] << (byte * 8));
3007   if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2))
3008     memval <<= 32;
3009   StoreMemory(uncached,(AccessLength_WORD - byte),memval,0,paddr,vaddr,isREAL);
3010 }
3011
3012
3013 000000000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
3014 "sync":STYPE == 0
3015 "sync <STYPE>"
3016 *mipsII:
3017 *mipsIII:
3018 *mipsIV:
3019 *vr5000:
3020 // start-sanitize-vr5400
3021 *vr5400:
3022 // end-sanitize-vr5400
3023 // start-sanitize-r5900
3024 *r5900:
3025 // end-sanitize-r5900
3026 *r3900:
3027 // start-sanitize-tx19
3028 *tx19:
3029 // end-sanitize-tx19
3030 {
3031   SyncOperation (STYPE);
3032 }
3033
3034
3035 000000,20.CODE,001100:SPECIAL:32::SYSCALL
3036 "syscall <CODE>"
3037 *mipsI,mipsII,mipsIII,mipsIV:
3038 *vr5000:
3039 // start-sanitize-vr5400
3040 *vr5400:
3041 // end-sanitize-vr5400
3042 // start-sanitize-r5900
3043 *r5900:
3044 // end-sanitize-r5900
3045 *r3900:
3046 // start-sanitize-tx19
3047 *tx19:
3048 // end-sanitize-tx19
3049 {
3050   SignalException(SystemCall, instruction_0);
3051 }
3052
3053
3054 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
3055 "teq r<RS>, r<RT>"
3056 *mipsII:
3057 *mipsIII:
3058 *mipsIV:
3059 *vr5000:
3060 // start-sanitize-vr5400
3061 *vr5400:
3062 // end-sanitize-vr5400
3063 // start-sanitize-r5900
3064 *r5900:
3065 // end-sanitize-r5900
3066 *r3900:
3067 // start-sanitize-tx19
3068 *tx19:
3069 // end-sanitize-tx19
3070 {
3071   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
3072     SignalException(Trap, instruction_0);
3073 }
3074
3075
3076 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
3077 "teqi r<RS>, <IMMEDIATE>"
3078 *mipsII:
3079 *mipsIII:
3080 *mipsIV:
3081 *vr5000:
3082 // start-sanitize-vr5400
3083 *vr5400:
3084 // end-sanitize-vr5400
3085 // start-sanitize-r5900
3086 *r5900:
3087 // end-sanitize-r5900
3088 *r3900:
3089 // start-sanitize-tx19
3090 *tx19:
3091 // end-sanitize-tx19
3092 {
3093   if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
3094     SignalException(Trap, instruction_0);
3095 }
3096
3097
3098 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
3099 "tge r<RS>, r<RT>"
3100 *mipsII:
3101 *mipsIII:
3102 *mipsIV:
3103 *vr5000:
3104 // start-sanitize-vr5400
3105 *vr5400:
3106 // end-sanitize-vr5400
3107 // start-sanitize-r5900
3108 *r5900:
3109 // end-sanitize-r5900
3110 *r3900:
3111 // start-sanitize-tx19
3112 *tx19:
3113 // end-sanitize-tx19
3114 {
3115   if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
3116     SignalException(Trap, instruction_0);
3117 }
3118
3119
3120 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
3121 "tgei r<RS>, <IMMEDIATE>"
3122 *mipsII:
3123 *mipsIII:
3124 *mipsIV:
3125 *vr5000:
3126 // start-sanitize-vr5400
3127 *vr5400:
3128 // end-sanitize-vr5400
3129 // start-sanitize-r5900
3130 *r5900:
3131 // end-sanitize-r5900
3132 *r3900:
3133 // start-sanitize-tx19
3134 *tx19:
3135 // end-sanitize-tx19
3136 {
3137   if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
3138     SignalException(Trap, instruction_0);
3139 }
3140
3141
3142 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
3143 "tgeiu r<RS>, <IMMEDIATE>"
3144 *mipsII:
3145 *mipsIII:
3146 *mipsIV:
3147 *vr5000:
3148 // start-sanitize-vr5400
3149 *vr5400:
3150 // end-sanitize-vr5400
3151 // start-sanitize-r5900
3152 *r5900:
3153 // end-sanitize-r5900
3154 *r3900:
3155 // start-sanitize-tx19
3156 *tx19:
3157 // end-sanitize-tx19
3158 {
3159   if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
3160     SignalException(Trap, instruction_0);
3161 }
3162
3163
3164 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
3165 "tgeu r<RS>, r<RT>"
3166 *mipsII:
3167 *mipsIII:
3168 *mipsIV:
3169 *vr5000:
3170 // start-sanitize-vr5400
3171 *vr5400:
3172 // end-sanitize-vr5400
3173 // start-sanitize-r5900
3174 *r5900:
3175 // end-sanitize-r5900
3176 *r3900:
3177 // start-sanitize-tx19
3178 *tx19:
3179 // end-sanitize-tx19
3180 {
3181   if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
3182     SignalException(Trap, instruction_0);
3183 }
3184
3185
3186 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
3187 "tlt r<RS>, r<RT>"
3188 *mipsII:
3189 *mipsIII:
3190 *mipsIV:
3191 *vr5000:
3192 // start-sanitize-vr5400
3193 *vr5400:
3194 // end-sanitize-vr5400
3195 // start-sanitize-r5900
3196 *r5900:
3197 // end-sanitize-r5900
3198 *r3900:
3199 // start-sanitize-tx19
3200 *tx19:
3201 // end-sanitize-tx19
3202 {
3203   if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
3204     SignalException(Trap, instruction_0);
3205 }
3206
3207
3208 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
3209 "tlti r<RS>, <IMMEDIATE>"
3210 *mipsII:
3211 *mipsIII:
3212 *mipsIV:
3213 *vr5000:
3214 // start-sanitize-vr5400
3215 *vr5400:
3216 // end-sanitize-vr5400
3217 // start-sanitize-r5900
3218 *r5900:
3219 // end-sanitize-r5900
3220 *r3900:
3221 // start-sanitize-tx19
3222 *tx19:
3223 // end-sanitize-tx19
3224 {
3225   if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
3226     SignalException(Trap, instruction_0);
3227 }
3228
3229
3230 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
3231 "tltiu r<RS>, <IMMEDIATE>"
3232 *mipsII:
3233 *mipsIII:
3234 *mipsIV:
3235 *vr5000:
3236 // start-sanitize-vr5400
3237 *vr5400:
3238 // end-sanitize-vr5400
3239 // start-sanitize-r5900
3240 *r5900:
3241 // end-sanitize-r5900
3242 *r3900:
3243 // start-sanitize-tx19
3244 *tx19:
3245 // end-sanitize-tx19
3246 {
3247   if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
3248     SignalException(Trap, instruction_0);
3249 }
3250
3251
3252 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
3253 "tltu r<RS>, r<RT>"
3254 *mipsII:
3255 *mipsIII:
3256 *mipsIV:
3257 *vr5000:
3258 // start-sanitize-vr5400
3259 *vr5400:
3260 // end-sanitize-vr5400
3261 // start-sanitize-r5900
3262 *r5900:
3263 // end-sanitize-r5900
3264 *r3900:
3265 // start-sanitize-tx19
3266 *tx19:
3267 // end-sanitize-tx19
3268 {
3269   if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
3270     SignalException(Trap, instruction_0);
3271 }
3272
3273
3274 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
3275 "tne r<RS>, r<RT>"
3276 *mipsII:
3277 *mipsIII:
3278 *mipsIV:
3279 *vr5000:
3280 // start-sanitize-vr5400
3281 *vr5400:
3282 // end-sanitize-vr5400
3283 // start-sanitize-r5900
3284 *r5900:
3285 // end-sanitize-r5900
3286 *r3900:
3287 // start-sanitize-tx19
3288 *tx19:
3289 // end-sanitize-tx19
3290 {
3291   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
3292     SignalException(Trap, instruction_0);
3293 }
3294
3295
3296 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
3297 "tne r<RS>, <IMMEDIATE>"
3298 *mipsII:
3299 *mipsIII:
3300 *mipsIV:
3301 *vr5000:
3302 // start-sanitize-vr5400
3303 *vr5400:
3304 // end-sanitize-vr5400
3305 // start-sanitize-r5900
3306 *r5900:
3307 // end-sanitize-r5900
3308 *r3900:
3309 // start-sanitize-tx19
3310 *tx19:
3311 // end-sanitize-tx19
3312 {
3313   if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
3314     SignalException(Trap, instruction_0);
3315 }
3316
3317
3318 000000,5.RS,5.RT,5.RD,00000100110:SPECIAL:32::XOR
3319 "xor r<RD>, r<RS>, r<RT>"
3320 *mipsI,mipsII,mipsIII,mipsIV:
3321 *vr5000:
3322 // start-sanitize-vr5400
3323 *vr5400:
3324 // end-sanitize-vr5400
3325 // start-sanitize-r5900
3326 *r5900:
3327 // end-sanitize-r5900
3328 *r3900:
3329 // start-sanitize-tx19
3330 *tx19:
3331 // end-sanitize-tx19
3332 {
3333   GPR[RD] = GPR[RS] ^ GPR[RT];
3334 }
3335
3336
3337 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
3338 "xori r<RT>, r<RS>, <IMMEDIATE>"
3339 *mipsI,mipsII,mipsIII,mipsIV:
3340 *vr5000:
3341 // start-sanitize-vr5400
3342 *vr5400:
3343 // end-sanitize-vr5400
3344 // start-sanitize-r5900
3345 *r5900:
3346 // end-sanitize-r5900
3347 *r3900:
3348 // start-sanitize-tx19
3349 *tx19:
3350 // end-sanitize-tx19
3351 {
3352   GPR[RT] = GPR[RS] ^ IMMEDIATE;
3353 }
3354
3355 \f
3356 //
3357 // MIPS Architecture:
3358 //
3359 //        FPU Instruction Set (COP1 & COP1X)
3360 //
3361
3362
3363 :%s::::FMT:int fmt
3364 {
3365   switch (fmt)
3366     {
3367     case fmt_single: return "s";
3368     case fmt_double: return "d";
3369     case fmt_word: return "w";
3370     case fmt_long: return "l";
3371     default: return "?";
3372     }
3373 }
3374
3375 :%s::::X:int x
3376 {
3377   switch (x)
3378     {
3379     case 0: return "f";
3380     case 1: return "t";
3381     default: return "?";
3382     }
3383 }
3384
3385 :%s::::TF:int tf
3386 {
3387   if (tf)
3388     return "t";
3389   else
3390     return "f";
3391 }
3392
3393 :%s::::ND:int nd
3394 {
3395   if (nd)
3396     return "l";
3397   else
3398     return "";
3399 }
3400
3401 :%s::::COND:int cond
3402 {
3403   switch (cond)
3404     {
3405     case 00: return "f";
3406     case 01: return "un";
3407     case 02: return "eq";
3408     case 03: return "ueq";
3409     case 04: return "olt";
3410     case 05: return "ult";
3411     case 06: return "ole";
3412     case 07: return "ule";
3413     case 010: return "sf";
3414     case 011: return "ngle";
3415     case 012: return "seq";
3416     case 013: return "ngl";
3417     case 014: return "lt";
3418     case 015: return "nge";
3419     case 016: return "le";
3420     case 017: return "ngt";
3421     default: return "?";
3422     }
3423 }
3424
3425
3426 010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
3427 "abs.%s<FMT> f<FD>, f<FS>"
3428 *mipsI,mipsII,mipsIII,mipsIV:
3429 *vr5000:
3430 // start-sanitize-vr5400
3431 *vr5400:
3432 // end-sanitize-vr5400
3433 // start-sanitize-r5900
3434 *r5900:
3435 // end-sanitize-r5900
3436 *r3900:
3437 // start-sanitize-tx19
3438 *tx19:
3439 // end-sanitize-tx19
3440 {
3441   unsigned32 instruction = instruction_0;
3442   int destreg = ((instruction >> 6) & 0x0000001F);
3443   int fs = ((instruction >> 11) & 0x0000001F);
3444   int format = ((instruction >> 21) & 0x00000007);
3445   {
3446     if ((format != fmt_single) && (format != fmt_double))
3447       SignalException(ReservedInstruction,instruction);
3448     else
3449       StoreFPR(destreg,format,AbsoluteValue(ValueFPR(fs,format),format));
3450   }
3451 }
3452
3453
3454
3455 010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD
3456 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
3457 *mipsI,mipsII,mipsIII,mipsIV:
3458 *vr5000:
3459 // start-sanitize-vr5400
3460 *vr5400:
3461 // end-sanitize-vr5400
3462 // start-sanitize-r5900
3463 *r5900:
3464 // end-sanitize-r5900
3465 *r3900:
3466 // start-sanitize-tx19
3467 *tx19:
3468 // end-sanitize-tx19
3469 {
3470   unsigned32 instruction = instruction_0;
3471   int destreg = ((instruction >> 6) & 0x0000001F);
3472   int fs = ((instruction >> 11) & 0x0000001F);
3473   int ft = ((instruction >> 16) & 0x0000001F);
3474   int format = ((instruction >> 21) & 0x00000007);
3475   {
3476     if ((format != fmt_single) && (format != fmt_double))
3477       SignalException(ReservedInstruction, instruction);
3478     else
3479       StoreFPR(destreg,format,Add(ValueFPR(fs,format),ValueFPR(ft,format),format));
3480   }
3481 }
3482
3483
3484
3485 // BC1F
3486 // BC1FL
3487 // BC1T
3488 // BC1TL
3489
3490 010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
3491 "bc1%s<TF>%s<ND> <OFFSET>"
3492 *mipsI,mipsII,mipsIII:
3493 // start-sanitize-r5900
3494 *r5900:
3495 // end-sanitize-r5900
3496 {
3497   if (PREVCOC1() == TF)
3498     {
3499       DELAY_SLOT (NIA + (EXTEND16 (OFFSET) << 2));
3500     }
3501   else if (ND)
3502     {
3503       NULLIFY_NEXT_INSTRUCTION ();
3504     }
3505 }
3506
3507 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
3508 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
3509 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
3510 *mipsIV:
3511 *vr5000:
3512 // start-sanitize-vr5400
3513 *vr5400:
3514 // end-sanitize-vr5400
3515 *r3900:
3516 // start-sanitize-tx19
3517 *tx19:
3518 // end-sanitize-tx19
3519 {
3520   if (GETFCC(CC) == TF)
3521     {
3522       DELAY_SLOT (NIA + (EXTEND16 (OFFSET) << 2));
3523     }
3524   else if (ND)
3525     {
3526       NULLIFY_NEXT_INSTRUCTION ();
3527     }
3528 }
3529
3530
3531
3532 // C.EQ.S
3533 // C.EQ.D
3534 // ...
3535
3536 :function:::void:do_c_cond_fmt:int fmt, int ft, int fs, int cc, int cond, instruction_word insn
3537 {
3538   if ((fmt != fmt_single) && (fmt != fmt_double))
3539     SignalException (ReservedInstruction, insn);
3540   else
3541     {
3542       int less;
3543       int equal;
3544       int unordered;
3545       int condition;
3546       unsigned64 ofs = ValueFPR (fs, fmt);
3547       unsigned64 oft = ValueFPR (ft, fmt);
3548       if (NaN (ofs, fmt) || NaN (oft, fmt))
3549         {
3550           if (FCSR & FP_ENABLE (IO))
3551             {
3552               FCSR |= FP_CAUSE (IO);
3553               SignalExceptionFPE ();
3554             }
3555           less = 0;
3556           equal = 0;
3557           unordered = 1;
3558         }
3559       else
3560         {
3561           less = Less (ofs, oft, fmt);
3562           equal = Equal (ofs, oft, fmt);
3563           unordered = 0;
3564         }
3565       condition = (((cond & (1 << 2)) && less)
3566                    || ((cond & (1 << 1)) && equal)
3567                    || ((cond & (1 << 0)) && unordered));
3568       SETFCC (cc, condition);
3569     }
3570 }
3571
3572 010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32::C.cond.fmt
3573 *mipsI,mipsII,mipsIII:
3574 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":
3575 {
3576   do_c_cond_fmt (SD_, FMT, FT, FS, 0, COND, instruction_0);
3577 }
3578
3579 010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32::C.cond.fmt
3580 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
3581 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
3582 *mipsIV:
3583 *vr5000:
3584 // start-sanitize-vr5400
3585 *vr5400:
3586 // end-sanitize-vr5400
3587 // start-sanitize-r5900
3588 *r5900:
3589 // end-sanitize-r5900
3590 *r3900:
3591 // start-sanitize-tx19
3592 *tx19:
3593 // end-sanitize-tx19
3594 {
3595   do_c_cond_fmt (SD_, FMT, FT, FS, CC, COND, instruction_0);
3596 }
3597
3598
3599 010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64::CEIL.L.fmt
3600 "ceil.l.%s<FMT> f<FD>, f<FS>"
3601 *mipsIII:
3602 *mipsIV:
3603 *vr5000:
3604 // start-sanitize-vr5400
3605 *vr5400:
3606 // end-sanitize-vr5400
3607 // start-sanitize-r5900
3608 *r5900:
3609 // end-sanitize-r5900
3610 *r3900:
3611 // start-sanitize-tx19
3612 *tx19:
3613 // end-sanitize-tx19
3614 {
3615   unsigned32 instruction = instruction_0;
3616   int destreg = ((instruction >> 6) & 0x0000001F);
3617   int fs = ((instruction >> 11) & 0x0000001F);
3618   int format = ((instruction >> 21) & 0x00000007);
3619   {
3620     if ((format != fmt_single) && (format != fmt_double))
3621       SignalException(ReservedInstruction,instruction);
3622     else
3623       StoreFPR(destreg,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_long));
3624   }
3625 }
3626
3627
3628 010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32::CEIL.W
3629 *mipsII:
3630 *mipsIII:
3631 *mipsIV:
3632 *vr5000:
3633 // start-sanitize-vr5400
3634 *vr5400:
3635 // end-sanitize-vr5400
3636 // start-sanitize-r5900
3637 *r5900:
3638 // end-sanitize-r5900
3639 *r3900:
3640 // start-sanitize-tx19
3641 *tx19:
3642 // end-sanitize-tx19
3643 {
3644   unsigned32 instruction = instruction_0;
3645   int destreg = ((instruction >> 6) & 0x0000001F);
3646   int fs = ((instruction >> 11) & 0x0000001F);
3647   int format = ((instruction >> 21) & 0x00000007);
3648   {
3649   if ((format != fmt_single) && (format != fmt_double))
3650    SignalException(ReservedInstruction,instruction);
3651   else
3652    StoreFPR(destreg,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_word));
3653   }
3654 }
3655
3656
3657 // CFC1
3658 // CTC1
3659 010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
3660 "c%s<X>c1 r<RT>, f<FS>"
3661 *mipsI:
3662 *mipsII:
3663 *mipsIII:
3664 {
3665   if (X)
3666     {
3667       if (FS == 0)
3668         PENDING_FILL((FS + FCR0IDX),VL4_8(GPR[RT]));
3669       else if (FS == 31)
3670         PENDING_FILL((FS + FCR31IDX),VL4_8(GPR[RT]));
3671       /* else NOP */
3672       PENDING_FILL(COCIDX,0); /* special case */
3673     }
3674   else
3675     { /* control from */
3676       if (FS == 0)
3677         PENDING_FILL(RT,SIGNEXTEND(FCR0,32));
3678       else if (FS == 31)
3679         PENDING_FILL(RT,SIGNEXTEND(FCR31,32));
3680       /* else NOP */
3681     }
3682 }
3683 010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
3684 "c%s<X>c1 r<RT>, f<FS>"
3685 *mipsIV:
3686 *vr5000:
3687 // start-sanitize-vr5400
3688 *vr5400:
3689 // end-sanitize-vr5400
3690 // start-sanitize-r5900
3691 *r5900:
3692 // end-sanitize-r5900
3693 *r3900:
3694 // start-sanitize-tx19
3695 *tx19:
3696 // end-sanitize-tx19
3697 {
3698   if (X)
3699     {
3700       if (FS == 0)
3701         FCR0 = VL4_8(GPR[RT]);
3702       else if (FS == 31)
3703         FCR31 = VL4_8(GPR[RT]);
3704       /* else NOP */
3705       SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
3706     }
3707   else
3708     { /* control from */
3709       if (FS == 0)
3710         GPR[RT] = SIGNEXTEND (FCR0, 32);
3711       else if (FS == 31)
3712         GPR[RT] = SIGNEXTEND (FCR31, 32);
3713       /* else NOP */
3714     }
3715 }
3716
3717
3718 //
3719 // FIXME: Does not correctly differentiate between mips*
3720 //
3721 010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32::CVT.D.fmt
3722 "cvt.d.%s<FMT> f<FD>, f<FS>"
3723 *mipsI,mipsII,mipsIII,mipsIV:
3724 *vr5000:
3725 // start-sanitize-vr5400
3726 *vr5400:
3727 // end-sanitize-vr5400
3728 // start-sanitize-r5900
3729 *r5900:
3730 // end-sanitize-r5900
3731 *r3900:
3732 // start-sanitize-tx19
3733 *tx19:
3734 // end-sanitize-tx19
3735 {
3736   unsigned32 instruction = instruction_0;
3737   int destreg = ((instruction >> 6) & 0x0000001F);
3738   int fs = ((instruction >> 11) & 0x0000001F);
3739   int format = ((instruction >> 21) & 0x00000007);
3740   {
3741     if ((format == fmt_double) | 0)
3742       SignalException(ReservedInstruction,instruction);
3743     else
3744       StoreFPR(destreg,fmt_double,Convert(GETRM(),ValueFPR(fs,format),format,fmt_double));
3745   }
3746 }
3747
3748
3749 010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64::CVT.L.fmt
3750 "cvt.l.%s<FMT> f<FD>, f<FS>"
3751 *mipsIII:
3752 *mipsIV:
3753 *vr5000:
3754 // start-sanitize-vr5400
3755 *vr5400:
3756 // end-sanitize-vr5400
3757 // start-sanitize-r5900
3758 *r5900:
3759 // end-sanitize-r5900
3760 *r3900:
3761 // start-sanitize-tx19
3762 *tx19:
3763 // end-sanitize-tx19
3764 {
3765   unsigned32 instruction = instruction_0;
3766   int destreg = ((instruction >> 6) & 0x0000001F);
3767   int fs = ((instruction >> 11) & 0x0000001F);
3768   int format = ((instruction >> 21) & 0x00000007);
3769   {
3770     if ((format == fmt_long) | ((format == fmt_long) || (format == fmt_word)))
3771       SignalException(ReservedInstruction,instruction);
3772     else
3773       StoreFPR(destreg,fmt_long,Convert(GETRM(),ValueFPR(fs,format),format,fmt_long));
3774   }
3775 }
3776
3777
3778 //
3779 // FIXME: Does not correctly differentiate between mips*
3780 //
3781 010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32::CVT.S.fmt
3782 "cvt.s.%s<FMT> f<FD>, f<FS>"
3783 *mipsI,mipsII,mipsIII,mipsIV:
3784 *vr5000:
3785 // start-sanitize-vr5400
3786 *vr5400:
3787 // end-sanitize-vr5400
3788 // start-sanitize-r5900
3789 *r5900:
3790 // end-sanitize-r5900
3791 *r3900:
3792 // start-sanitize-tx19
3793 *tx19:
3794 // end-sanitize-tx19
3795 {
3796   unsigned32 instruction = instruction_0;
3797   int destreg = ((instruction >> 6) & 0x0000001F);
3798   int fs = ((instruction >> 11) & 0x0000001F);
3799   int format = ((instruction >> 21) & 0x00000007);
3800   {
3801     if ((format == fmt_single) | 0)
3802       SignalException(ReservedInstruction,instruction);
3803     else
3804       StoreFPR(destreg,fmt_single,Convert(GETRM(),ValueFPR(fs,format),format,fmt_single));
3805   }
3806 }
3807
3808
3809 010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32::CVT.W.fmt
3810 "cvt.w.%s<FMT> f<FD>, f<FS>"
3811 *mipsI,mipsII,mipsIII,mipsIV:
3812 *vr5000:
3813 // start-sanitize-vr5400
3814 *vr5400:
3815 // end-sanitize-vr5400
3816 // start-sanitize-r5900
3817 *r5900:
3818 // end-sanitize-r5900
3819 *r3900:
3820 // start-sanitize-tx19
3821 *tx19:
3822 // end-sanitize-tx19
3823 {
3824   unsigned32 instruction = instruction_0;
3825   int destreg = ((instruction >> 6) & 0x0000001F);
3826   int fs = ((instruction >> 11) & 0x0000001F);
3827   int format = ((instruction >> 21) & 0x00000007);
3828   {
3829     if ((format == fmt_word) | ((format == fmt_long) || (format == fmt_word)))
3830       SignalException(ReservedInstruction,instruction);
3831     else
3832       StoreFPR(destreg,fmt_word,Convert(GETRM(),ValueFPR(fs,format),format,fmt_word));
3833   }
3834 }
3835
3836
3837 010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32::DIV.fmt
3838 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
3839 *mipsI,mipsII,mipsIII,mipsIV:
3840 *vr5000:
3841 // start-sanitize-vr5400
3842 *vr5400:
3843 // end-sanitize-vr5400
3844 // start-sanitize-r5900
3845 *r5900:
3846 // end-sanitize-r5900
3847 *r3900:
3848 // start-sanitize-tx19
3849 *tx19:
3850 // end-sanitize-tx19
3851 {
3852   unsigned32 instruction = instruction_0;
3853   int destreg = ((instruction >> 6) & 0x0000001F);
3854   int fs = ((instruction >> 11) & 0x0000001F);
3855   int ft = ((instruction >> 16) & 0x0000001F);
3856   int format = ((instruction >> 21) & 0x00000007);
3857   {
3858     if ((format != fmt_single) && (format != fmt_double))
3859       SignalException(ReservedInstruction,instruction);
3860     else
3861       StoreFPR(destreg,format,Divide(ValueFPR(fs,format),ValueFPR(ft,format),format));
3862   }
3863 }
3864
3865
3866 // DMFC1
3867 // DMTC1
3868 010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
3869 "dm%s<X>c1 r<RT>, f<FS>"
3870 *mipsIII:
3871 {
3872   if (X)
3873     {
3874       if (SizeFGR() == 64)
3875         PENDING_FILL((FS + FGRIDX),GPR[RT]);
3876       else if ((FS & 0x1) == 0)
3877         {
3878           PENDING_FILL(((FS + 1) + FGRIDX),VH4_8(GPR[RT]));
3879           PENDING_FILL((FS + FGRIDX),VL4_8(GPR[RT]));
3880         }
3881     }
3882   else
3883     {
3884       if (SizeFGR() == 64)
3885         PENDING_FILL(RT,FGR[FS]);
3886       else if ((FS & 0x1) == 0)
3887         PENDING_FILL(RT,(SET64HI(FGR[FS+1]) | FGR[FS]));
3888       else
3889         PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
3890     }
3891 }
3892 010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
3893 "dm%s<X>c1 r<RT>, f<FS>"
3894 *mipsIV:
3895 *vr5000:
3896 // start-sanitize-vr5400
3897 *vr5400:
3898 // end-sanitize-vr5400
3899 // start-sanitize-r5900
3900 *r5900:
3901 // end-sanitize-r5900
3902 *r3900:
3903 // start-sanitize-tx19
3904 *tx19:
3905 // end-sanitize-tx19
3906 {
3907   if (X)
3908     {
3909       if (SizeFGR() == 64)
3910         StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
3911       else if ((FS & 0x1) == 0)
3912         StoreFPR (FS, fmt_uninterpreted_64, SET64HI (FGR[FS+1]) | FGR[FS]);
3913     }
3914   else
3915     {
3916       if (SizeFGR() == 64)
3917         GPR[RT] = FGR[FS];
3918       else if ((FS & 0x1) == 0)
3919         GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
3920       else
3921         GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
3922     }
3923 }
3924
3925
3926 010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64::FLOOR.L.fmt
3927 "floor.l.%s<FMT> f<FD>, f<FS>"
3928 *mipsIII:
3929 *mipsIV:
3930 *vr5000:
3931 // start-sanitize-vr5400
3932 *vr5400:
3933 // end-sanitize-vr5400
3934 // start-sanitize-r5900
3935 *r5900:
3936 // end-sanitize-r5900
3937 *r3900:
3938 // start-sanitize-tx19
3939 *tx19:
3940 // end-sanitize-tx19
3941 {
3942   unsigned32 instruction = instruction_0;
3943   int destreg = ((instruction >> 6) & 0x0000001F);
3944   int fs = ((instruction >> 11) & 0x0000001F);
3945   int format = ((instruction >> 21) & 0x00000007);
3946   {
3947     if ((format != fmt_single) && (format != fmt_double))
3948       SignalException(ReservedInstruction,instruction);
3949     else
3950       StoreFPR(destreg,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_long));
3951   }
3952 }
3953
3954
3955 010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32::FLOOR.W.fmt
3956 "floor.w.%s<FMT> f<FD>, f<FS>"
3957 *mipsII:
3958 *mipsIII:
3959 *mipsIV:
3960 *vr5000:
3961 // start-sanitize-vr5400
3962 *vr5400:
3963 // end-sanitize-vr5400
3964 // start-sanitize-r5900
3965 *r5900:
3966 // end-sanitize-r5900
3967 *r3900:
3968 // start-sanitize-tx19
3969 *tx19:
3970 // end-sanitize-tx19
3971 {
3972   unsigned32 instruction = instruction_0;
3973   int destreg = ((instruction >> 6) & 0x0000001F);
3974   int fs = ((instruction >> 11) & 0x0000001F);
3975   int format = ((instruction >> 21) & 0x00000007);
3976   {
3977     if ((format != fmt_single) && (format != fmt_double))
3978       SignalException(ReservedInstruction,instruction);
3979     else
3980       StoreFPR(destreg,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_word));
3981   }
3982 }
3983
3984
3985 110101,5.BASE,5.FT,16.OFFSET:COP1:64::LDC1
3986 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
3987 *mipsII:
3988 *mipsIII:
3989 *mipsIV:
3990 *vr5000:
3991 // start-sanitize-vr5400
3992 *vr5400:
3993 // end-sanitize-vr5400
3994 *r3900:
3995 // start-sanitize-tx19
3996 *tx19:
3997 // end-sanitize-tx19
3998 {
3999   address_word vaddr = GPR[BASE] + EXTEND16 (OFFSET);
4000   address_word paddr;
4001   int uncached;
4002   if ((vaddr & 7) != 0)
4003     SignalExceptionAddressLoad();
4004   else
4005     {
4006       unsigned64 memval;
4007       AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL);
4008       LoadMemory(&memval,0,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
4009       COP_LD(((instruction_0 >> 26) & 0x3),FT,memval);;
4010     }
4011 }
4012
4013
4014 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64::LDXC1
4015 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
4016 *mipsIV:
4017 *vr5000:
4018 // start-sanitize-vr5400
4019 *vr5400:
4020 // end-sanitize-vr5400
4021 {
4022   unsigned32 instruction = instruction_0;
4023   int destreg = ((instruction >> 6) & 0x0000001F);
4024   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4025   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4026   {
4027     address_word vaddr = ((unsigned64)op1 + op2);
4028     address_word paddr;
4029     int uncached;
4030     if ((vaddr & 7) != 0)
4031       SignalExceptionAddressLoad();
4032     else
4033       {
4034         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4035           {
4036             unsigned64 memval = 0;
4037             unsigned64 memval1 = 0;
4038             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
4039             COP_LD(1,destreg,memval);;
4040           }
4041       }
4042   }
4043 }
4044
4045
4046
4047 110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1
4048 "lwc1 f<FT>, <OFFSET>(r<BASE>)"
4049 *mipsI,mipsII,mipsIII,mipsIV:
4050 *vr5000:
4051 // start-sanitize-vr5400
4052 *vr5400:
4053 // end-sanitize-vr5400
4054 // start-sanitize-r5900
4055 *r5900:
4056 // end-sanitize-r5900
4057 *r3900:
4058 // start-sanitize-tx19
4059 *tx19:
4060 // end-sanitize-tx19
4061 {
4062   unsigned32 instruction = instruction_0;
4063   signed_word offset = EXTEND16 (OFFSET);
4064   int destreg UNUSED = ((instruction >> 16) & 0x0000001F);
4065   signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
4066   {
4067     address_word vaddr = ((uword64)op1 + offset);
4068     address_word paddr;
4069     int uncached;
4070     if ((vaddr & 3) != 0)
4071       SignalExceptionAddressLoad();
4072     else
4073       {
4074         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4075           {
4076             uword64 memval = 0;
4077             uword64 memval1 = 0;
4078             uword64 mask = 0x7;
4079             unsigned int shift = 2;
4080             unsigned int reverse UNUSED = (ReverseEndian ? (mask >> shift) : 0);
4081             unsigned int bigend UNUSED = (BigEndianCPU ? (mask >> shift) : 0);
4082             unsigned int byte UNUSED;
4083             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
4084             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
4085             byte = ((vaddr & mask) ^ (bigend << shift));
4086             COP_LW(((instruction >> 26) & 0x3),destreg,(unsigned int)((memval >> (8 * byte)) & 0xFFFFFFFF));
4087           }
4088       }
4089   }
4090 }
4091
4092
4093 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32::LWXC1
4094 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
4095 *mipsIV:
4096 *vr5000:
4097 // start-sanitize-vr5400
4098 *vr5400:
4099 // end-sanitize-vr5400
4100 {
4101   unsigned32 instruction = instruction_0;
4102   int destreg = ((instruction >> 6) & 0x0000001F);
4103   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4104   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4105   {
4106    address_word vaddr = ((unsigned64)op1 + op2);
4107    address_word paddr;
4108    int uncached;
4109    if ((vaddr & 3) != 0)
4110     SignalExceptionAddressLoad();
4111    else
4112    {
4113     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4114     {
4115      unsigned64 memval = 0;
4116      unsigned64 memval1 = 0;
4117      unsigned64 mask = 0x7;
4118      unsigned int shift = 2;
4119      unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
4120      unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
4121      unsigned int byte;
4122      paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
4123      LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
4124      byte = ((vaddr & mask) ^ (bigend << shift));
4125      COP_LW(1,destreg,(unsigned int)((memval >> (8 * byte)) & 0xFFFFFFFF));
4126     }
4127    }
4128   }
4129 }
4130
4131
4132
4133 //
4134 // FIXME: Not correct for mips*
4135 //
4136 010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32::MADD.D
4137 "madd.d f<FD>, f<FR>, f<FS>, f<FT>"
4138 *mipsIV:
4139 *vr5000:
4140 // start-sanitize-vr5400
4141 *vr5400:
4142 // end-sanitize-vr5400
4143 // start-sanitize-r5900
4144 *r5900:
4145 // end-sanitize-r5900
4146 {
4147   unsigned32 instruction = instruction_0;
4148   int destreg = ((instruction >> 6) & 0x0000001F);
4149   int fs = ((instruction >> 11) & 0x0000001F);
4150   int ft = ((instruction >> 16) & 0x0000001F);
4151   int fr = ((instruction >> 21) & 0x0000001F);
4152   {
4153     StoreFPR(destreg,fmt_double,Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
4154   }
4155 }
4156
4157
4158 010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32::MADD.S
4159 "madd.s f<FD>, f<FR>, f<FS>, f<FT>"
4160 *mipsIV:
4161 *vr5000:
4162 // start-sanitize-vr5400
4163 *vr5400:
4164 // end-sanitize-vr5400
4165 // start-sanitize-r5900
4166 *r5900:
4167 // end-sanitize-r5900
4168 {
4169   unsigned32 instruction = instruction_0;
4170   int destreg = ((instruction >> 6) & 0x0000001F);
4171   int fs = ((instruction >> 11) & 0x0000001F);
4172   int ft = ((instruction >> 16) & 0x0000001F);
4173   int fr = ((instruction >> 21) & 0x0000001F);
4174   {
4175     StoreFPR(destreg,fmt_single,Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
4176   }
4177 }
4178
4179
4180 // MFC1
4181 // MTC1
4182 010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
4183 "m%s<X>c1 r<RT>, f<FS>"
4184 *mipsI:
4185 *mipsII:
4186 *mipsIII:
4187 {
4188   if (X)
4189     { /*MTC1*/
4190       if (SizeFGR() == 64)
4191         PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT])));
4192       else
4193         PENDING_FILL ((FS + FGRIDX), VL4_8(GPR[RT]));
4194     }
4195   else /*MFC1*/
4196     PENDING_FILL (RT, SIGNEXTEND(FGR[FS],32));
4197 }
4198 010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
4199 "m%s<X>c1 r<RT>, f<FS>"
4200 *mipsIV:
4201 *vr5000:
4202 // start-sanitize-vr5400
4203 *vr5400:
4204 // end-sanitize-vr5400
4205 // start-sanitize-r5900
4206 *r5900:
4207 // end-sanitize-r5900
4208 *r3900:
4209 // start-sanitize-tx19
4210 *tx19:
4211 // end-sanitize-tx19
4212 {
4213   if (X)
4214     /*MTC1*/
4215     StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
4216   else /*MFC1*/
4217     GPR[RT] = SIGNEXTEND(FGR[FS],32);
4218 }
4219
4220
4221 010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32::MOV.fmt
4222 "mov.%s<FMT> f<FD>, f<FS>"
4223 *mipsI,mipsII,mipsIII,mipsIV:
4224 *vr5000:
4225 // start-sanitize-vr5400
4226 *vr5400:
4227 // end-sanitize-vr5400
4228 // start-sanitize-r5900
4229 *r5900:
4230 // end-sanitize-r5900
4231 *r3900:
4232 // start-sanitize-tx19
4233 *tx19:
4234 // end-sanitize-tx19
4235 {
4236   unsigned32 instruction = instruction_0;
4237   int destreg = ((instruction >> 6) & 0x0000001F);
4238   int fs = ((instruction >> 11) & 0x0000001F);
4239   int format = ((instruction >> 21) & 0x00000007);
4240   {
4241     StoreFPR(destreg,format,ValueFPR(fs,format));
4242   }
4243 }
4244
4245
4246 // MOVF
4247 000000,5.RS,3.CC,0,1.TF,5.RD,00000000001:SPECIAL:32::MOVtf
4248 "mov%s<TF> r<RD>, r<RS>, <CC>"
4249 *mipsIV:
4250 *vr5000:
4251 // start-sanitize-vr5400
4252 *vr5400:
4253 // end-sanitize-vr5400
4254 // start-sanitize-r5900
4255 *r5900:
4256 // end-sanitize-r5900
4257 {
4258   if (GETFCC(CC) == TF)
4259     GPR[RD] = GPR[RS];
4260 }
4261
4262
4263 // MOVF.fmt
4264 010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32::MOVtf.fmt
4265 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
4266 *mipsIV:
4267 *vr5000:
4268 // start-sanitize-vr5400
4269 *vr5400:
4270 // end-sanitize-vr5400
4271 // start-sanitize-r5900
4272 *r5900:
4273 // end-sanitize-r5900
4274 {
4275   unsigned32 instruction = instruction_0;
4276   int format = ((instruction >> 21) & 0x00000007);
4277   {
4278    if (GETFCC(CC) == TF)
4279      StoreFPR (FD, format, ValueFPR (FS, format));
4280    else
4281      StoreFPR (FD, format, ValueFPR (FD, format));
4282   }
4283 }
4284
4285
4286 010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32::MOVN.fmt
4287 *mipsIV:
4288 *vr5000:
4289 // start-sanitize-vr5400
4290 *vr5400:
4291 // end-sanitize-vr5400
4292 // start-sanitize-r5900
4293 *r5900:
4294 // end-sanitize-r5900
4295 {
4296   unsigned32 instruction = instruction_0;
4297   int destreg = ((instruction >> 6) & 0x0000001F);
4298   int fs = ((instruction >> 11) & 0x0000001F);
4299   int format = ((instruction >> 21) & 0x00000007);
4300   {
4301     StoreFPR(destreg,format,ValueFPR(fs,format));
4302   }
4303 }
4304
4305
4306 // MOVT see MOVtf
4307
4308
4309 // MOVT.fmt see MOVtf.fmt
4310
4311
4312
4313 010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32::MOVZ.fmt
4314 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
4315 *mipsIV:
4316 *vr5000:
4317 // start-sanitize-vr5400
4318 *vr5400:
4319 // end-sanitize-vr5400
4320 // start-sanitize-r5900
4321 *r5900:
4322 // end-sanitize-r5900
4323 {
4324   unsigned32 instruction = instruction_0;
4325   int destreg = ((instruction >> 6) & 0x0000001F);
4326   int fs = ((instruction >> 11) & 0x0000001F);
4327   int format = ((instruction >> 21) & 0x00000007);
4328   {
4329    StoreFPR(destreg,format,ValueFPR(fs,format));
4330   }
4331 }
4332
4333
4334 // MSUB.fmt
4335 010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32::MSUB.D
4336 "msub.d f<FD>, f<FR>, f<FS>, f<FT>"
4337 *mipsIV:
4338 *vr5000:
4339 // start-sanitize-vr5400
4340 *vr5400:
4341 // end-sanitize-vr5400
4342 // start-sanitize-r5900
4343 *r5900:
4344 // end-sanitize-r5900
4345 {
4346   unsigned32 instruction = instruction_0;
4347   int destreg = ((instruction >> 6) & 0x0000001F);
4348   int fs = ((instruction >> 11) & 0x0000001F);
4349   int ft = ((instruction >> 16) & 0x0000001F);
4350   int fr = ((instruction >> 21) & 0x0000001F);
4351   {
4352     StoreFPR(destreg,fmt_double,Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
4353   }
4354 }
4355
4356
4357 // MSUB.fmt
4358 010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32::MSUB.S
4359 "msub.s f<FD>, f<FR>, f<FS>, f<FT>"
4360 *mipsIV:
4361 *vr5000:
4362 // start-sanitize-vr5400
4363 *vr5400:
4364 // end-sanitize-vr5400
4365 // start-sanitize-r5900
4366 *r5900:
4367 // end-sanitize-r5900
4368 {
4369   unsigned32 instruction = instruction_0;
4370   int destreg = ((instruction >> 6) & 0x0000001F);
4371   int fs = ((instruction >> 11) & 0x0000001F);
4372   int ft = ((instruction >> 16) & 0x0000001F);
4373   int fr = ((instruction >> 21) & 0x0000001F);
4374   {
4375    StoreFPR(destreg,fmt_single,Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
4376   }
4377 }
4378
4379
4380 // MTC1 see MxC1
4381
4382
4383 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32::MUL.fmt
4384 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
4385 *mipsI,mipsII,mipsIII,mipsIV:
4386 *vr5000:
4387 // start-sanitize-vr5400
4388 *vr5400:
4389 // end-sanitize-vr5400
4390 // start-sanitize-r5900
4391 *r5900:
4392 // end-sanitize-r5900
4393 *r3900:
4394 // start-sanitize-tx19
4395 *tx19:
4396 // end-sanitize-tx19
4397 {
4398   unsigned32 instruction = instruction_0;
4399   int destreg = ((instruction >> 6) & 0x0000001F);
4400   int fs = ((instruction >> 11) & 0x0000001F);
4401   int ft = ((instruction >> 16) & 0x0000001F);
4402   int format = ((instruction >> 21) & 0x00000007);
4403   {
4404     if ((format != fmt_single) && (format != fmt_double))
4405       SignalException(ReservedInstruction,instruction);
4406     else
4407       StoreFPR(destreg,format,Multiply(ValueFPR(fs,format),ValueFPR(ft,format),format));
4408   }
4409 }
4410
4411
4412 010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32::NEG.fmt
4413 "neg.%s<FMT> f<FD>, f<FS>"
4414 *mipsI,mipsII,mipsIII,mipsIV:
4415 *vr5000:
4416 // start-sanitize-vr5400
4417 *vr5400:
4418 // end-sanitize-vr5400
4419 // start-sanitize-r5900
4420 *r5900:
4421 // end-sanitize-r5900
4422 *r3900:
4423 // start-sanitize-tx19
4424 *tx19:
4425 // end-sanitize-tx19
4426 {
4427   unsigned32 instruction = instruction_0;
4428   int destreg = ((instruction >> 6) & 0x0000001F);
4429   int fs = ((instruction >> 11) & 0x0000001F);
4430   int format = ((instruction >> 21) & 0x00000007);
4431   {
4432     if ((format != fmt_single) && (format != fmt_double))
4433       SignalException(ReservedInstruction,instruction);
4434     else
4435       StoreFPR(destreg,format,Negate(ValueFPR(fs,format),format));
4436   }
4437 }
4438
4439
4440 // NMADD.fmt
4441 010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32::NMADD.D
4442 "nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
4443 *mipsIV:
4444 *vr5000:
4445 // start-sanitize-vr5400
4446 *vr5400:
4447 // end-sanitize-vr5400
4448 {
4449   unsigned32 instruction = instruction_0;
4450   int destreg = ((instruction >> 6) & 0x0000001F);
4451   int fs = ((instruction >> 11) & 0x0000001F);
4452   int ft = ((instruction >> 16) & 0x0000001F);
4453   int fr = ((instruction >> 21) & 0x0000001F);
4454   {
4455    StoreFPR(destreg,fmt_double,Negate(Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
4456   }
4457 }
4458
4459
4460 // NMADD.fmt
4461 010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32::NMADD.S
4462 "nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
4463 *mipsIV:
4464 *vr5000:
4465 // start-sanitize-vr5400
4466 *vr5400:
4467 // end-sanitize-vr5400
4468 {
4469   unsigned32 instruction = instruction_0;
4470   int destreg = ((instruction >> 6) & 0x0000001F);
4471   int fs = ((instruction >> 11) & 0x0000001F);
4472   int ft = ((instruction >> 16) & 0x0000001F);
4473   int fr = ((instruction >> 21) & 0x0000001F);
4474   {
4475    StoreFPR(destreg,fmt_single,Negate(Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
4476   }
4477 }
4478
4479
4480 // NMSUB.fmt
4481 010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32::NMSUB.D
4482 "nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
4483 *mipsIV:
4484 *vr5000:
4485 // start-sanitize-vr5400
4486 *vr5400:
4487 // end-sanitize-vr5400
4488 {
4489   unsigned32 instruction = instruction_0;
4490   int destreg = ((instruction >> 6) & 0x0000001F);
4491   int fs = ((instruction >> 11) & 0x0000001F);
4492   int ft = ((instruction >> 16) & 0x0000001F);
4493   int fr = ((instruction >> 21) & 0x0000001F);
4494   {
4495    StoreFPR(destreg,fmt_double,Negate(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
4496   }
4497 }
4498
4499
4500 // NMSUB.fmt
4501 010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32::NMSUB.S
4502 "nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
4503 *mipsIV:
4504 *vr5000:
4505 // start-sanitize-vr5400
4506 *vr5400:
4507 // end-sanitize-vr5400
4508 {
4509   unsigned32 instruction = instruction_0;
4510   int destreg = ((instruction >> 6) & 0x0000001F);
4511   int fs = ((instruction >> 11) & 0x0000001F);
4512   int ft = ((instruction >> 16) & 0x0000001F);
4513   int fr = ((instruction >> 21) & 0x0000001F);
4514   {
4515     StoreFPR(destreg,fmt_single,Negate(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
4516   }
4517 }
4518
4519
4520 010011,5.BASE,5.INDEX,5.HINT,00000001111:COP1X:32::PREFX
4521 "prefx <HINT>, r<INDEX>(r<BASE>)"
4522 *mipsIV:
4523 *vr5000:
4524 // start-sanitize-vr5400
4525 *vr5400:
4526 // end-sanitize-vr5400
4527 {
4528   unsigned32 instruction = instruction_0;
4529   int fs = ((instruction >> 11) & 0x0000001F);
4530   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4531   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4532   {
4533     address_word vaddr = ((unsigned64)op1 + (unsigned64)op2);
4534     address_word paddr;
4535     int uncached;
4536     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4537       Prefetch(uncached,paddr,vaddr,isDATA,fs);
4538   }
4539 }
4540
4541 010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32::RECIP.fmt
4542 *mipsIV:
4543 "recip.%s<FMT> f<FD>, f<FS>"
4544 *vr5000:
4545 // start-sanitize-vr5400
4546 *vr5400:
4547 // end-sanitize-vr5400
4548 {
4549   unsigned32 instruction = instruction_0;
4550   int destreg = ((instruction >> 6) & 0x0000001F);
4551   int fs = ((instruction >> 11) & 0x0000001F);
4552   int format = ((instruction >> 21) & 0x00000007);
4553   {
4554   if ((format != fmt_single) && (format != fmt_double))
4555    SignalException(ReservedInstruction,instruction);
4556   else
4557    StoreFPR(destreg,format,Recip(ValueFPR(fs,format),format));
4558   }
4559 }
4560
4561
4562 010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64::ROUND.L.fmt
4563 "round.l.%s<FMT> f<FD>, f<FS>"
4564 *mipsIII:
4565 *mipsIV:
4566 *vr5000:
4567 // start-sanitize-vr5400
4568 *vr5400:
4569 // end-sanitize-vr5400
4570 // start-sanitize-r5900
4571 *r5900:
4572 // end-sanitize-r5900
4573 *r3900:
4574 // start-sanitize-tx19
4575 *tx19:
4576 // end-sanitize-tx19
4577 {
4578   unsigned32 instruction = instruction_0;
4579   int destreg = ((instruction >> 6) & 0x0000001F);
4580   int fs = ((instruction >> 11) & 0x0000001F);
4581   int format = ((instruction >> 21) & 0x00000007);
4582   {
4583     if ((format != fmt_single) && (format != fmt_double))
4584       SignalException(ReservedInstruction,instruction);
4585     else
4586       StoreFPR(destreg,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_long));
4587   }
4588 }
4589
4590
4591 010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32::ROUND.W.fmt
4592 "round.w.%s<FMT> f<FD>, f<FS>"
4593 *mipsII:
4594 *mipsIII:
4595 *mipsIV:
4596 *vr5000:
4597 // start-sanitize-vr5400
4598 *vr5400:
4599 // end-sanitize-vr5400
4600 // start-sanitize-r5900
4601 *r5900:
4602 // end-sanitize-r5900
4603 *r3900:
4604 // start-sanitize-tx19
4605 *tx19:
4606 // end-sanitize-tx19
4607 {
4608   unsigned32 instruction = instruction_0;
4609   int destreg = ((instruction >> 6) & 0x0000001F);
4610   int fs = ((instruction >> 11) & 0x0000001F);
4611   int format = ((instruction >> 21) & 0x00000007);
4612   {
4613   if ((format != fmt_single) && (format != fmt_double))
4614    SignalException(ReservedInstruction,instruction);
4615   else
4616    StoreFPR(destreg,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_word));
4617   }
4618 }
4619
4620
4621 010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32::RSQRT.fmt
4622 *mipsIV:
4623 "rsqrt.%s<FMT> f<FD>, f<FS>"
4624 *vr5000:
4625 // start-sanitize-vr5400
4626 *vr5400:
4627 // end-sanitize-vr5400
4628 {
4629   unsigned32 instruction = instruction_0;
4630   int destreg = ((instruction >> 6) & 0x0000001F);
4631   int fs = ((instruction >> 11) & 0x0000001F);
4632   int format = ((instruction >> 21) & 0x00000007);
4633   {
4634   if ((format != fmt_single) && (format != fmt_double))
4635    SignalException(ReservedInstruction,instruction);
4636   else
4637    StoreFPR(destreg,format,Recip(SquareRoot(ValueFPR(fs,format),format),format));
4638   }
4639 }
4640
4641
4642 111101,5.BASE,5.FT,16.OFFSET:COP1:64::SDC1
4643 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
4644 *mipsII:
4645 *mipsIII:
4646 *mipsIV:
4647 *vr5000:
4648 // start-sanitize-vr5400
4649 *vr5400:
4650 // end-sanitize-vr5400
4651 *r3900:
4652 // start-sanitize-tx19
4653 *tx19:
4654 // end-sanitize-tx19
4655 {
4656   address_word vaddr = GPR[BASE] + EXTEND16 (OFFSET);
4657   int uncached;
4658   if ((vaddr & 7) != 0)
4659     SignalExceptionAddressStore();
4660   else
4661     {
4662       address_word paddr;
4663       unsigned64 memval;
4664       AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL);
4665       memval = (unsigned64) COP_SD(((instruction_0 >> 26) & 0x3),FT);
4666       StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,0,paddr,vaddr,isREAL);
4667     }
4668 }
4669
4670
4671
4672 010011,5.RS,5.RT,vvvvv,00000001001:COP1X:64::SDXC1
4673 *mipsIV:
4674 *vr5000:
4675 // start-sanitize-vr5400
4676 *vr5400:
4677 // end-sanitize-vr5400
4678 {
4679   unsigned32 instruction = instruction_0;
4680   int fs = ((instruction >> 11) & 0x0000001F);
4681   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4682   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4683   {
4684     address_word vaddr = ((unsigned64)op1 + op2);
4685     address_word paddr;
4686     int uncached;
4687     if ((vaddr & 7) != 0)
4688       SignalExceptionAddressStore();
4689     else
4690       {
4691         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4692           {
4693             unsigned64 memval = 0;
4694             unsigned64 memval1 = 0;
4695             memval = (unsigned64)COP_SD(1,fs);
4696             {
4697               StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
4698             }
4699           }
4700       }
4701   }
4702 }
4703
4704
4705 010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32::SQRT.fmt
4706 "sqrt.%s<FMT> f<FD>, f<FS>"
4707 *mipsII:
4708 *mipsIII:
4709 *mipsIV:
4710 *vr5000:
4711 // start-sanitize-vr5400
4712 *vr5400:
4713 // end-sanitize-vr5400
4714 // start-sanitize-r5900
4715 *r5900:
4716 // end-sanitize-r5900
4717 *r3900:
4718 // start-sanitize-tx19
4719 *tx19:
4720 // end-sanitize-tx19
4721 {
4722   unsigned32 instruction = instruction_0;
4723   int destreg = ((instruction >> 6) & 0x0000001F);
4724   int fs = ((instruction >> 11) & 0x0000001F);
4725   int format = ((instruction >> 21) & 0x00000007);
4726   {
4727     if ((format != fmt_single) && (format != fmt_double))
4728       SignalException(ReservedInstruction,instruction);
4729     else
4730       StoreFPR(destreg,format,(SquareRoot(ValueFPR(fs,format),format)));
4731   }
4732 }
4733
4734
4735 010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32::SUB.fmt
4736 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
4737 *mipsI,mipsII,mipsIII,mipsIV:
4738 *vr5000:
4739 // start-sanitize-vr5400
4740 *vr5400:
4741 // end-sanitize-vr5400
4742 // start-sanitize-r5900
4743 *r5900:
4744 // end-sanitize-r5900
4745 *r3900:
4746 // start-sanitize-tx19
4747 *tx19:
4748 // end-sanitize-tx19
4749 {
4750   unsigned32 instruction = instruction_0;
4751   int destreg = ((instruction >> 6) & 0x0000001F);
4752   int fs = ((instruction >> 11) & 0x0000001F);
4753   int ft = ((instruction >> 16) & 0x0000001F);
4754   int format = ((instruction >> 21) & 0x00000007);
4755   {
4756     if ((format != fmt_single) && (format != fmt_double))
4757       SignalException(ReservedInstruction,instruction);
4758     else
4759       StoreFPR(destreg,format,Sub(ValueFPR(fs,format),ValueFPR(ft,format),format));
4760   }
4761 }
4762
4763
4764
4765 111001,5.BASE,5.FT,16.OFFSET:COP1:32::SWC1
4766 "swc1 f<FT>, <OFFSET>(r<BASE>)"
4767 *mipsI,mipsII,mipsIII,mipsIV:
4768 *vr5000:
4769 // start-sanitize-vr5400
4770 *vr5400:
4771 // end-sanitize-vr5400
4772 // start-sanitize-r5900
4773 *r5900:
4774 // end-sanitize-r5900
4775 *r3900:
4776 // start-sanitize-tx19
4777 *tx19:
4778 // end-sanitize-tx19
4779 {
4780   unsigned32 instruction = instruction_0;
4781   signed_word offset = EXTEND16 (OFFSET);
4782   int destreg UNUSED = ((instruction >> 16) & 0x0000001F);
4783   signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
4784   {
4785     address_word vaddr = ((uword64)op1 + offset);
4786     address_word paddr;
4787     int uncached;
4788     if ((vaddr & 3) != 0)
4789       SignalExceptionAddressStore();
4790     else
4791       {
4792         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4793           {
4794             uword64 memval = 0;
4795             uword64 memval1 = 0;
4796             uword64 mask = 0x7;
4797             unsigned int byte;
4798             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
4799             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
4800             memval = (((uword64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
4801             {
4802               StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
4803             }
4804           }
4805       }
4806   }
4807 }
4808
4809
4810 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32::SWXC1
4811 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
4812 *mipsIV:
4813 *vr5000:
4814 // start-sanitize-vr5400
4815 *vr5400:
4816 // end-sanitize-vr5400
4817 {
4818   unsigned32 instruction = instruction_0;
4819   int fs = ((instruction >> 11) & 0x0000001F);
4820   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4821   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4822   {
4823    address_word vaddr = ((unsigned64)op1 + op2);
4824    address_word paddr;
4825    int uncached;
4826    if ((vaddr & 3) != 0)
4827     SignalExceptionAddressStore();
4828    else
4829    {
4830     if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4831     {
4832      unsigned64 memval = 0;
4833      unsigned64 memval1 = 0;
4834      unsigned64 mask = 0x7;
4835      unsigned int byte;
4836      paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
4837      byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
4838      memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte));
4839       {
4840        StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
4841       }
4842     }
4843    }
4844   }
4845 }
4846
4847
4848 010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64::TRUNC.L.fmt
4849 "trunc.l.%s<FMT> f<FD>, f<FS>"
4850 *mipsIII:
4851 *mipsIV:
4852 *vr5000:
4853 // start-sanitize-vr5400
4854 *vr5400:
4855 // end-sanitize-vr5400
4856 // start-sanitize-r5900
4857 *r5900:
4858 // end-sanitize-r5900
4859 *r3900:
4860 // start-sanitize-tx19
4861 *tx19:
4862 // end-sanitize-tx19
4863 {
4864   unsigned32 instruction = instruction_0;
4865   int destreg = ((instruction >> 6) & 0x0000001F);
4866   int fs = ((instruction >> 11) & 0x0000001F);
4867   int format = ((instruction >> 21) & 0x00000007);
4868   {
4869   if ((format != fmt_single) && (format != fmt_double))
4870    SignalException(ReservedInstruction,instruction);
4871   else
4872    StoreFPR(destreg,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_long));
4873   }
4874 }
4875
4876
4877 010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32::TRUNC.W
4878 "trunc.w.%s<FMT> f<FD>, f<FS>"
4879 *mipsII:
4880 *mipsIII:
4881 *mipsIV:
4882 *vr5000:
4883 // start-sanitize-vr5400
4884 *vr5400:
4885 // end-sanitize-vr5400
4886 // start-sanitize-r5900
4887 *r5900:
4888 // end-sanitize-r5900
4889 *r3900:
4890 // start-sanitize-tx19
4891 *tx19:
4892 // end-sanitize-tx19
4893 {
4894   unsigned32 instruction = instruction_0;
4895   int destreg = ((instruction >> 6) & 0x0000001F);
4896   int fs = ((instruction >> 11) & 0x0000001F);
4897   int format = ((instruction >> 21) & 0x00000007);
4898   {
4899   if ((format != fmt_single) && (format != fmt_double))
4900    SignalException(ReservedInstruction,instruction);
4901   else
4902    StoreFPR(destreg,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_word));
4903   }
4904 }
4905
4906 \f
4907 //
4908 // MIPS Architecture:
4909 //
4910 //        System Control Instruction Set (COP0)
4911 //
4912
4913
4914 010000,01000,00000,16.OFFSET:COP0:32::BC0F
4915 "bc0f <OFFSET>"
4916 *mipsI,mipsII,mipsIII,mipsIV:
4917 *vr5000:
4918 // start-sanitize-vr5400
4919 *vr5400:
4920 // end-sanitize-vr5400
4921 // start-sanitize-r5900
4922 *r5900:
4923 // end-sanitize-r5900
4924
4925
4926 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
4927 "bc0fl <OFFSET>"
4928 *mipsI,mipsII,mipsIII,mipsIV:
4929 *vr5000:
4930 // start-sanitize-vr5400
4931 *vr5400:
4932 // end-sanitize-vr5400
4933 // start-sanitize-r5900
4934 *r5900:
4935 // end-sanitize-r5900
4936
4937
4938 010000,01000,00001,16.OFFSET:COP0:32::BC0T
4939 "bc0t <OFFSET>"
4940 *mipsI,mipsII,mipsIII,mipsIV:
4941 // start-sanitize-r5900
4942 *r5900:
4943 // end-sanitize-r5900
4944
4945
4946
4947 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
4948 "bc0tl <OFFSET>"
4949 *mipsI,mipsII,mipsIII,mipsIV:
4950 *vr5000:
4951 // start-sanitize-vr5400
4952 *vr5400:
4953 // end-sanitize-vr5400
4954 // start-sanitize-r5900
4955 *r5900:
4956 // end-sanitize-r5900
4957
4958
4959 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
4960 *mipsIII:
4961 *mipsIV:
4962 *vr5000:
4963 // start-sanitize-vr5400
4964 *vr5400:
4965 // end-sanitize-vr5400
4966 // start-sanitize-r5900
4967 *r5900:
4968 // end-sanitize-r5900
4969 *r3900:
4970 // start-sanitize-tx19
4971 *tx19:
4972 // end-sanitize-tx19
4973 {
4974   unsigned32 instruction = instruction_0;
4975   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
4976   int hint = ((instruction >> 16) & 0x0000001F);
4977   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4978   {
4979     address_word vaddr = (op1 + offset);
4980     address_word paddr;
4981     int uncached;
4982     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4983       CacheOp(hint,vaddr,paddr,instruction);
4984   }
4985 }
4986
4987
4988 010000,10000,000000000000000,111001:COP0:32::DI
4989 "di"
4990 *mipsI,mipsII,mipsIII,mipsIV:
4991 *vr5000:
4992 // start-sanitize-vr5400
4993 *vr5400:
4994 // end-sanitize-vr5400
4995 // start-sanitize-r5900
4996 *r5900:
4997 // end-sanitize-r5900
4998
4999
5000 010000,10000,000000000000000,111000:COP0:32::EI
5001 "ei"
5002 *mipsI,mipsII,mipsIII,mipsIV:
5003 *vr5000:
5004 // start-sanitize-vr5400
5005 *vr5400:
5006 // end-sanitize-vr5400
5007 // start-sanitize-r5900
5008 *r5900:
5009 // end-sanitize-r5900
5010
5011
5012 010000,10000,000000000000000,011000:COP0:32::ERET
5013 "eret"
5014 *mipsIII:
5015 *mipsIV:
5016 *vr5000:
5017 // start-sanitize-vr5400
5018 *vr5400:
5019 // end-sanitize-vr5400
5020 // start-sanitize-r5900
5021 *r5900:
5022 // end-sanitize-r5900
5023
5024
5025 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
5026 "mfc0 r<RT>, r<RD> # <REGX>"
5027 *mipsI,mipsII,mipsIII,mipsIV:
5028 *vr5000:
5029 // start-sanitize-vr5400
5030 *vr5400:
5031 // end-sanitize-vr5400
5032 // start-sanitize-r5900
5033 *r5900:
5034 // end-sanitize-r5900
5035 {
5036   DecodeCoproc (instruction_0);
5037 }
5038
5039 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
5040 "mtc0 r<RT>, r<RD> # <REGX>"
5041 *mipsI,mipsII,mipsIII,mipsIV:
5042 *vr5000:
5043 // start-sanitize-vr5400
5044 *vr5400:
5045 // end-sanitize-vr5400
5046 // start-sanitize-r5900
5047 *r5900:
5048 // end-sanitize-r5900
5049 {
5050   DecodeCoproc (instruction_0);
5051 }
5052
5053
5054 010000,10000,000000000000000,001000:COP0:32::TLBP
5055 "tlbp"
5056 *mipsI,mipsII,mipsIII,mipsIV:
5057 *vr5000:
5058 // start-sanitize-vr5400
5059 *vr5400:
5060 // end-sanitize-vr5400
5061 // start-sanitize-r5900
5062 *r5900:
5063 // end-sanitize-r5900
5064
5065
5066 010000,10000,000000000000000,000001:COP0:32::TLBR
5067 "tlbr"
5068 *mipsI,mipsII,mipsIII,mipsIV:
5069 *vr5000:
5070 // start-sanitize-vr5400
5071 *vr5400:
5072 // end-sanitize-vr5400
5073 // start-sanitize-r5900
5074 *r5900:
5075 // end-sanitize-r5900
5076
5077
5078 010000,10000,000000000000000,000010:COP0:32::TLBWI
5079 "tlbwi"
5080 *mipsI,mipsII,mipsIII,mipsIV:
5081 *vr5000:
5082 // start-sanitize-vr5400
5083 *vr5400:
5084 // end-sanitize-vr5400
5085 // start-sanitize-r5900
5086 *r5900:
5087 // end-sanitize-r5900
5088
5089
5090 010000,10000,000000000000000,000110:COP0:32::TLBWR
5091 "tlbwr"
5092 *mipsI,mipsII,mipsIII,mipsIV:
5093 *vr5000:
5094 // start-sanitize-vr5400
5095 *vr5400:
5096 // end-sanitize-vr5400
5097 // start-sanitize-r5900
5098 *r5900:
5099 // end-sanitize-r5900
5100
5101 \f
5102 :include:::m16.igen
5103 // start-sanitize-vr5400
5104 :include::vr5400:vr5400.igen
5105 :include:::mdmx.igen
5106 // end-sanitize-vr5400
5107 // start-sanitize-r5900
5108 :include::r5900:r5900.igen
5109 // end-sanitize-r5900
5110 \f
5111 // start-sanitize-cygnus-never
5112
5113 // // FIXME FIXME FIXME What is this instruction?
5114 // 111011,5.RS,5.RT,16.OFFSET:NORMAL:32::<INT>
5115 // *mipsI:
5116 // *mipsII:
5117 // *mipsIII:
5118 // *mipsIV:
5119 // // start-sanitize-r5900
5120 // *r5900:
5121 // // end-sanitize-r5900
5122 // *r3900:
5123 // // start-sanitize-tx19
5124 // *tx19:
5125 // // end-sanitize-tx19
5126 // {
5127 //   unsigned32 instruction = instruction_0;
5128 //   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
5129 //   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5130 //   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5131 //   {
5132 //     if (CoProcPresent(3))
5133 //       SignalException(CoProcessorUnusable);
5134 //     else
5135 //       SignalException(ReservedInstruction,instruction);
5136 //   }
5137 // }
5138
5139 // end-sanitize-cygnus-never
5140 // start-sanitize-cygnus-never
5141
5142 // // FIXME FIXME FIXME What is this?
5143 // 11100,******,00001:RR:16::SDBBP
5144 // *mips16:
5145 // {
5146 //   unsigned32 instruction = instruction_0;
5147 //   if (have_extendval)
5148 //     SignalException (ReservedInstruction, instruction);
5149 //   {
5150 //     SignalException(DebugBreakPoint,instruction);
5151 //   }
5152 // }
5153
5154 // end-sanitize-cygnus-never
5155 // start-sanitize-cygnus-never
5156
5157 // // FIXME FIXME FIXME What is this?
5158 // 000000,********************,001110:SPECIAL:32::SDBBP
5159 // *r3900:
5160 // {
5161 //   unsigned32 instruction = instruction_0;
5162 //   {
5163 //     SignalException(DebugBreakPoint,instruction);
5164 //   }
5165 // }
5166
5167 // end-sanitize-cygnus-never
5168 // start-sanitize-cygnus-never
5169
5170 // // FIXME FIXME FIXME This apparently belongs to the vr4100 which
5171 // // isn't yet reconized by this simulator.
5172 // 000000,5.RS,5.RT,0000000000101000:SPECIAL:32::MADD16
5173 // *vr4100:
5174 // {
5175 //   unsigned32 instruction = instruction_0;
5176 //   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5177 //   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5178 //   {
5179 //     CHECKHILO("Multiply-Add");
5180 //     {
5181 //       unsigned64 temp = (op1 * op2);
5182 //       temp += (SET64HI(VL4_8(HI)) | VL4_8(LO));
5183 //       LO = SIGNEXTEND((unsigned64)VL4_8(temp),32);
5184 //       HI = SIGNEXTEND((unsigned64)VH4_8(temp),32);
5185 //     }
5186 //   }
5187 // }
5188
5189 // end-sanitize-cygnus-never
5190 // start-sanitize-cygnus-never
5191
5192 // // FIXME FIXME FIXME This apparently belongs to the vr4100 which
5193 // // isn't yet reconized by this simulator.
5194 // 000000,5.RS,5.RT,0000000000101001:SPECIAL:64::DMADD16
5195 // *vr4100:
5196 // {
5197 //   unsigned32 instruction = instruction_0;
5198 //   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5199 //   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5200 //   {
5201 //     CHECKHILO("Multiply-Add");
5202 //     {
5203 //       unsigned64 temp = (op1 * op2);
5204 //       LO = LO + temp;
5205 //     }
5206 //   }
5207 // }
5208
5209 // start-sanitize-cygnus-never