3 // In mips.igen, the semantics for many of the instructions were created
4 // using code generated by gencode. Those semantic segments could be
8 // <insn-word> { "+" <insn-word> }
15 // { <insn-mnemonic> }
20 // IGEN config - mips16
21 // :option:16::insn-bit-size:16
22 // :option:16::hi-bit-nr:15
23 :option:16::insn-specifying-widths:true
24 :option:16::gen-delayed-branch:false
26 // IGEN config - mips32/64..
27 // :option:32::insn-bit-size:32
28 // :option:32::hi-bit-nr:31
29 :option:32::insn-specifying-widths:true
30 :option:32::gen-delayed-branch:false
33 // Generate separate simulators for each target
34 // :option:::multi-sim:true
37 // Models known by this simulator are defined below.
39 // When placing models in the instruction descriptions, please place
40 // them one per line, in the order given here.
44 // Instructions and related functions for these models are included in
46 :model:::mipsI:mips3000:
47 :model:::mipsII:mips6000:
48 :model:::mipsIII:mips4000:
49 :model:::mipsIV:mips8000:
50 :model:::mipsV:mipsisaV:
54 // Standard MIPS ISA instructions used for these models are listed here,
55 // as are functions needed by those standard instructions. Instructions
56 // which are model-dependent and which are not in the standard MIPS ISAs
57 // (or which pre-date or use different encodings than the standard
58 // instructions) are (for the most part) in separate .igen files.
59 :model:::vr4100:mips4100: // vr.igen
60 :model:::vr5000:mips5000:
61 :model:::r3900:mips3900: // tx.igen
63 // MIPS Application Specific Extensions (ASEs)
65 // Instructions for the ASEs are in separate .igen files.
66 :model:::mips16:mips16: // m16.igen (and m16.dc)
69 // Pseudo instructions known by IGEN
72 SignalException (ReservedInstruction, 0);
76 // Pseudo instructions known by interp.c
77 // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
78 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
81 SignalException (ReservedInstruction, instruction_0);
88 // Simulate a 32 bit delayslot instruction
91 :function:::address_word:delayslot32:address_word target
93 instruction_word delay_insn;
94 sim_events_slip (SD, 1);
96 CIA = CIA + 4; /* NOTE not mips16 */
97 STATE |= simDELAYSLOT;
98 delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
99 ENGINE_ISSUE_PREFIX_HOOK();
100 idecode_issue (CPU_, delay_insn, (CIA));
101 STATE &= ~simDELAYSLOT;
105 :function:::address_word:nullify_next_insn32:
107 sim_events_slip (SD, 1);
108 dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
115 // Calculate an effective address given a base and an offset.
118 :function:::address_word:loadstore_ea:address_word base, address_word offset
128 return base + offset;
134 // Check that an access to a HI/LO register meets timing requirements
136 // The following requirements exist:
138 // - A MT {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
139 // - A OP {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
140 // - A MF {HI,LO} read was not corrupted by a preceeding MT{LO,HI} update
141 // corruption occures when MT{LO,HI} is preceeded by a OP {HI,LO}.
144 :function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
146 if (history->mf.timestamp + 3 > time)
148 sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
149 itable[MY_INDEX].name,
151 (long) history->mf.cia);
157 :function:::int:check_mt_hilo:hilo_history *history
166 signed64 time = sim_events_time (SD);
167 int ok = check_mf_cycles (SD_, history, time, "MT");
168 history->mt.timestamp = time;
169 history->mt.cia = CIA;
173 :function:::int:check_mt_hilo:hilo_history *history
176 signed64 time = sim_events_time (SD);
177 history->mt.timestamp = time;
178 history->mt.cia = CIA;
183 :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
193 signed64 time = sim_events_time (SD);
196 && peer->mt.timestamp > history->op.timestamp
197 && history->mt.timestamp < history->op.timestamp
198 && ! (history->mf.timestamp > history->op.timestamp
199 && history->mf.timestamp < peer->mt.timestamp)
200 && ! (peer->mf.timestamp > history->op.timestamp
201 && peer->mf.timestamp < peer->mt.timestamp))
203 /* The peer has been written to since the last OP yet we have
205 sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
206 itable[MY_INDEX].name,
208 (long) history->op.cia,
209 (long) peer->mt.cia);
212 history->mf.timestamp = time;
213 history->mf.cia = CIA;
219 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
228 signed64 time = sim_events_time (SD);
229 int ok = (check_mf_cycles (SD_, hi, time, "OP")
230 && check_mf_cycles (SD_, lo, time, "OP"));
231 hi->op.timestamp = time;
232 lo->op.timestamp = time;
238 // The r3900 mult and multu insns _can_ be exectuted immediatly after
240 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
243 /* FIXME: could record the fact that a stall occured if we want */
244 signed64 time = sim_events_time (SD);
245 hi->op.timestamp = time;
246 lo->op.timestamp = time;
253 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
263 signed64 time = sim_events_time (SD);
264 int ok = (check_mf_cycles (SD_, hi, time, "OP")
265 && check_mf_cycles (SD_, lo, time, "OP"));
266 hi->op.timestamp = time;
267 lo->op.timestamp = time;
276 // Check that the 64-bit instruction can currently be used, and signal
277 // an ReservedInstruction exception if not.
280 :function:::void:check_u64:instruction_word insn
287 // On mips64, if UserMode check SR:PX & SR:UX bits.
288 // The check should be similar to mips64 for any with PX/UX bit equivalents.
294 // MIPS Architecture:
296 // CPU Instruction Set (mipsI - mipsV)
301 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
302 "add r<RD>, r<RS>, r<RT>"
312 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
314 ALU32_BEGIN (GPR[RS]);
316 ALU32_END (GPR[RD]); /* This checks for overflow. */
318 TRACE_ALU_RESULT (GPR[RD]);
323 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
324 "addi r<RT>, r<RS>, <IMMEDIATE>"
334 TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
336 ALU32_BEGIN (GPR[RS]);
337 ALU32_ADD (EXTEND16 (IMMEDIATE));
338 ALU32_END (GPR[RT]); /* This checks for overflow. */
340 TRACE_ALU_RESULT (GPR[RT]);
345 :function:::void:do_addiu:int rs, int rt, unsigned16 immediate
347 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
348 GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
349 TRACE_ALU_RESULT (GPR[rt]);
352 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
353 "addiu r<RT>, r<RS>, <IMMEDIATE>"
363 do_addiu (SD_, RS, RT, IMMEDIATE);
368 :function:::void:do_addu:int rs, int rt, int rd
370 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
371 GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
372 TRACE_ALU_RESULT (GPR[rd]);
375 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
376 "addu r<RD>, r<RS>, r<RT>"
386 do_addu (SD_, RS, RT, RD);
391 :function:::void:do_and:int rs, int rt, int rd
393 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
394 GPR[rd] = GPR[rs] & GPR[rt];
395 TRACE_ALU_RESULT (GPR[rd]);
398 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
399 "and r<RD>, r<RS>, r<RT>"
409 do_and (SD_, RS, RT, RD);
414 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
415 "and r<RT>, r<RS>, <IMMEDIATE>"
425 TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
426 GPR[RT] = GPR[RS] & IMMEDIATE;
427 TRACE_ALU_RESULT (GPR[RT]);
432 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
433 "beq r<RS>, r<RT>, <OFFSET>"
443 address_word offset = EXTEND16 (OFFSET) << 2;
445 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
447 mark_branch_bug (NIA+offset);
448 DELAY_SLOT (NIA + offset);
454 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
455 "beql r<RS>, r<RT>, <OFFSET>"
464 address_word offset = EXTEND16 (OFFSET) << 2;
466 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
468 mark_branch_bug (NIA+offset);
469 DELAY_SLOT (NIA + offset);
472 NULLIFY_NEXT_INSTRUCTION ();
477 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
478 "bgez r<RS>, <OFFSET>"
488 address_word offset = EXTEND16 (OFFSET) << 2;
490 if ((signed_word) GPR[RS] >= 0)
492 mark_branch_bug (NIA+offset);
493 DELAY_SLOT (NIA + offset);
499 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
500 "bgezal r<RS>, <OFFSET>"
510 address_word offset = EXTEND16 (OFFSET) << 2;
513 if ((signed_word) GPR[RS] >= 0)
515 mark_branch_bug (NIA+offset);
516 DELAY_SLOT (NIA + offset);
522 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
523 "bgezall r<RS>, <OFFSET>"
532 address_word offset = EXTEND16 (OFFSET) << 2;
535 /* NOTE: The branch occurs AFTER the next instruction has been
537 if ((signed_word) GPR[RS] >= 0)
539 mark_branch_bug (NIA+offset);
540 DELAY_SLOT (NIA + offset);
543 NULLIFY_NEXT_INSTRUCTION ();
548 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
549 "bgezl r<RS>, <OFFSET>"
558 address_word offset = EXTEND16 (OFFSET) << 2;
560 if ((signed_word) GPR[RS] >= 0)
562 mark_branch_bug (NIA+offset);
563 DELAY_SLOT (NIA + offset);
566 NULLIFY_NEXT_INSTRUCTION ();
571 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
572 "bgtz r<RS>, <OFFSET>"
582 address_word offset = EXTEND16 (OFFSET) << 2;
584 if ((signed_word) GPR[RS] > 0)
586 mark_branch_bug (NIA+offset);
587 DELAY_SLOT (NIA + offset);
593 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
594 "bgtzl r<RS>, <OFFSET>"
603 address_word offset = EXTEND16 (OFFSET) << 2;
605 /* NOTE: The branch occurs AFTER the next instruction has been
607 if ((signed_word) GPR[RS] > 0)
609 mark_branch_bug (NIA+offset);
610 DELAY_SLOT (NIA + offset);
613 NULLIFY_NEXT_INSTRUCTION ();
618 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
619 "blez r<RS>, <OFFSET>"
629 address_word offset = EXTEND16 (OFFSET) << 2;
631 /* NOTE: The branch occurs AFTER the next instruction has been
633 if ((signed_word) GPR[RS] <= 0)
635 mark_branch_bug (NIA+offset);
636 DELAY_SLOT (NIA + offset);
642 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
643 "bgezl r<RS>, <OFFSET>"
652 address_word offset = EXTEND16 (OFFSET) << 2;
654 if ((signed_word) GPR[RS] <= 0)
656 mark_branch_bug (NIA+offset);
657 DELAY_SLOT (NIA + offset);
660 NULLIFY_NEXT_INSTRUCTION ();
665 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
666 "bltz r<RS>, <OFFSET>"
676 address_word offset = EXTEND16 (OFFSET) << 2;
678 if ((signed_word) GPR[RS] < 0)
680 mark_branch_bug (NIA+offset);
681 DELAY_SLOT (NIA + offset);
687 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
688 "bltzal r<RS>, <OFFSET>"
698 address_word offset = EXTEND16 (OFFSET) << 2;
701 /* NOTE: The branch occurs AFTER the next instruction has been
703 if ((signed_word) GPR[RS] < 0)
705 mark_branch_bug (NIA+offset);
706 DELAY_SLOT (NIA + offset);
712 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
713 "bltzall r<RS>, <OFFSET>"
722 address_word offset = EXTEND16 (OFFSET) << 2;
725 if ((signed_word) GPR[RS] < 0)
727 mark_branch_bug (NIA+offset);
728 DELAY_SLOT (NIA + offset);
731 NULLIFY_NEXT_INSTRUCTION ();
736 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
737 "bltzl r<RS>, <OFFSET>"
746 address_word offset = EXTEND16 (OFFSET) << 2;
748 /* NOTE: The branch occurs AFTER the next instruction has been
750 if ((signed_word) GPR[RS] < 0)
752 mark_branch_bug (NIA+offset);
753 DELAY_SLOT (NIA + offset);
756 NULLIFY_NEXT_INSTRUCTION ();
761 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
762 "bne r<RS>, r<RT>, <OFFSET>"
772 address_word offset = EXTEND16 (OFFSET) << 2;
774 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
776 mark_branch_bug (NIA+offset);
777 DELAY_SLOT (NIA + offset);
783 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
784 "bnel r<RS>, r<RT>, <OFFSET>"
793 address_word offset = EXTEND16 (OFFSET) << 2;
795 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
797 mark_branch_bug (NIA+offset);
798 DELAY_SLOT (NIA + offset);
801 NULLIFY_NEXT_INSTRUCTION ();
806 000000,20.CODE,001101:SPECIAL:32::BREAK
817 /* Check for some break instruction which are reserved for use by the simulator. */
818 unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
819 if (break_code == (HALT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
820 break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
822 sim_engine_halt (SD, CPU, NULL, cia,
823 sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
825 else if (break_code == (BREAKPOINT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
826 break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
828 if (STATE & simDELAYSLOT)
829 PC = cia - 4; /* reference the branch instruction */
832 SignalException(BreakPoint, instruction_0);
837 /* If we get this far, we're not an instruction reserved by the sim. Raise
839 SignalException(BreakPoint, instruction_0);
845 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
846 "dadd r<RD>, r<RS>, r<RT>"
853 check_u64 (SD_, instruction_0);
854 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
856 ALU64_BEGIN (GPR[RS]);
858 ALU64_END (GPR[RD]); /* This checks for overflow. */
860 TRACE_ALU_RESULT (GPR[RD]);
865 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
866 "daddi r<RT>, r<RS>, <IMMEDIATE>"
873 check_u64 (SD_, instruction_0);
874 TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
876 ALU64_BEGIN (GPR[RS]);
877 ALU64_ADD (EXTEND16 (IMMEDIATE));
878 ALU64_END (GPR[RT]); /* This checks for overflow. */
880 TRACE_ALU_RESULT (GPR[RT]);
885 :function:::void:do_daddiu:int rs, int rt, unsigned16 immediate
887 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
888 GPR[rt] = GPR[rs] + EXTEND16 (immediate);
889 TRACE_ALU_RESULT (GPR[rt]);
892 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
893 "daddiu r<RT>, r<RS>, <IMMEDIATE>"
900 check_u64 (SD_, instruction_0);
901 do_daddiu (SD_, RS, RT, IMMEDIATE);
906 :function:::void:do_daddu:int rs, int rt, int rd
908 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
909 GPR[rd] = GPR[rs] + GPR[rt];
910 TRACE_ALU_RESULT (GPR[rd]);
913 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
914 "daddu r<RD>, r<RS>, r<RT>"
921 check_u64 (SD_, instruction_0);
922 do_daddu (SD_, RS, RT, RD);
927 :function:::void:do_ddiv:int rs, int rt
929 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
930 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
932 signed64 n = GPR[rs];
933 signed64 d = GPR[rt];
938 lo = SIGNED64 (0x8000000000000000);
941 else if (d == -1 && n == SIGNED64 (0x8000000000000000))
943 lo = SIGNED64 (0x8000000000000000);
954 TRACE_ALU_RESULT2 (HI, LO);
957 000000,5.RS,5.RT,0000000000,011110:SPECIAL:64::DDIV
965 check_u64 (SD_, instruction_0);
966 do_ddiv (SD_, RS, RT);
971 :function:::void:do_ddivu:int rs, int rt
973 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
974 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
976 unsigned64 n = GPR[rs];
977 unsigned64 d = GPR[rt];
982 lo = SIGNED64 (0x8000000000000000);
993 TRACE_ALU_RESULT2 (HI, LO);
996 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
1004 check_u64 (SD_, instruction_0);
1005 do_ddivu (SD_, RS, RT);
1010 :function:::void:do_div:int rs, int rt
1012 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1013 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1015 signed32 n = GPR[rs];
1016 signed32 d = GPR[rt];
1019 LO = EXTEND32 (0x80000000);
1022 else if (n == SIGNED32 (0x80000000) && d == -1)
1024 LO = EXTEND32 (0x80000000);
1029 LO = EXTEND32 (n / d);
1030 HI = EXTEND32 (n % d);
1033 TRACE_ALU_RESULT2 (HI, LO);
1036 000000,5.RS,5.RT,0000000000,011010:SPECIAL:32::DIV
1047 do_div (SD_, RS, RT);
1052 :function:::void:do_divu:int rs, int rt
1054 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1055 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1057 unsigned32 n = GPR[rs];
1058 unsigned32 d = GPR[rt];
1061 LO = EXTEND32 (0x80000000);
1066 LO = EXTEND32 (n / d);
1067 HI = EXTEND32 (n % d);
1070 TRACE_ALU_RESULT2 (HI, LO);
1073 000000,5.RS,5.RT,0000000000,011011:SPECIAL:32::DIVU
1084 do_divu (SD_, RS, RT);
1089 :function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
1099 unsigned64 op1 = GPR[rs];
1100 unsigned64 op2 = GPR[rt];
1101 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1102 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1103 /* make signed multiply unsigned */
1118 /* multiply out the 4 sub products */
1119 m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
1120 m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
1121 m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
1122 m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
1123 /* add the products */
1124 mid = ((unsigned64) VH4_8 (m00)
1125 + (unsigned64) VL4_8 (m10)
1126 + (unsigned64) VL4_8 (m01));
1127 lo = U8_4 (mid, m00);
1129 + (unsigned64) VH4_8 (mid)
1130 + (unsigned64) VH4_8 (m01)
1131 + (unsigned64) VH4_8 (m10));
1141 /* save the result HI/LO (and a gpr) */
1146 TRACE_ALU_RESULT2 (HI, LO);
1149 :function:::void:do_dmult:int rs, int rt, int rd
1151 do_dmultx (SD_, rs, rt, rd, 1);
1154 000000,5.RS,5.RT,0000000000,011100:SPECIAL:64::DMULT
1155 "dmult r<RS>, r<RT>"
1161 check_u64 (SD_, instruction_0);
1162 do_dmult (SD_, RS, RT, 0);
1165 000000,5.RS,5.RT,5.RD,00000,011100:SPECIAL:64::DMULT
1166 "dmult r<RS>, r<RT>":RD == 0
1167 "dmult r<RD>, r<RS>, r<RT>"
1170 check_u64 (SD_, instruction_0);
1171 do_dmult (SD_, RS, RT, RD);
1176 :function:::void:do_dmultu:int rs, int rt, int rd
1178 do_dmultx (SD_, rs, rt, rd, 0);
1181 000000,5.RS,5.RT,0000000000,011101:SPECIAL:64::DMULTU
1182 "dmultu r<RS>, r<RT>"
1188 check_u64 (SD_, instruction_0);
1189 do_dmultu (SD_, RS, RT, 0);
1192 000000,5.RS,5.RT,5.RD,00000,011101:SPECIAL:64::DMULTU
1193 "dmultu r<RD>, r<RS>, r<RT>":RD == 0
1194 "dmultu r<RS>, r<RT>"
1197 check_u64 (SD_, instruction_0);
1198 do_dmultu (SD_, RS, RT, RD);
1201 :function:::void:do_dsll:int rt, int rd, int shift
1203 TRACE_ALU_INPUT2 (GPR[rt], shift);
1204 GPR[rd] = GPR[rt] << shift;
1205 TRACE_ALU_RESULT (GPR[rd]);
1208 000000,00000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
1209 "dsll r<RD>, r<RT>, <SHIFT>"
1216 check_u64 (SD_, instruction_0);
1217 do_dsll (SD_, RT, RD, SHIFT);
1221 000000,00000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
1222 "dsll32 r<RD>, r<RT>, <SHIFT>"
1230 check_u64 (SD_, instruction_0);
1231 TRACE_ALU_INPUT2 (GPR[RT], s);
1232 GPR[RD] = GPR[RT] << s;
1233 TRACE_ALU_RESULT (GPR[RD]);
1236 :function:::void:do_dsllv:int rs, int rt, int rd
1238 int s = MASKED64 (GPR[rs], 5, 0);
1239 TRACE_ALU_INPUT2 (GPR[rt], s);
1240 GPR[rd] = GPR[rt] << s;
1241 TRACE_ALU_RESULT (GPR[rd]);
1244 000000,5.RS,5.RT,5.RD,00000,010100:SPECIAL:64::DSLLV
1245 "dsllv r<RD>, r<RT>, r<RS>"
1252 check_u64 (SD_, instruction_0);
1253 do_dsllv (SD_, RS, RT, RD);
1256 :function:::void:do_dsra:int rt, int rd, int shift
1258 TRACE_ALU_INPUT2 (GPR[rt], shift);
1259 GPR[rd] = ((signed64) GPR[rt]) >> shift;
1260 TRACE_ALU_RESULT (GPR[rd]);
1264 000000,00000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
1265 "dsra r<RD>, r<RT>, <SHIFT>"
1272 check_u64 (SD_, instruction_0);
1273 do_dsra (SD_, RT, RD, SHIFT);
1277 000000,00000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
1278 "dsra32 r<RD>, r<RT>, <SHIFT>"
1286 check_u64 (SD_, instruction_0);
1287 TRACE_ALU_INPUT2 (GPR[RT], s);
1288 GPR[RD] = ((signed64) GPR[RT]) >> s;
1289 TRACE_ALU_RESULT (GPR[RD]);
1293 :function:::void:do_dsrav:int rs, int rt, int rd
1295 int s = MASKED64 (GPR[rs], 5, 0);
1296 TRACE_ALU_INPUT2 (GPR[rt], s);
1297 GPR[rd] = ((signed64) GPR[rt]) >> s;
1298 TRACE_ALU_RESULT (GPR[rd]);
1301 000000,5.RS,5.RT,5.RD,00000,010111:SPECIAL:64::DSRAV
1302 "dsrav r<RD>, r<RT>, r<RS>"
1309 check_u64 (SD_, instruction_0);
1310 do_dsrav (SD_, RS, RT, RD);
1313 :function:::void:do_dsrl:int rt, int rd, int shift
1315 TRACE_ALU_INPUT2 (GPR[rt], shift);
1316 GPR[rd] = (unsigned64) GPR[rt] >> shift;
1317 TRACE_ALU_RESULT (GPR[rd]);
1321 000000,00000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
1322 "dsrl r<RD>, r<RT>, <SHIFT>"
1329 check_u64 (SD_, instruction_0);
1330 do_dsrl (SD_, RT, RD, SHIFT);
1334 000000,00000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
1335 "dsrl32 r<RD>, r<RT>, <SHIFT>"
1343 check_u64 (SD_, instruction_0);
1344 TRACE_ALU_INPUT2 (GPR[RT], s);
1345 GPR[RD] = (unsigned64) GPR[RT] >> s;
1346 TRACE_ALU_RESULT (GPR[RD]);
1350 :function:::void:do_dsrlv:int rs, int rt, int rd
1352 int s = MASKED64 (GPR[rs], 5, 0);
1353 TRACE_ALU_INPUT2 (GPR[rt], s);
1354 GPR[rd] = (unsigned64) GPR[rt] >> s;
1355 TRACE_ALU_RESULT (GPR[rd]);
1360 000000,5.RS,5.RT,5.RD,00000,010110:SPECIAL:64::DSRLV
1361 "dsrlv r<RD>, r<RT>, r<RS>"
1368 check_u64 (SD_, instruction_0);
1369 do_dsrlv (SD_, RS, RT, RD);
1373 000000,5.RS,5.RT,5.RD,00000,101110:SPECIAL:64::DSUB
1374 "dsub r<RD>, r<RS>, r<RT>"
1381 check_u64 (SD_, instruction_0);
1382 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1384 ALU64_BEGIN (GPR[RS]);
1385 ALU64_SUB (GPR[RT]);
1386 ALU64_END (GPR[RD]); /* This checks for overflow. */
1388 TRACE_ALU_RESULT (GPR[RD]);
1392 :function:::void:do_dsubu:int rs, int rt, int rd
1394 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1395 GPR[rd] = GPR[rs] - GPR[rt];
1396 TRACE_ALU_RESULT (GPR[rd]);
1399 000000,5.RS,5.RT,5.RD,00000,101111:SPECIAL:64::DSUBU
1400 "dsubu r<RD>, r<RS>, r<RT>"
1407 check_u64 (SD_, instruction_0);
1408 do_dsubu (SD_, RS, RT, RD);
1412 000010,26.INSTR_INDEX:NORMAL:32::J
1423 /* NOTE: The region used is that of the delay slot NIA and NOT the
1424 current instruction */
1425 address_word region = (NIA & MASK (63, 28));
1426 DELAY_SLOT (region | (INSTR_INDEX << 2));
1430 000011,26.INSTR_INDEX:NORMAL:32::JAL
1441 /* NOTE: The region used is that of the delay slot and NOT the
1442 current instruction */
1443 address_word region = (NIA & MASK (63, 28));
1445 DELAY_SLOT (region | (INSTR_INDEX << 2));
1448 000000,5.RS,00000,5.RD,00000,001001:SPECIAL:32::JALR
1449 "jalr r<RS>":RD == 31
1460 address_word temp = GPR[RS];
1466 000000,5.RS,000000000000000,001000:SPECIAL:32::JR
1477 DELAY_SLOT (GPR[RS]);
1481 :function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
1483 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1484 address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
1485 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
1492 vaddr = loadstore_ea (SD_, base, offset);
1493 if ((vaddr & access) != 0)
1495 SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal);
1497 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1498 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1499 LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
1500 byte = ((vaddr & mask) ^ bigendiancpu);
1501 return (memval >> (8 * byte));
1504 :function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
1506 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1507 address_word reverseendian = (ReverseEndian ? -1 : 0);
1508 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
1517 unsigned_word lhs_mask;
1520 vaddr = loadstore_ea (SD_, base, offset);
1521 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1522 paddr = (paddr ^ (reverseendian & mask));
1523 if (BigEndianMem == 0)
1524 paddr = paddr & ~access;
1526 /* compute where within the word/mem we are */
1527 byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
1528 word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
1529 nr_lhs_bits = 8 * byte + 8;
1530 nr_rhs_bits = 8 * access - 8 * byte;
1531 /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
1533 /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
1534 (long) ((unsigned64) vaddr >> 32), (long) vaddr,
1535 (long) ((unsigned64) paddr >> 32), (long) paddr,
1536 word, byte, nr_lhs_bits, nr_rhs_bits); */
1538 LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
1541 /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
1542 temp = (memval << nr_rhs_bits);
1546 /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
1547 temp = (memval >> nr_lhs_bits);
1549 lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
1550 rt = (rt & ~lhs_mask) | (temp & lhs_mask);
1552 /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
1553 (long) ((unsigned64) memval >> 32), (long) memval,
1554 (long) ((unsigned64) temp >> 32), (long) temp,
1555 (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
1556 (long) (rt >> 32), (long) rt); */
1560 :function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
1562 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1563 address_word reverseendian = (ReverseEndian ? -1 : 0);
1564 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
1571 vaddr = loadstore_ea (SD_, base, offset);
1572 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1573 /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
1574 paddr = (paddr ^ (reverseendian & mask));
1575 if (BigEndianMem != 0)
1576 paddr = paddr & ~access;
1577 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
1578 /* NOTE: SPEC is wrong, had `byte' not `access - byte'. See SW. */
1579 LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
1580 /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
1581 (long) paddr, byte, (long) paddr, (long) memval); */
1583 unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
1585 rt |= (memval >> (8 * byte)) & screen;
1591 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
1592 "lb r<RT>, <OFFSET>(r<BASE>)"
1602 GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
1606 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
1607 "lbu r<RT>, <OFFSET>(r<BASE>)"
1617 GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
1621 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
1622 "ld r<RT>, <OFFSET>(r<BASE>)"
1629 check_u64 (SD_, instruction_0);
1630 GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1634 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
1635 "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1644 COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1650 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
1651 "ldl r<RT>, <OFFSET>(r<BASE>)"
1658 check_u64 (SD_, instruction_0);
1659 GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1663 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
1664 "ldr r<RT>, <OFFSET>(r<BASE>)"
1671 check_u64 (SD_, instruction_0);
1672 GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1676 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
1677 "lh r<RT>, <OFFSET>(r<BASE>)"
1687 GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
1691 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
1692 "lhu r<RT>, <OFFSET>(r<BASE>)"
1702 GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
1706 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
1707 "ll r<RT>, <OFFSET>(r<BASE>)"
1715 address_word base = GPR[BASE];
1716 address_word offset = EXTEND16 (OFFSET);
1718 address_word vaddr = loadstore_ea (SD_, base, offset);
1721 if ((vaddr & 3) != 0)
1723 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer, sim_core_unaligned_signal);
1727 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1729 unsigned64 memval = 0;
1730 unsigned64 memval1 = 0;
1731 unsigned64 mask = 0x7;
1732 unsigned int shift = 2;
1733 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1734 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1736 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1737 LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
1738 byte = ((vaddr & mask) ^ (bigend << shift));
1739 GPR[RT] = EXTEND32 (memval >> (8 * byte));
1747 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
1748 "lld r<RT>, <OFFSET>(r<BASE>)"
1755 address_word base = GPR[BASE];
1756 address_word offset = EXTEND16 (OFFSET);
1757 check_u64 (SD_, instruction_0);
1759 address_word vaddr = loadstore_ea (SD_, base, offset);
1762 if ((vaddr & 7) != 0)
1764 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer, sim_core_unaligned_signal);
1768 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1770 unsigned64 memval = 0;
1771 unsigned64 memval1 = 0;
1772 LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
1781 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
1782 "lui r<RT>, <IMMEDIATE>"
1792 TRACE_ALU_INPUT1 (IMMEDIATE);
1793 GPR[RT] = EXTEND32 (IMMEDIATE << 16);
1794 TRACE_ALU_RESULT (GPR[RT]);
1798 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
1799 "lw r<RT>, <OFFSET>(r<BASE>)"
1809 GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
1813 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
1814 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1824 COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
1828 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
1829 "lwl r<RT>, <OFFSET>(r<BASE>)"
1839 GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
1843 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
1844 "lwr r<RT>, <OFFSET>(r<BASE>)"
1854 GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
1858 100111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LWU
1859 "lwu r<RT>, <OFFSET>(r<BASE>)"
1866 check_u64 (SD_, instruction_0);
1867 GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
1871 :function:::void:do_mfhi:int rd
1873 check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
1874 TRACE_ALU_INPUT1 (HI);
1876 TRACE_ALU_RESULT (GPR[rd]);
1879 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
1895 :function:::void:do_mflo:int rd
1897 check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
1898 TRACE_ALU_INPUT1 (LO);
1900 TRACE_ALU_RESULT (GPR[rd]);
1903 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
1919 000000,5.RS,5.RT,5.RD,00000,001011:SPECIAL:32::MOVN
1920 "movn r<RD>, r<RS>, r<RT>"
1931 000000,5.RS,5.RT,5.RD,00000,001010:SPECIAL:32::MOVZ
1932 "movz r<RD>, r<RS>, r<RT>"
1943 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
1954 check_mt_hilo (SD_, HIHISTORY);
1960 000000,5.RS,000000000000000,010011:SPECIAL:32::MTLO
1971 check_mt_hilo (SD_, LOHISTORY);
1977 :function:::void:do_mult:int rs, int rt, int rd
1980 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1981 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1982 prod = (((signed64)(signed32) GPR[rs])
1983 * ((signed64)(signed32) GPR[rt]));
1984 LO = EXTEND32 (VL4_8 (prod));
1985 HI = EXTEND32 (VH4_8 (prod));
1988 TRACE_ALU_RESULT2 (HI, LO);
1991 000000,5.RS,5.RT,0000000000,011000:SPECIAL:32::MULT
2000 do_mult (SD_, RS, RT, 0);
2004 000000,5.RS,5.RT,5.RD,00000,011000:SPECIAL:32::MULT
2005 "mult r<RS>, r<RT>":RD == 0
2006 "mult r<RD>, r<RS>, r<RT>"
2010 do_mult (SD_, RS, RT, RD);
2014 :function:::void:do_multu:int rs, int rt, int rd
2017 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2018 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2019 prod = (((unsigned64)(unsigned32) GPR[rs])
2020 * ((unsigned64)(unsigned32) GPR[rt]));
2021 LO = EXTEND32 (VL4_8 (prod));
2022 HI = EXTEND32 (VH4_8 (prod));
2025 TRACE_ALU_RESULT2 (HI, LO);
2028 000000,5.RS,5.RT,0000000000,011001:SPECIAL:32::MULTU
2029 "multu r<RS>, r<RT>"
2037 do_multu (SD_, RS, RT, 0);
2040 000000,5.RS,5.RT,5.RD,00000,011001:SPECIAL:32::MULTU
2041 "multu r<RS>, r<RT>":RD == 0
2042 "multu r<RD>, r<RS>, r<RT>"
2046 do_multu (SD_, RS, RT, RD);
2050 :function:::void:do_nor:int rs, int rt, int rd
2052 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2053 GPR[rd] = ~ (GPR[rs] | GPR[rt]);
2054 TRACE_ALU_RESULT (GPR[rd]);
2057 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
2058 "nor r<RD>, r<RS>, r<RT>"
2068 do_nor (SD_, RS, RT, RD);
2072 :function:::void:do_or:int rs, int rt, int rd
2074 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2075 GPR[rd] = (GPR[rs] | GPR[rt]);
2076 TRACE_ALU_RESULT (GPR[rd]);
2079 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
2080 "or r<RD>, r<RS>, r<RT>"
2090 do_or (SD_, RS, RT, RD);
2095 :function:::void:do_ori:int rs, int rt, unsigned immediate
2097 TRACE_ALU_INPUT2 (GPR[rs], immediate);
2098 GPR[rt] = (GPR[rs] | immediate);
2099 TRACE_ALU_RESULT (GPR[rt]);
2102 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
2103 "ori r<RT>, r<RS>, <IMMEDIATE>"
2113 do_ori (SD_, RS, RT, IMMEDIATE);
2117 110011,5.BASE,5.HINT,16.OFFSET:NORMAL:32::PREF
2118 "pref <HINT>, <OFFSET>(r<BASE>)"
2123 address_word base = GPR[BASE];
2124 address_word offset = EXTEND16 (OFFSET);
2126 address_word vaddr = loadstore_ea (SD_, base, offset);
2130 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2131 Prefetch(uncached,paddr,vaddr,isDATA,HINT);
2137 :function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
2139 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2140 address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
2141 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
2148 vaddr = loadstore_ea (SD_, base, offset);
2149 if ((vaddr & access) != 0)
2151 SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal);
2153 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2154 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
2155 byte = ((vaddr & mask) ^ bigendiancpu);
2156 memval = (word << (8 * byte));
2157 StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
2160 :function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
2162 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2163 address_word reverseendian = (ReverseEndian ? -1 : 0);
2164 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2174 vaddr = loadstore_ea (SD_, base, offset);
2175 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2176 paddr = (paddr ^ (reverseendian & mask));
2177 if (BigEndianMem == 0)
2178 paddr = paddr & ~access;
2180 /* compute where within the word/mem we are */
2181 byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
2182 word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
2183 nr_lhs_bits = 8 * byte + 8;
2184 nr_rhs_bits = 8 * access - 8 * byte;
2185 /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
2186 /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
2187 (long) ((unsigned64) vaddr >> 32), (long) vaddr,
2188 (long) ((unsigned64) paddr >> 32), (long) paddr,
2189 word, byte, nr_lhs_bits, nr_rhs_bits); */
2193 memval = (rt >> nr_rhs_bits);
2197 memval = (rt << nr_lhs_bits);
2199 /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
2200 (long) ((unsigned64) rt >> 32), (long) rt,
2201 (long) ((unsigned64) memval >> 32), (long) memval); */
2202 StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
2205 :function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
2207 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2208 address_word reverseendian = (ReverseEndian ? -1 : 0);
2209 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2216 vaddr = loadstore_ea (SD_, base, offset);
2217 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2218 paddr = (paddr ^ (reverseendian & mask));
2219 if (BigEndianMem != 0)
2221 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2222 memval = (rt << (byte * 8));
2223 StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
2227 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
2228 "sb r<RT>, <OFFSET>(r<BASE>)"
2238 do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2242 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
2243 "sc r<RT>, <OFFSET>(r<BASE>)"
2251 unsigned32 instruction = instruction_0;
2252 address_word base = GPR[BASE];
2253 address_word offset = EXTEND16 (OFFSET);
2255 address_word vaddr = loadstore_ea (SD_, base, offset);
2258 if ((vaddr & 3) != 0)
2260 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
2264 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2266 unsigned64 memval = 0;
2267 unsigned64 memval1 = 0;
2268 unsigned64 mask = 0x7;
2270 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2271 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2272 memval = ((unsigned64) GPR[RT] << (8 * byte));
2275 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2284 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
2285 "scd r<RT>, <OFFSET>(r<BASE>)"
2292 address_word base = GPR[BASE];
2293 address_word offset = EXTEND16 (OFFSET);
2294 check_u64 (SD_, instruction_0);
2296 address_word vaddr = loadstore_ea (SD_, base, offset);
2299 if ((vaddr & 7) != 0)
2301 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer, sim_core_unaligned_signal);
2305 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2307 unsigned64 memval = 0;
2308 unsigned64 memval1 = 0;
2312 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2321 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
2322 "sd r<RT>, <OFFSET>(r<BASE>)"
2329 check_u64 (SD_, instruction_0);
2330 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2334 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
2335 "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2343 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
2347 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
2348 "sdl r<RT>, <OFFSET>(r<BASE>)"
2355 check_u64 (SD_, instruction_0);
2356 do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2360 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
2361 "sdr r<RT>, <OFFSET>(r<BASE>)"
2368 check_u64 (SD_, instruction_0);
2369 do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2373 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
2374 "sh r<RT>, <OFFSET>(r<BASE>)"
2384 do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2388 :function:::void:do_sll:int rt, int rd, int shift
2390 unsigned32 temp = (GPR[rt] << shift);
2391 TRACE_ALU_INPUT2 (GPR[rt], shift);
2392 GPR[rd] = EXTEND32 (temp);
2393 TRACE_ALU_RESULT (GPR[rd]);
2396 000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
2397 "nop":RD == 0 && RT == 0 && SHIFT == 0
2398 "sll r<RD>, r<RT>, <SHIFT>"
2408 /* Skip shift for NOP, so that there won't be lots of extraneous
2410 if (RD != 0 || RT != 0 || SHIFT != 0)
2411 do_sll (SD_, RT, RD, SHIFT);
2415 :function:::void:do_sllv:int rs, int rt, int rd
2417 int s = MASKED (GPR[rs], 4, 0);
2418 unsigned32 temp = (GPR[rt] << s);
2419 TRACE_ALU_INPUT2 (GPR[rt], s);
2420 GPR[rd] = EXTEND32 (temp);
2421 TRACE_ALU_RESULT (GPR[rd]);
2424 000000,5.RS,5.RT,5.RD,00000,000100:SPECIAL:32::SLLV
2425 "sllv r<RD>, r<RT>, r<RS>"
2435 do_sllv (SD_, RS, RT, RD);
2439 :function:::void:do_slt:int rs, int rt, int rd
2441 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2442 GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
2443 TRACE_ALU_RESULT (GPR[rd]);
2446 000000,5.RS,5.RT,5.RD,00000,101010:SPECIAL:32::SLT
2447 "slt r<RD>, r<RS>, r<RT>"
2457 do_slt (SD_, RS, RT, RD);
2461 :function:::void:do_slti:int rs, int rt, unsigned16 immediate
2463 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2464 GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
2465 TRACE_ALU_RESULT (GPR[rt]);
2468 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
2469 "slti r<RT>, r<RS>, <IMMEDIATE>"
2479 do_slti (SD_, RS, RT, IMMEDIATE);
2483 :function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
2485 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2486 GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
2487 TRACE_ALU_RESULT (GPR[rt]);
2490 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
2491 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
2501 do_sltiu (SD_, RS, RT, IMMEDIATE);
2506 :function:::void:do_sltu:int rs, int rt, int rd
2508 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2509 GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
2510 TRACE_ALU_RESULT (GPR[rd]);
2513 000000,5.RS,5.RT,5.RD,00000,101011:SPECIAL:32::SLTU
2514 "sltu r<RD>, r<RS>, r<RT>"
2524 do_sltu (SD_, RS, RT, RD);
2528 :function:::void:do_sra:int rt, int rd, int shift
2530 signed32 temp = (signed32) GPR[rt] >> shift;
2531 TRACE_ALU_INPUT2 (GPR[rt], shift);
2532 GPR[rd] = EXTEND32 (temp);
2533 TRACE_ALU_RESULT (GPR[rd]);
2536 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
2537 "sra r<RD>, r<RT>, <SHIFT>"
2547 do_sra (SD_, RT, RD, SHIFT);
2552 :function:::void:do_srav:int rs, int rt, int rd
2554 int s = MASKED (GPR[rs], 4, 0);
2555 signed32 temp = (signed32) GPR[rt] >> s;
2556 TRACE_ALU_INPUT2 (GPR[rt], s);
2557 GPR[rd] = EXTEND32 (temp);
2558 TRACE_ALU_RESULT (GPR[rd]);
2561 000000,5.RS,5.RT,5.RD,00000,000111:SPECIAL:32::SRAV
2562 "srav r<RD>, r<RT>, r<RS>"
2572 do_srav (SD_, RS, RT, RD);
2577 :function:::void:do_srl:int rt, int rd, int shift
2579 unsigned32 temp = (unsigned32) GPR[rt] >> shift;
2580 TRACE_ALU_INPUT2 (GPR[rt], shift);
2581 GPR[rd] = EXTEND32 (temp);
2582 TRACE_ALU_RESULT (GPR[rd]);
2585 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
2586 "srl r<RD>, r<RT>, <SHIFT>"
2596 do_srl (SD_, RT, RD, SHIFT);
2600 :function:::void:do_srlv:int rs, int rt, int rd
2602 int s = MASKED (GPR[rs], 4, 0);
2603 unsigned32 temp = (unsigned32) GPR[rt] >> s;
2604 TRACE_ALU_INPUT2 (GPR[rt], s);
2605 GPR[rd] = EXTEND32 (temp);
2606 TRACE_ALU_RESULT (GPR[rd]);
2609 000000,5.RS,5.RT,5.RD,00000,000110:SPECIAL:32::SRLV
2610 "srlv r<RD>, r<RT>, r<RS>"
2620 do_srlv (SD_, RS, RT, RD);
2624 000000,5.RS,5.RT,5.RD,00000,100010:SPECIAL:32::SUB
2625 "sub r<RD>, r<RS>, r<RT>"
2635 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2637 ALU32_BEGIN (GPR[RS]);
2638 ALU32_SUB (GPR[RT]);
2639 ALU32_END (GPR[RD]); /* This checks for overflow. */
2641 TRACE_ALU_RESULT (GPR[RD]);
2645 :function:::void:do_subu:int rs, int rt, int rd
2647 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2648 GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
2649 TRACE_ALU_RESULT (GPR[rd]);
2652 000000,5.RS,5.RT,5.RD,00000,100011:SPECIAL:32::SUBU
2653 "subu r<RD>, r<RS>, r<RT>"
2663 do_subu (SD_, RS, RT, RD);
2667 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
2668 "sw r<RT>, <OFFSET>(r<BASE>)"
2678 do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2682 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
2683 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2693 do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
2697 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
2698 "swl r<RT>, <OFFSET>(r<BASE>)"
2708 do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2712 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
2713 "swr r<RT>, <OFFSET>(r<BASE>)"
2723 do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2727 000000,000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
2738 SyncOperation (STYPE);
2742 000000,20.CODE,001100:SPECIAL:32::SYSCALL
2753 SignalException(SystemCall, instruction_0);
2757 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
2766 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
2767 SignalException(Trap, instruction_0);
2771 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
2772 "teqi r<RS>, <IMMEDIATE>"
2780 if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
2781 SignalException(Trap, instruction_0);
2785 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
2794 if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
2795 SignalException(Trap, instruction_0);
2799 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
2800 "tgei r<RS>, <IMMEDIATE>"
2808 if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
2809 SignalException(Trap, instruction_0);
2813 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
2814 "tgeiu r<RS>, <IMMEDIATE>"
2822 if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
2823 SignalException(Trap, instruction_0);
2827 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
2836 if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
2837 SignalException(Trap, instruction_0);
2841 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
2850 if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
2851 SignalException(Trap, instruction_0);
2855 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
2856 "tlti r<RS>, <IMMEDIATE>"
2864 if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
2865 SignalException(Trap, instruction_0);
2869 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
2870 "tltiu r<RS>, <IMMEDIATE>"
2878 if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
2879 SignalException(Trap, instruction_0);
2883 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
2892 if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
2893 SignalException(Trap, instruction_0);
2897 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
2906 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
2907 SignalException(Trap, instruction_0);
2911 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
2912 "tne r<RS>, <IMMEDIATE>"
2920 if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
2921 SignalException(Trap, instruction_0);
2925 :function:::void:do_xor:int rs, int rt, int rd
2927 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2928 GPR[rd] = GPR[rs] ^ GPR[rt];
2929 TRACE_ALU_RESULT (GPR[rd]);
2932 000000,5.RS,5.RT,5.RD,00000,100110:SPECIAL:32::XOR
2933 "xor r<RD>, r<RS>, r<RT>"
2943 do_xor (SD_, RS, RT, RD);
2947 :function:::void:do_xori:int rs, int rt, unsigned16 immediate
2949 TRACE_ALU_INPUT2 (GPR[rs], immediate);
2950 GPR[rt] = GPR[rs] ^ immediate;
2951 TRACE_ALU_RESULT (GPR[rt]);
2954 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
2955 "xori r<RT>, r<RS>, <IMMEDIATE>"
2965 do_xori (SD_, RS, RT, IMMEDIATE);
2970 // MIPS Architecture:
2972 // FPU Instruction Set (COP1 & COP1X)
2980 case fmt_single: return "s";
2981 case fmt_double: return "d";
2982 case fmt_word: return "w";
2983 case fmt_long: return "l";
2984 default: return "?";
2994 default: return "?";
3014 :%s::::COND:int cond
3018 case 00: return "f";
3019 case 01: return "un";
3020 case 02: return "eq";
3021 case 03: return "ueq";
3022 case 04: return "olt";
3023 case 05: return "ult";
3024 case 06: return "ole";
3025 case 07: return "ule";
3026 case 010: return "sf";
3027 case 011: return "ngle";
3028 case 012: return "seq";
3029 case 013: return "ngl";
3030 case 014: return "lt";
3031 case 015: return "nge";
3032 case 016: return "le";
3033 case 017: return "ngt";
3034 default: return "?";
3040 // Check that the FPU is currently usable, and signal a CoProcessorUnusable
3041 // exception if not.
3044 :function:::void:check_fpu:
3054 #if 0 /* XXX FIXME: For now, never treat the FPU as disabled. */
3055 if (! COP_Usable (1))
3056 SignalExceptionCoProcessorUnusable (1);
3061 010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
3062 "abs.%s<FMT> f<FD>, f<FS>"
3075 if ((fmt != fmt_single) && (fmt != fmt_double))
3076 SignalException(ReservedInstruction,instruction_0);
3078 StoreFPR(FD,fmt,AbsoluteValue(ValueFPR(FS,fmt),fmt));
3084 010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
3085 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
3098 if ((fmt != fmt_single) && (fmt != fmt_double))
3099 SignalException(ReservedInstruction, instruction_0);
3101 StoreFPR(FD,fmt,Add(ValueFPR(FS,fmt),ValueFPR(FT,fmt),fmt));
3112 010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a
3113 "bc1%s<TF>%s<ND> <OFFSET>"
3119 check_branch_bug ();
3120 TRACE_BRANCH_INPUT (PREVCOC1());
3121 if (PREVCOC1() == TF)
3123 address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
3124 TRACE_BRANCH_RESULT (dest);
3125 mark_branch_bug (dest);
3130 TRACE_BRANCH_RESULT (0);
3131 NULLIFY_NEXT_INSTRUCTION ();
3135 TRACE_BRANCH_RESULT (NIA);
3139 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1b
3140 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
3141 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
3149 check_branch_bug ();
3150 if (GETFCC(CC) == TF)
3152 address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
3153 mark_branch_bug (dest);
3158 NULLIFY_NEXT_INSTRUCTION ();
3171 :function:::void:do_c_cond_fmt:int fmt, int ft, int fs, int cc, int cond, instruction_word insn
3173 if ((fmt != fmt_single) && (fmt != fmt_double))
3174 SignalException (ReservedInstruction, insn);
3181 unsigned64 ofs = ValueFPR (fs, fmt);
3182 unsigned64 oft = ValueFPR (ft, fmt);
3183 if (NaN (ofs, fmt) || NaN (oft, fmt))
3185 if (FCSR & FP_ENABLE (IO))
3187 FCSR |= FP_CAUSE (IO);
3188 SignalExceptionFPE ();
3196 less = Less (ofs, oft, fmt);
3197 equal = Equal (ofs, oft, fmt);
3200 condition = (((cond & (1 << 2)) && less)
3201 || ((cond & (1 << 1)) && equal)
3202 || ((cond & (1 << 0)) && unordered));
3203 SETFCC (cc, condition);
3207 010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32,f::C.cond.fmta
3208 "c.%s<COND>.%s<FMT> f<FS>, f<FT>"
3214 do_c_cond_fmt (SD_, FMT, FT, FS, 0, COND, instruction_0);
3217 010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32,f::C.cond.fmtb
3218 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
3219 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
3227 do_c_cond_fmt (SD_, FMT, FT, FS, CC, COND, instruction_0);
3231 010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64,f::CEIL.L.fmt
3232 "ceil.l.%s<FMT> f<FD>, f<FS>"
3243 if ((fmt != fmt_single) && (fmt != fmt_double))
3244 SignalException(ReservedInstruction,instruction_0);
3246 StoreFPR(FD,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(FS,fmt),fmt,fmt_long));
3251 010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32,f::CEIL.W
3263 if ((fmt != fmt_single) && (fmt != fmt_double))
3264 SignalException(ReservedInstruction,instruction_0);
3266 StoreFPR(FD,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(FS,fmt),fmt,fmt_word));
3273 010001,00,X,10,5.RT,5.FS,00000000000:COP1Sa:32,f::CxC1
3274 "c%s<X>c1 r<RT>, f<FS>"
3283 PENDING_FILL(FCR0IDX,VL4_8(GPR[RT]));
3285 PENDING_FILL(FCR31IDX,VL4_8(GPR[RT]));
3287 PENDING_SCHED(FCSR, FCR31 & (1<<23), 1, 23);
3290 { /* control from */
3292 PENDING_FILL(RT, EXTEND32 (FCR0));
3294 PENDING_FILL(RT, EXTEND32 (FCR31));
3298 010001,00,X,10,5.RT,5.FS,00000000000:COP1Sb:32,f::CxC1
3299 "c%s<X>c1 r<RT>, f<FS>"
3310 TRACE_ALU_INPUT1 (GPR[RT]);
3313 FCR0 = VL4_8(GPR[RT]);
3314 TRACE_ALU_RESULT (FCR0);
3318 FCR31 = VL4_8(GPR[RT]);
3319 SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
3320 TRACE_ALU_RESULT (FCR31);
3324 TRACE_ALU_RESULT0 ();
3329 { /* control from */
3332 TRACE_ALU_INPUT1 (FCR0);
3333 GPR[RT] = EXTEND32 (FCR0);
3337 TRACE_ALU_INPUT1 (FCR31);
3338 GPR[RT] = EXTEND32 (FCR31);
3340 TRACE_ALU_RESULT (GPR[RT]);
3347 // FIXME: Does not correctly differentiate between mips*
3349 010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32,f::CVT.D.fmt
3350 "cvt.d.%s<FMT> f<FD>, f<FS>"
3363 if ((fmt == fmt_double) | 0)
3364 SignalException(ReservedInstruction,instruction_0);
3366 StoreFPR(FD,fmt_double,Convert(GETRM(),ValueFPR(FS,fmt),fmt,fmt_double));
3371 010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64,f::CVT.L.fmt
3372 "cvt.l.%s<FMT> f<FD>, f<FS>"
3383 if ((fmt == fmt_long) | ((fmt == fmt_long) || (fmt == fmt_word)))
3384 SignalException(ReservedInstruction,instruction_0);
3386 StoreFPR(FD,fmt_long,Convert(GETRM(),ValueFPR(FS,fmt),fmt,fmt_long));
3392 // FIXME: Does not correctly differentiate between mips*
3394 010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.fmt
3395 "cvt.s.%s<FMT> f<FD>, f<FS>"
3408 if ((fmt == fmt_single) | 0)
3409 SignalException(ReservedInstruction,instruction_0);
3411 StoreFPR(FD,fmt_single,Convert(GETRM(),ValueFPR(FS,fmt),fmt,fmt_single));
3416 010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32,f::CVT.W.fmt
3417 "cvt.w.%s<FMT> f<FD>, f<FS>"
3430 if ((fmt == fmt_word) | ((fmt == fmt_long) || (fmt == fmt_word)))
3431 SignalException(ReservedInstruction,instruction_0);
3433 StoreFPR(FD,fmt_word,Convert(GETRM(),ValueFPR(FS,fmt),fmt,fmt_word));
3438 010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32,f::DIV.fmt
3439 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
3452 if ((fmt != fmt_single) && (fmt != fmt_double))
3453 SignalException(ReservedInstruction,instruction_0);
3455 StoreFPR(FD,fmt,Divide(ValueFPR(FS,fmt),ValueFPR(FT,fmt),fmt));
3462 010001,00,X,01,5.RT,5.FS,00000000000:COP1Sa:64,f::DMxC1
3463 "dm%s<X>c1 r<RT>, f<FS>"
3467 check_u64 (SD_, instruction_0);
3470 if (SizeFGR() == 64)
3471 PENDING_FILL((FS + FGRIDX),GPR[RT]);
3472 else if ((FS & 0x1) == 0)
3474 PENDING_FILL(((FS + 1) + FGRIDX),VH4_8(GPR[RT]));
3475 PENDING_FILL((FS + FGRIDX),VL4_8(GPR[RT]));
3480 if (SizeFGR() == 64)
3481 PENDING_FILL(RT,FGR[FS]);
3482 else if ((FS & 0x1) == 0)
3483 PENDING_FILL(RT,(SET64HI(FGR[FS+1]) | FGR[FS]));
3486 if (STATE_VERBOSE_P(SD))
3488 "Warning: PC 0x%lx: semantic_DMxC1_COP1Sa 32-bit use of odd FPR number\n",
3490 PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
3494 010001,00,X,01,5.RT,5.FS,00000000000:COP1Sb:64,f::DMxC1
3495 "dm%s<X>c1 r<RT>, f<FS>"
3503 check_u64 (SD_, instruction_0);
3506 if (SizeFGR() == 64)
3507 StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
3508 else if ((FS & 0x1) == 0)
3509 StoreFPR (FS, fmt_uninterpreted_64, SET64HI (FGR[FS+1]) | FGR[FS]);
3513 if (SizeFGR() == 64)
3515 else if ((FS & 0x1) == 0)
3516 GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
3519 if (STATE_VERBOSE_P(SD))
3521 "Warning: PC 0x%lx: DMxC1 32-bit use of odd FPR number\n",
3523 GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
3529 010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64,f::FLOOR.L.fmt
3530 "floor.l.%s<FMT> f<FD>, f<FS>"
3541 if ((fmt != fmt_single) && (fmt != fmt_double))
3542 SignalException(ReservedInstruction,instruction_0);
3544 StoreFPR(FS,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(FS,fmt),fmt,fmt_long));
3549 010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32,f::FLOOR.W.fmt
3550 "floor.w.%s<FMT> f<FD>, f<FS>"
3562 if ((fmt != fmt_single) && (fmt != fmt_double))
3563 SignalException(ReservedInstruction,instruction_0);
3565 StoreFPR(FD,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(FS,fmt),fmt,fmt_word));
3570 110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1
3571 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
3581 COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
3585 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64,f::LDXC1
3586 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
3592 check_u64 (SD_, instruction_0);
3593 COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
3598 110001,5.BASE,5.FT,16.OFFSET:COP1:32,f::LWC1
3599 "lwc1 f<FT>, <OFFSET>(r<BASE>)"
3610 COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
3614 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:64,f::LWXC1
3615 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
3621 check_u64 (SD_, instruction_0);
3622 COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
3628 // FIXME: Not correct for mips*
3630 010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32,f::MADD.D
3631 "madd.d f<FD>, f<FR>, f<FS>, f<FT>"
3638 StoreFPR(FD,fmt_double,Add(Multiply(ValueFPR(FS,fmt_double),ValueFPR(FT,fmt_double),fmt_double),ValueFPR(FR,fmt_double),fmt_double));
3643 010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32,f::MADD.S
3644 "madd.s f<FD>, f<FR>, f<FS>, f<FT>"
3651 StoreFPR(FD,fmt_single,Add(Multiply(ValueFPR(FS,fmt_single),ValueFPR(FT,fmt_single),fmt_single),ValueFPR(FR,fmt_single),fmt_single));
3658 010001,00,X,00,5.RT,5.FS,00000000000:COP1Sa:32,f::MxC1
3659 "m%s<X>c1 r<RT>, f<FS>"
3667 if (SizeFGR() == 64)
3669 if (STATE_VERBOSE_P(SD))
3671 "Warning: PC 0x%lx: MTC1 not DMTC1 with 64 bit regs\n",
3673 PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT])));
3676 PENDING_FILL ((FS + FGRIDX), VL4_8(GPR[RT]));
3679 PENDING_FILL (RT, EXTEND32 (FGR[FS]));
3681 010001,00,X,00,5.RT,5.FS,00000000000:COP1Sb:32,f::MxC1
3682 "m%s<X>c1 r<RT>, f<FS>"
3693 StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
3695 GPR[RT] = EXTEND32 (FGR[FS]);
3699 010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32,f::MOV.fmt
3700 "mov.%s<FMT> f<FD>, f<FS>"
3712 StoreFPR(FD,fmt,ValueFPR(FS,fmt));
3718 000000,5.RS,3.CC,0,1.TF,5.RD,00000,000001:SPECIAL:32,f::MOVtf
3719 "mov%s<TF> r<RD>, r<RS>, <CC>"
3725 if (GETFCC(CC) == TF)
3732 010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32,f::MOVtf.fmt
3733 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
3741 if (GETFCC(CC) == TF)
3742 StoreFPR (FD, fmt, ValueFPR (FS, fmt));
3744 StoreFPR (FD, fmt, ValueFPR (FD, fmt));
3749 010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32,f::MOVN.fmt
3750 "movn.%s<FMT> f<FD>, f<FS>, r<RT>"
3757 StoreFPR (FD, FMT, ValueFPR (FS, FMT));
3759 StoreFPR (FD, FMT, ValueFPR (FD, FMT));
3766 // MOVT.fmt see MOVtf.fmt
3770 010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32,f::MOVZ.fmt
3771 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
3778 StoreFPR (FD, FMT, ValueFPR (FS, FMT));
3780 StoreFPR (FD, FMT, ValueFPR (FD, FMT));
3785 010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32,f::MSUB.D
3786 "msub.d f<FD>, f<FR>, f<FS>, f<FT>"
3792 StoreFPR(FD,fmt_double,Sub(Multiply(ValueFPR(FS,fmt_double),ValueFPR(FT,fmt_double),fmt_double),ValueFPR(FR,fmt_double),fmt_double));
3797 010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32,f::MSUB.S
3798 "msub.s f<FD>, f<FR>, f<FS>, f<FT>"
3804 StoreFPR(FD,fmt_single,Sub(Multiply(ValueFPR(FS,fmt_single),ValueFPR(FT,fmt_single),fmt_single),ValueFPR(FR,fmt_single),fmt_single));
3811 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32,f::MUL.fmt
3812 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
3825 if ((fmt != fmt_single) && (fmt != fmt_double))
3826 SignalException(ReservedInstruction,instruction_0);
3828 StoreFPR(FD,fmt,Multiply(ValueFPR(FS,fmt),ValueFPR(FT,fmt),fmt));
3833 010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32,f::NEG.fmt
3834 "neg.%s<FMT> f<FD>, f<FS>"
3847 if ((fmt != fmt_single) && (fmt != fmt_double))
3848 SignalException(ReservedInstruction,instruction_0);
3850 StoreFPR(FD,fmt,Negate(ValueFPR(FS,fmt),fmt));
3856 010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32,f::NMADD.D
3857 "nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
3863 StoreFPR(FD,fmt_double,Negate(Add(Multiply(ValueFPR(FS,fmt_double),ValueFPR(FT,fmt_double),fmt_double),ValueFPR(FR,fmt_double),fmt_double),fmt_double));
3868 010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32,f::NMADD.S
3869 "nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
3875 StoreFPR(FD,fmt_single,Negate(Add(Multiply(ValueFPR(FS,fmt_single),ValueFPR(FT,fmt_single),fmt_single),ValueFPR(FR,fmt_single),fmt_single),fmt_single));
3880 010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32,f::NMSUB.D
3881 "nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
3887 StoreFPR(FD,fmt_double,Negate(Sub(Multiply(ValueFPR(FS,fmt_double),ValueFPR(FT,fmt_double),fmt_double),ValueFPR(FR,fmt_double),fmt_double),fmt_double));
3892 010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32,f::NMSUB.S
3893 "nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
3899 StoreFPR(FD,fmt_single,Negate(Sub(Multiply(ValueFPR(FS,fmt_single),ValueFPR(FT,fmt_single),fmt_single),ValueFPR(FR,fmt_single),fmt_single),fmt_single));
3903 010011,5.BASE,5.INDEX,5.HINT,00000,001111:COP1X:64::PREFX
3904 "prefx <HINT>, r<INDEX>(r<BASE>)"
3909 address_word base = GPR[BASE];
3910 address_word index = GPR[INDEX];
3912 address_word vaddr = loadstore_ea (SD_, base, index);
3915 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
3916 Prefetch(uncached,paddr,vaddr,isDATA,HINT);
3920 010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32,f::RECIP.fmt
3921 "recip.%s<FMT> f<FD>, f<FS>"
3929 if ((fmt != fmt_single) && (fmt != fmt_double))
3930 SignalException(ReservedInstruction,instruction_0);
3932 StoreFPR(FD,fmt,Recip(ValueFPR(FS,fmt),fmt));
3937 010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64,f::ROUND.L.fmt
3938 "round.l.%s<FMT> f<FD>, f<FS>"
3949 if ((fmt != fmt_single) && (fmt != fmt_double))
3950 SignalException(ReservedInstruction,instruction_0);
3952 StoreFPR(FD,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(FS,fmt),fmt,fmt_long));
3957 010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32,f::ROUND.W.fmt
3958 "round.w.%s<FMT> f<FD>, f<FS>"
3970 if ((fmt != fmt_single) && (fmt != fmt_double))
3971 SignalException(ReservedInstruction,instruction_0);
3973 StoreFPR(FD,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(FS,fmt),fmt,fmt_word));
3978 010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32,f::RSQRT.fmt
3981 "rsqrt.%s<FMT> f<FD>, f<FS>"
3987 if ((fmt != fmt_single) && (fmt != fmt_double))
3988 SignalException(ReservedInstruction,instruction_0);
3990 StoreFPR(FD,fmt,Recip(SquareRoot(ValueFPR(FS,fmt),fmt),fmt));
3995 111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1
3996 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
4006 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
4010 010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64,f::SDXC1
4011 "sdxc1 f<FS>, r<INDEX>(r<BASE>)"
4017 check_u64 (SD_, instruction_0);
4018 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
4022 010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32,f::SQRT.fmt
4023 "sqrt.%s<FMT> f<FD>, f<FS>"
4035 if ((fmt != fmt_single) && (fmt != fmt_double))
4036 SignalException(ReservedInstruction,instruction_0);
4038 StoreFPR(FD,fmt,(SquareRoot(ValueFPR(FS,fmt),fmt)));
4043 010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32,f::SUB.fmt
4044 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
4057 if ((fmt != fmt_single) && (fmt != fmt_double))
4058 SignalException(ReservedInstruction,instruction_0);
4060 StoreFPR(FD,fmt,Sub(ValueFPR(FS,fmt),ValueFPR(FT,fmt),fmt));
4066 111001,5.BASE,5.FT,16.OFFSET:COP1:32,f::SWC1
4067 "swc1 f<FT>, <OFFSET>(r<BASE>)"
4077 address_word base = GPR[BASE];
4078 address_word offset = EXTEND16 (OFFSET);
4081 address_word vaddr = loadstore_ea (SD_, base, offset);
4084 if ((vaddr & 3) != 0)
4086 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr, write_transfer, sim_core_unaligned_signal);
4090 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4093 uword64 memval1 = 0;
4094 uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
4095 address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0);
4096 address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
4098 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
4099 byte = ((vaddr & mask) ^ bigendiancpu);
4100 memval = (((uword64)COP_SW(((instruction_0 >> 26) & 0x3),FT)) << (8 * byte));
4101 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
4108 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32,f::SWXC1
4109 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
4115 address_word base = GPR[BASE];
4116 address_word index = GPR[INDEX];
4118 check_u64 (SD_, instruction_0);
4120 address_word vaddr = loadstore_ea (SD_, base, index);
4123 if ((vaddr & 3) != 0)
4125 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
4129 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4131 unsigned64 memval = 0;
4132 unsigned64 memval1 = 0;
4133 unsigned64 mask = 0x7;
4135 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
4136 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
4137 memval = (((unsigned64)COP_SW(1,FS)) << (8 * byte));
4139 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
4147 010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64,f::TRUNC.L.fmt
4148 "trunc.l.%s<FMT> f<FD>, f<FS>"
4159 if ((fmt != fmt_single) && (fmt != fmt_double))
4160 SignalException(ReservedInstruction,instruction_0);
4162 StoreFPR(FD,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(FS,fmt),fmt,fmt_long));
4167 010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32,f::TRUNC.W
4168 "trunc.w.%s<FMT> f<FD>, f<FS>"
4180 if ((fmt != fmt_single) && (fmt != fmt_double))
4181 SignalException(ReservedInstruction,instruction_0);
4183 StoreFPR(FD,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(FS,fmt),fmt,fmt_word));
4189 // MIPS Architecture:
4191 // System Control Instruction Set (COP0)
4195 010000,01000,00000,16.OFFSET:COP0:32::BC0F
4205 010000,01000,00000,16.OFFSET:COP0:32::BC0F
4207 // stub needed for eCos as tx39 hardware bug workaround
4214 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
4225 010000,01000,00001,16.OFFSET:COP0:32::BC0T
4235 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
4246 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
4247 "cache <OP>, <OFFSET>(r<BASE>)"
4255 address_word base = GPR[BASE];
4256 address_word offset = EXTEND16 (OFFSET);
4258 address_word vaddr = loadstore_ea (SD_, base, offset);
4261 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4262 CacheOp(OP,vaddr,paddr,instruction_0);
4267 010000,1,0000000000000000000,111001:COP0:32::DI
4278 010000,00001,5.RT,5.RD,00000000000:COP0:64::DMFC0
4279 "dmfc0 r<RT>, r<RD>"
4284 check_u64 (SD_, instruction_0);
4285 DecodeCoproc (instruction_0);
4289 010000,00101,5.RT,5.RD,00000000000:COP0:64::DMTC0
4290 "dmtc0 r<RT>, r<RD>"
4295 check_u64 (SD_, instruction_0);
4296 DecodeCoproc (instruction_0);
4300 010000,1,0000000000000000000,111000:COP0:32::EI
4311 010000,1,0000000000000000000,011000:COP0:32::ERET
4319 if (SR & status_ERL)
4321 /* Oops, not yet available */
4322 sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
4334 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
4335 "mfc0 r<RT>, r<RD> # <REGX>"
4345 TRACE_ALU_INPUT0 ();
4346 DecodeCoproc (instruction_0);
4347 TRACE_ALU_RESULT (GPR[RT]);
4350 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
4351 "mtc0 r<RT>, r<RD> # <REGX>"
4361 DecodeCoproc (instruction_0);
4365 010000,1,0000000000000000000,010000:COP0:32::RFE
4376 DecodeCoproc (instruction_0);
4380 0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
4381 "cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
4390 DecodeCoproc (instruction_0);
4395 010000,1,0000000000000000000,001000:COP0:32::TLBP
4406 010000,1,0000000000000000000,000001:COP0:32::TLBR
4417 010000,1,0000000000000000000,000010:COP0:32::TLBWI
4428 010000,1,0000000000000000000,000110:COP0:32::TLBWR