sim/mips/sim-main.h

   1 /* MIPS Simulator definition.
   2    Copyright (C) 1997-2015 Free Software Foundation, Inc.
   3    Contributed by Cygnus Support.
   4
   5 This file is part of GDB, the GNU debugger.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 3 of the License, or
  10 (at your option) any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License
  18 along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  19
  20 #ifndef SIM_MAIN_H
  21 #define SIM_MAIN_H
  22
  23 /* This simulator doesn't cache the Current Instruction Address */
  24 /* #define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA) */
  25 /* #define SIM_ENGINE_RESUME_HOOK(SD, LAST_CPU, CIA) */
  26
  27 /* hobble some common features for moment */
  28 #define WITH_WATCHPOINTS 1
  29 #define WITH_MODULO_MEMORY 1
  30
  31
  32 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
  33 mips_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR))
  34
  35 #include "sim-basics.h"
  36
  37 typedef address_word sim_cia;
  38
  39 #include "sim-base.h"
  40 #include "bfd.h"
  41
  42 /* Deprecated macros and types for manipulating 64bit values.  Use
  43    ../common/sim-bits.h and ../common/sim-endian.h macros instead. */
  44
  45 typedef signed64 word64;
  46 typedef unsigned64 uword64;
  47
  48 #define WORD64LO(t)     (unsigned int)((t)&0xFFFFFFFF)
  49 #define WORD64HI(t)     (unsigned int)(((uword64)(t))>>32)
  50 #define SET64LO(t)      (((uword64)(t))&0xFFFFFFFF)
  51 #define SET64HI(t)      (((uword64)(t))<<32)
  52 #define WORD64(h,l)     ((word64)((SET64HI(h)|SET64LO(l))))
  53 #define UWORD64(h,l)     (SET64HI(h)|SET64LO(l))
  54
  55 /* Check if a value will fit within a halfword: */
  56 #define NOTHALFWORDVALUE(v) ((((((uword64)(v)>>16) == 0) && !((v) & ((unsigned)1 << 15))) || (((((uword64)(v)>>32) == 0xFFFFFFFF) && ((((uword64)(v)>>16) & 0xFFFF) == 0xFFFF)) && ((v) & ((unsigned)1 << 15)))) ? (1 == 0) : (1 == 1))
  57
  58
  59
  60 /* Floating-point operations: */
  61
  62 #include "sim-fpu.h"
  63 #include "cp1.h"
  64
  65 /* FPU registers must be one of the following types. All other values
  66    are reserved (and undefined). */
  67 typedef enum {
  68  fmt_single  = 0,
  69  fmt_double  = 1,
  70  fmt_word    = 4,
  71  fmt_long    = 5,
  72  fmt_ps      = 6,
  73  /* The following are well outside the normal acceptable format
  74     range, and are used in the register status vector. */
  75  fmt_unknown       = 0x10000000,
  76  fmt_uninterpreted = 0x20000000,
  77  fmt_uninterpreted_32 = 0x40000000,
  78  fmt_uninterpreted_64 = 0x80000000U,
  79 } FP_formats;
  80
  81 /* For paired word (pw) operations, the opcode representation is fmt_word,
  82    but register transfers (StoreFPR, ValueFPR, etc.) are done as fmt_long.  */
  83 #define fmt_pw fmt_long
  84
  85 /* This should be the COC1 value at the start of the preceding
  86    instruction: */
  87 #define PREVCOC1() ((STATE & simPCOC1) ? 1 : 0)
  88
  89 #ifdef TARGET_ENABLE_FR
  90 /* FIXME: this should be enabled for all targets, but needs testing first. */
  91 #define SizeFGR() (((WITH_TARGET_FLOATING_POINT_BITSIZE) == 64) \
  92    ? ((SR & status_FR) ? 64 : 32) \
  93    : (WITH_TARGET_FLOATING_POINT_BITSIZE))
  94 #else
  95 #define SizeFGR() (WITH_TARGET_FLOATING_POINT_BITSIZE)
  96 #endif
  97
  98
  99
 100
 101
 102 /* HI/LO register accesses */
 103
 104 /* For some MIPS targets, the HI/LO registers have certain timing
 105    restrictions in that, for instance, a read of a HI register must be
 106    separated by at least three instructions from a preceeding read.
 107
 108    The struct below is used to record the last access by each of A MT,
 109    MF or other OP instruction to a HI/LO register.  See mips.igen for
 110    more details. */
 111
 112 typedef struct _hilo_access {
 113   signed64 timestamp;
 114   address_word cia;
 115 } hilo_access;
 116
 117 typedef struct _hilo_history {
 118   hilo_access mt;
 119   hilo_access mf;
 120   hilo_access op;
 121 } hilo_history;
 122
 123
 124
 125
 126 /* Integer ALU operations: */
 127
 128 #include "sim-alu.h"
 129
 130 #define ALU32_END(ANS) \
 131   if (ALU32_HAD_OVERFLOW) \
 132     SignalExceptionIntegerOverflow (); \
 133   (ANS) = (signed32) ALU32_OVERFLOW_RESULT
 134
 135
 136 #define ALU64_END(ANS) \
 137   if (ALU64_HAD_OVERFLOW) \
 138     SignalExceptionIntegerOverflow (); \
 139   (ANS) = ALU64_OVERFLOW_RESULT;
 140
 141
 142
 143
 144
 145 /* The following is probably not used for MIPS IV onwards: */
 146 /* Slots for delayed register updates. For the moment we just have a
 147    fixed number of slots (rather than a more generic, dynamic
 148    system). This keeps the simulator fast. However, we only allow
 149    for the register update to be delayed for a single instruction
 150    cycle. */
 151 #define PSLOTS (8) /* Maximum number of instruction cycles */
 152
 153 typedef struct _pending_write_queue {
 154   int in;
 155   int out;
 156   int total;
 157   int slot_delay[PSLOTS];
 158   int slot_size[PSLOTS];
 159   int slot_bit[PSLOTS];
 160   void *slot_dest[PSLOTS];
 161   unsigned64 slot_value[PSLOTS];
 162 } pending_write_queue;
 163
 164 #ifndef PENDING_TRACE
 165 #define PENDING_TRACE 0
 166 #endif
 167 #define PENDING_IN ((CPU)->pending.in)
 168 #define PENDING_OUT ((CPU)->pending.out)
 169 #define PENDING_TOTAL ((CPU)->pending.total)
 170 #define PENDING_SLOT_SIZE ((CPU)->pending.slot_size)
 171 #define PENDING_SLOT_BIT ((CPU)->pending.slot_bit)
 172 #define PENDING_SLOT_DELAY ((CPU)->pending.slot_delay)
 173 #define PENDING_SLOT_DEST ((CPU)->pending.slot_dest)
 174 #define PENDING_SLOT_VALUE ((CPU)->pending.slot_value)
 175
 176 /* Invalidate the pending write queue, all pending writes are
 177    discarded. */
 178
 179 #define PENDING_INVALIDATE() \
 180 memset (&(CPU)->pending, 0, sizeof ((CPU)->pending))
 181
 182 /* Schedule a write to DEST for N cycles time.  For 64 bit
 183    destinations, schedule two writes.  For floating point registers,
 184    the caller should schedule a write to both the dest register and
 185    the FPR_STATE register.  When BIT is non-negative, only BIT of DEST
 186    is updated. */
 187
 188 #define PENDING_SCHED(DEST,VAL,DELAY,BIT)                               \
 189   do {                                                                  \
 190     if (PENDING_SLOT_DEST[PENDING_IN] != NULL)                          \
 191       sim_engine_abort (SD, CPU, cia,                                   \
 192                         "PENDING_SCHED - buffer overflow\n");           \
 193     if (PENDING_TRACE)                                                  \
 194       sim_io_eprintf (SD, "PENDING_SCHED - 0x%lx - dest 0x%lx, val 0x%lx, bit %d, size %d, pending_in %d, pending_out %d, pending_total %d\n",                  \
 195                       (unsigned long) cia, (unsigned long) &(DEST),     \
 196                       (unsigned long) (VAL), (BIT), (int) sizeof (DEST),\
 197                       PENDING_IN, PENDING_OUT, PENDING_TOTAL);          \
 198     PENDING_SLOT_DELAY[PENDING_IN] = (DELAY) + 1;                       \
 199     PENDING_SLOT_DEST[PENDING_IN] = &(DEST);                            \
 200     PENDING_SLOT_VALUE[PENDING_IN] = (VAL);                             \
 201     PENDING_SLOT_SIZE[PENDING_IN] = sizeof (DEST);                      \
 202     PENDING_SLOT_BIT[PENDING_IN] = (BIT);                               \
 203     PENDING_IN = (PENDING_IN + 1) % PSLOTS;                             \
 204     PENDING_TOTAL += 1;                                                 \
 205   } while (0)
 206
 207 #define PENDING_WRITE(DEST,VAL,DELAY) PENDING_SCHED(DEST,VAL,DELAY,-1)
 208 #define PENDING_BIT(DEST,VAL,DELAY,BIT) PENDING_SCHED(DEST,VAL,DELAY,BIT)
 209
 210 #define PENDING_TICK() pending_tick (SD, CPU, cia)
 211
 212 #define PENDING_FLUSH() abort () /* think about this one */
 213 #define PENDING_FP() abort () /* think about this one */
 214
 215 /* For backward compatibility */
 216 #define PENDING_FILL(R,VAL)                                             \
 217 do {                                                                    \
 218   if ((R) >= FGR_BASE && (R) < FGR_BASE + NR_FGR)                       \
 219     {                                                                   \
 220       PENDING_SCHED(FGR[(R) - FGR_BASE], VAL, 1, -1);                   \
 221       PENDING_SCHED(FPR_STATE[(R) - FGR_BASE], fmt_uninterpreted, 1, -1); \
 222     }                                                                   \
 223   else                                                                  \
 224     PENDING_SCHED(GPR[(R)], VAL, 1, -1);                                \
 225 } while (0)
 226
 227
 228 enum float_operation
 229   {
 230     FLOP_ADD,    FLOP_SUB,    FLOP_MUL,    FLOP_MADD,
 231     FLOP_MSUB,   FLOP_MAX=10, FLOP_MIN,    FLOP_ABS,
 232     FLOP_ITOF0=14, FLOP_FTOI0=18, FLOP_NEG=23
 233   };
 234
 235
 236 /* The internal representation of an MDMX accumulator.
 237    Note that 24 and 48 bit accumulator elements are represented in
 238    32 or 64 bits.  Since the accumulators are 2's complement with
 239    overflow suppressed, high-order bits can be ignored in most contexts.  */
 240
 241 typedef signed32 signed24;
 242 typedef signed64 signed48;
 243
 244 typedef union {
 245   signed24  ob[8];
 246   signed48  qh[4];
 247 } MDMX_accumulator;
 248
 249
 250 /* Conventional system arguments.  */
 251 #define SIM_STATE  sim_cpu *cpu, address_word cia
 252 #define SIM_ARGS   CPU, cia
 253
 254 struct _sim_cpu {
 255
 256
 257   /* The following are internal simulator state variables: */
 258 #define CIA_GET(CPU) ((CPU)->registers[PCIDX] + 0)
 259 #define CIA_SET(CPU,CIA) ((CPU)->registers[PCIDX] = (CIA))
 260   address_word dspc;  /* delay-slot PC */
 261 #define DSPC ((CPU)->dspc)
 262
 263 #define DELAY_SLOT(TARGET) NIA = delayslot32 (SD_, (TARGET))
 264 #define NULLIFY_NEXT_INSTRUCTION() NIA = nullify_next_insn32 (SD_)
 265
 266
 267   /* State of the simulator */
 268   unsigned int state;
 269   unsigned int dsstate;
 270 #define STATE ((CPU)->state)
 271 #define DSSTATE ((CPU)->dsstate)
 272
 273 /* Flags in the "state" variable: */
 274 #define simHALTEX       (1 << 2)  /* 0 = run; 1 = halt on exception */
 275 #define simHALTIN       (1 << 3)  /* 0 = run; 1 = halt on interrupt */
 276 #define simTRACE        (1 << 8)  /* 0 = do nothing; 1 = trace address activity */
 277 #define simPCOC0        (1 << 17) /* COC[1] from current */
 278 #define simPCOC1        (1 << 18) /* COC[1] from previous */
 279 #define simDELAYSLOT    (1 << 24) /* 0 = do nothing; 1 = delay slot entry exists */
 280 #define simSKIPNEXT     (1 << 25) /* 0 = do nothing; 1 = skip instruction */
 281 #define simSIGINT       (1 << 28)  /* 0 = do nothing; 1 = SIGINT has occured */
 282 #define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */
 283
 284 #ifndef ENGINE_ISSUE_PREFIX_HOOK
 285 #define ENGINE_ISSUE_PREFIX_HOOK() \
 286   { \
 287     /* Perform any pending writes */ \
 288     PENDING_TICK(); \
 289     /* Set previous flag, depending on current: */ \
 290     if (STATE & simPCOC0) \
 291      STATE |= simPCOC1; \
 292     else \
 293      STATE &= ~simPCOC1; \
 294     /* and update the current value: */ \
 295     if (GETFCC(0)) \
 296      STATE |= simPCOC0; \
 297     else \
 298      STATE &= ~simPCOC0; \
 299   }
 300 #endif /* ENGINE_ISSUE_PREFIX_HOOK */
 301
 302
 303 /* This is nasty, since we have to rely on matching the register
 304    numbers used by GDB. Unfortunately, depending on the MIPS target
 305    GDB uses different register numbers. We cannot just include the
 306    relevant "gdb/tm.h" link, since GDB may not be configured before
 307    the sim world, and also the GDB header file requires too much other
 308    state. */
 309
 310 #ifndef TM_MIPS_H
 311 #define LAST_EMBED_REGNUM (96)
 312 #define NUM_REGS (LAST_EMBED_REGNUM + 1)
 313
 314 #define FP0_REGNUM 38           /* Floating point register 0 (single float) */
 315 #define FCRCS_REGNUM 70         /* FP control/status */
 316 #define FCRIR_REGNUM 71         /* FP implementation/revision */
 317 #endif
 318
 319
 320 /* To keep this default simulator simple, and fast, we use a direct
 321    vector of registers. The internal simulator engine then uses
 322    manifests to access the correct slot. */
 323
 324   unsigned_word registers[LAST_EMBED_REGNUM + 1];
 325
 326   int register_widths[NUM_REGS];
 327 #define REGISTERS       ((CPU)->registers)
 328
 329 #define GPR     (&REGISTERS[0])
 330 #define GPR_SET(N,VAL) (REGISTERS[(N)] = (VAL))
 331
 332 #define LO      (REGISTERS[33])
 333 #define HI      (REGISTERS[34])
 334 #define PCIDX   37
 335 #define PC      (REGISTERS[PCIDX])
 336 #define CAUSE   (REGISTERS[36])
 337 #define SRIDX   (32)
 338 #define SR      (REGISTERS[SRIDX])      /* CPU status register */
 339 #define FCR0IDX  (71)
 340 #define FCR0    (REGISTERS[FCR0IDX])    /* really a 32bit register */
 341 #define FCR31IDX (70)
 342 #define FCR31   (REGISTERS[FCR31IDX])   /* really a 32bit register */
 343 #define FCSR    (FCR31)
 344 #define Debug   (REGISTERS[86])
 345 #define DEPC    (REGISTERS[87])
 346 #define EPC     (REGISTERS[88])
 347 #define ACX     (REGISTERS[89])
 348
 349 #define AC0LOIDX        (33)    /* Must be the same register as LO */
 350 #define AC0HIIDX        (34)    /* Must be the same register as HI */
 351 #define AC1LOIDX        (90)
 352 #define AC1HIIDX        (91)
 353 #define AC2LOIDX        (92)
 354 #define AC2HIIDX        (93)
 355 #define AC3LOIDX        (94)
 356 #define AC3HIIDX        (95)
 357
 358 #define DSPLO(N)        (REGISTERS[DSPLO_REGNUM[N]])
 359 #define DSPHI(N)        (REGISTERS[DSPHI_REGNUM[N]])
 360
 361 #define DSPCRIDX        (96)    /* DSP control register */
 362 #define DSPCR           (REGISTERS[DSPCRIDX])
 363
 364 #define DSPCR_POS_SHIFT         (0)
 365 #define DSPCR_POS_MASK          (0x3f)
 366 #define DSPCR_POS_SMASK         (DSPCR_POS_MASK << DSPCR_POS_SHIFT)
 367
 368 #define DSPCR_SCOUNT_SHIFT      (7)
 369 #define DSPCR_SCOUNT_MASK       (0x3f)
 370 #define DSPCR_SCOUNT_SMASK      (DSPCR_SCOUNT_MASK << DSPCR_SCOUNT_SHIFT)
 371
 372 #define DSPCR_CARRY_SHIFT       (13)
 373 #define DSPCR_CARRY_MASK        (1)
 374 #define DSPCR_CARRY_SMASK       (DSPCR_CARRY_MASK << DSPCR_CARRY_SHIFT)
 375 #define DSPCR_CARRY             (1 << DSPCR_CARRY_SHIFT)
 376
 377 #define DSPCR_EFI_SHIFT         (14)
 378 #define DSPCR_EFI_MASK          (1)
 379 #define DSPCR_EFI_SMASK         (DSPCR_EFI_MASK << DSPCR_EFI_SHIFT)
 380 #define DSPCR_EFI               (1 << DSPCR_EFI_MASK)
 381
 382 #define DSPCR_OUFLAG_SHIFT      (16)
 383 #define DSPCR_OUFLAG_MASK       (0xff)
 384 #define DSPCR_OUFLAG_SMASK      (DSPCR_OUFLAG_MASK << DSPCR_OUFLAG_SHIFT)
 385 #define DSPCR_OUFLAG4           (1 << (DSPCR_OUFLAG_SHIFT + 4))
 386 #define DSPCR_OUFLAG5           (1 << (DSPCR_OUFLAG_SHIFT + 5))
 387 #define DSPCR_OUFLAG6           (1 << (DSPCR_OUFLAG_SHIFT + 6))
 388 #define DSPCR_OUFLAG7           (1 << (DSPCR_OUFLAG_SHIFT + 7))
 389
 390 #define DSPCR_CCOND_SHIFT       (24)
 391 #define DSPCR_CCOND_MASK        (0xf)
 392 #define DSPCR_CCOND_SMASK       (DSPCR_CCOND_MASK << DSPCR_CCOND_SHIFT)
 393
 394   /* All internal state modified by signal_exception() that may need to be
 395      rolled back for passing moment-of-exception image back to gdb. */
 396   unsigned_word exc_trigger_registers[LAST_EMBED_REGNUM + 1];
 397   unsigned_word exc_suspend_registers[LAST_EMBED_REGNUM + 1];
 398   int exc_suspended;
 399
 400 #define SIM_CPU_EXCEPTION_TRIGGER(SD,CPU,CIA) mips_cpu_exception_trigger(SD,CPU,CIA)
 401 #define SIM_CPU_EXCEPTION_SUSPEND(SD,CPU,EXC) mips_cpu_exception_suspend(SD,CPU,EXC)
 402 #define SIM_CPU_EXCEPTION_RESUME(SD,CPU,EXC) mips_cpu_exception_resume(SD,CPU,EXC)
 403
 404   unsigned_word c0_config_reg;
 405 #define C0_CONFIG ((CPU)->c0_config_reg)
 406
 407 /* The following are pseudonyms for standard registers */
 408 #define ZERO    (REGISTERS[0])
 409 #define V0      (REGISTERS[2])
 410 #define A0      (REGISTERS[4])
 411 #define A1      (REGISTERS[5])
 412 #define A2      (REGISTERS[6])
 413 #define A3      (REGISTERS[7])
 414 #define T8IDX   24
 415 #define T8      (REGISTERS[T8IDX])
 416 #define SPIDX   29
 417 #define SP      (REGISTERS[SPIDX])
 418 #define RAIDX   31
 419 #define RA      (REGISTERS[RAIDX])
 420
 421   /* While space is allocated in the main registers arrray for some of
 422      the COP0 registers, that space isn't sufficient.  Unknown COP0
 423      registers overflow into the array below */
 424
 425 #define NR_COP0_GPR     32
 426   unsigned_word cop0_gpr[NR_COP0_GPR];
 427 #define COP0_GPR        ((CPU)->cop0_gpr)
 428 #define COP0_BADVADDR   (COP0_GPR[8])
 429
 430   /* While space is allocated for the floating point registers in the
 431      main registers array, they are stored separatly.  This is because
 432      their size may not necessarily match the size of either the
 433      general-purpose or system specific registers.  */
 434 #define NR_FGR    (32)
 435 #define FGR_BASE  FP0_REGNUM
 436   fp_word fgr[NR_FGR];
 437 #define FGR       ((CPU)->fgr)
 438
 439   /* Keep the current format state for each register: */
 440   FP_formats fpr_state[32];
 441 #define FPR_STATE ((CPU)->fpr_state)
 442
 443   pending_write_queue pending;
 444
 445   /* The MDMX accumulator (used only for MDMX ASE).  */
 446   MDMX_accumulator acc;
 447 #define ACC             ((CPU)->acc)
 448
 449   /* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic
 450      read-write instructions. It is set when a linked load occurs. It
 451      is tested and cleared by the conditional store. It is cleared
 452      (during other CPU operations) when a store to the location would
 453      no longer be atomic. In particular, it is cleared by exception
 454      return instructions. */
 455   int llbit;
 456 #define LLBIT ((CPU)->llbit)
 457
 458
 459 /* The HIHISTORY and LOHISTORY timestamps are used to ensure that
 460    corruptions caused by using the HI or LO register too close to a
 461    following operation is spotted. See mips.igen for more details. */
 462
 463   hilo_history hi_history;
 464 #define HIHISTORY (&(CPU)->hi_history)
 465   hilo_history lo_history;
 466 #define LOHISTORY (&(CPU)->lo_history)
 467
 468
 469   sim_cpu_base base;
 470 };
 471
 472
 473 /* MIPS specific simulator watch config */
 474
 475 void watch_options_install (SIM_DESC sd);
 476
 477 struct swatch {
 478   sim_event *pc;
 479   sim_event *clock;
 480   sim_event *cycles;
 481 };
 482
 483
 484 /* FIXME: At present much of the simulator is still static */
 485 struct sim_state {
 486
 487   struct swatch watch;
 488
 489   sim_cpu cpu[MAX_NR_PROCESSORS];
 490 #if (WITH_SMP)
 491 #define STATE_CPU(sd,n) (&(sd)->cpu[n])
 492 #else
 493 #define STATE_CPU(sd,n) (&(sd)->cpu[0])
 494 #endif
 495
 496
 497   sim_state_base base;
 498 };
 499
 500
 501
 502 /* Status information: */
 503
 504 /* TODO : these should be the bitmasks for these bits within the
 505    status register. At the moment the following are VR4300
 506    bit-positions: */
 507 #define status_KSU_mask  (0x18)         /* mask for KSU bits */
 508 #define status_KSU_shift (3)            /* shift for field */
 509 #define ksu_kernel       (0x0)
 510 #define ksu_supervisor   (0x1)
 511 #define ksu_user         (0x2)
 512 #define ksu_unknown      (0x3)
 513
 514 #define SR_KSU           ((SR & status_KSU_mask) >> status_KSU_shift)
 515
 516 #define status_IE        (1 <<  0)      /* Interrupt enable */
 517 #define status_EIE       (1 << 16)      /* Enable Interrupt Enable */
 518 #define status_EXL       (1 <<  1)      /* Exception level */
 519 #define status_RE        (1 << 25)      /* Reverse Endian in user mode */
 520 #define status_FR        (1 << 26)      /* enables MIPS III additional FP registers */
 521 #define status_SR        (1 << 20)      /* soft reset or NMI */
 522 #define status_BEV       (1 << 22)      /* Location of general exception vectors */
 523 #define status_TS        (1 << 21)      /* TLB shutdown has occurred */
 524 #define status_ERL       (1 <<  2)      /* Error level */
 525 #define status_IM7       (1 << 15)      /* Timer Interrupt Mask */
 526 #define status_RP        (1 << 27)      /* Reduced Power mode */
 527
 528 /* Specializations for TX39 family */
 529 #define status_IEc       (1 << 0)       /* Interrupt enable (current) */
 530 #define status_KUc       (1 << 1)       /* Kernel/User mode */
 531 #define status_IEp       (1 << 2)       /* Interrupt enable (previous) */
 532 #define status_KUp       (1 << 3)       /* Kernel/User mode */
 533 #define status_IEo       (1 << 4)       /* Interrupt enable (old) */
 534 #define status_KUo       (1 << 5)       /* Kernel/User mode */
 535 #define status_IM_mask   (0xff)         /* Interrupt mask */
 536 #define status_IM_shift  (8)
 537 #define status_NMI       (1 << 20)      /* NMI */
 538 #define status_NMI       (1 << 20)      /* NMI */
 539
 540 /* Status bits used by MIPS32/MIPS64.  */
 541 #define status_UX        (1 <<  5)      /* 64-bit user addrs */
 542 #define status_SX        (1 <<  6)      /* 64-bit supervisor addrs */
 543 #define status_KX        (1 <<  7)      /* 64-bit kernel addrs */
 544 #define status_TS        (1 << 21)      /* TLB shutdown has occurred */
 545 #define status_PX        (1 << 23)      /* Enable 64 bit operations */
 546 #define status_MX        (1 << 24)      /* Enable MDMX resources */
 547 #define status_CU0       (1 << 28)      /* Coprocessor 0 usable */
 548 #define status_CU1       (1 << 29)      /* Coprocessor 1 usable */
 549 #define status_CU2       (1 << 30)      /* Coprocessor 2 usable */
 550 #define status_CU3       (1 << 31)      /* Coprocessor 3 usable */
 551 /* Bits reserved for implementations:  */
 552 #define status_SBX       (1 << 16)      /* Enable SiByte SB-1 extensions.  */
 553
 554 #define cause_BD ((unsigned)1 << 31)    /* L1 Exception in branch delay slot */
 555 #define cause_BD2         (1 << 30)     /* L2 Exception in branch delay slot */
 556 #define cause_CE_mask     0x30000000    /* Coprocessor exception */
 557 #define cause_CE_shift    28
 558 #define cause_EXC2_mask   0x00070000
 559 #define cause_EXC2_shift  16
 560 #define cause_IP7         (1 << 15)     /* Interrupt pending */
 561 #define cause_SIOP        (1 << 12)     /* SIO pending */
 562 #define cause_IP3         (1 << 11)     /* Int 0 pending */
 563 #define cause_IP2         (1 << 10)     /* Int 1 pending */
 564
 565 #define cause_EXC_mask  (0x1c)          /* Exception code */
 566 #define cause_EXC_shift (2)
 567
 568 #define cause_SW0       (1 << 8)        /* Software interrupt 0 */
 569 #define cause_SW1       (1 << 9)        /* Software interrupt 1 */
 570 #define cause_IP_mask   (0x3f)          /* Interrupt pending field */
 571 #define cause_IP_shift  (10)
 572
 573 #define cause_set_EXC(x)  CAUSE = (CAUSE & ~cause_EXC_mask)  | ((x << cause_EXC_shift)  & cause_EXC_mask)
 574 #define cause_set_EXC2(x) CAUSE = (CAUSE & ~cause_EXC2_mask) | ((x << cause_EXC2_shift) & cause_EXC2_mask)
 575
 576
 577 /* NOTE: We keep the following status flags as bit values (1 for true,
 578    0 for false). This allows them to be used in binary boolean
 579    operations without worrying about what exactly the non-zero true
 580    value is. */
 581
 582 /* UserMode */
 583 #ifdef SUBTARGET_R3900
 584 #define UserMode        ((SR & status_KUc) ? 1 : 0)
 585 #else
 586 #define UserMode        ((((SR & status_KSU_mask) >> status_KSU_shift) == ksu_user) ? 1 : 0)
 587 #endif /* SUBTARGET_R3900 */
 588
 589 /* BigEndianMem */
 590 /* Hardware configuration. Affects endianness of LoadMemory and
 591    StoreMemory and the endianness of Kernel and Supervisor mode
 592    execution. The value is 0 for little-endian; 1 for big-endian. */
 593 #define BigEndianMem    (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
 594 /*(state & simBE) ? 1 : 0)*/
 595
 596 /* ReverseEndian */
 597 /* This mode is selected if in User mode with the RE bit being set in
 598    SR (Status Register). It reverses the endianness of load and store
 599    instructions. */
 600 #define ReverseEndian   (((SR & status_RE) && UserMode) ? 1 : 0)
 601
 602 /* BigEndianCPU */
 603 /* The endianness for load and store instructions (0=little;1=big). In
 604    User mode this endianness may be switched by setting the state_RE
 605    bit in the SR register. Thus, BigEndianCPU may be computed as
 606    (BigEndianMem EOR ReverseEndian). */
 607 #define BigEndianCPU    (BigEndianMem ^ ReverseEndian) /* Already bits */
 608
 609
 610
 611 /* Exceptions: */
 612
 613 /* NOTE: These numbers depend on the processor architecture being
 614    simulated: */
 615 enum ExceptionCause {
 616   Interrupt               = 0,
 617   TLBModification         = 1,
 618   TLBLoad                 = 2,
 619   TLBStore                = 3,
 620   AddressLoad             = 4,
 621   AddressStore            = 5,
 622   InstructionFetch        = 6,
 623   DataReference           = 7,
 624   SystemCall              = 8,
 625   BreakPoint              = 9,
 626   ReservedInstruction     = 10,
 627   CoProcessorUnusable     = 11,
 628   IntegerOverflow         = 12,    /* Arithmetic overflow (IDT monitor raises SIGFPE) */
 629   Trap                    = 13,
 630   FPE                     = 15,
 631   DebugBreakPoint         = 16,    /* Impl. dep. in MIPS32/MIPS64.  */
 632   MDMX                    = 22,
 633   Watch                   = 23,
 634   MCheck                  = 24,
 635   CacheErr                = 30,
 636   NMIReset                = 31,    /* Reserved in MIPS32/MIPS64.  */
 637
 638
 639 /* The following exception code is actually private to the simulator
 640    world. It is *NOT* a processor feature, and is used to signal
 641    run-time errors in the simulator. */
 642   SimulatorFault          = 0xFFFFFFFF
 643 };
 644
 645 #define TLB_REFILL  (0)
 646 #define TLB_INVALID (1)
 647
 648
 649 /* The following break instructions are reserved for use by the
 650    simulator.  The first is used to halt the simulation.  The second
 651    is used by gdb for break-points.  NOTE: Care must be taken, since
 652    this value may be used in later revisions of the MIPS ISA. */
 653 #define HALT_INSTRUCTION_MASK   (0x03FFFFC0)
 654
 655 #define HALT_INSTRUCTION        (0x03ff000d)
 656 #define HALT_INSTRUCTION2       (0x0000ffcd)
 657
 658
 659 #define BREAKPOINT_INSTRUCTION  (0x0005000d)
 660 #define BREAKPOINT_INSTRUCTION2 (0x0000014d)
 661
 662
 663
 664 void interrupt_event (SIM_DESC sd, void *data);
 665
 666 void signal_exception (SIM_DESC sd, sim_cpu *cpu, address_word cia, int exception, ...);
 667 #define SignalException(exc,instruction)     signal_exception (SD, CPU, cia, (exc), (instruction))
 668 #define SignalExceptionInterrupt(level)      signal_exception (SD, CPU, cia, Interrupt, level)
 669 #define SignalExceptionInstructionFetch()    signal_exception (SD, CPU, cia, InstructionFetch)
 670 #define SignalExceptionAddressStore()        signal_exception (SD, CPU, cia, AddressStore)
 671 #define SignalExceptionAddressLoad()         signal_exception (SD, CPU, cia, AddressLoad)
 672 #define SignalExceptionDataReference()       signal_exception (SD, CPU, cia, DataReference)
 673 #define SignalExceptionSimulatorFault(buf)   signal_exception (SD, CPU, cia, SimulatorFault, buf)
 674 #define SignalExceptionFPE()                 signal_exception (SD, CPU, cia, FPE)
 675 #define SignalExceptionIntegerOverflow()     signal_exception (SD, CPU, cia, IntegerOverflow)
 676 #define SignalExceptionCoProcessorUnusable(cop) signal_exception (SD, CPU, cia, CoProcessorUnusable)
 677 #define SignalExceptionNMIReset()            signal_exception (SD, CPU, cia, NMIReset)
 678 #define SignalExceptionTLBRefillStore()      signal_exception (SD, CPU, cia, TLBStore, TLB_REFILL)
 679 #define SignalExceptionTLBRefillLoad()       signal_exception (SD, CPU, cia, TLBLoad, TLB_REFILL)
 680 #define SignalExceptionTLBInvalidStore()     signal_exception (SD, CPU, cia, TLBStore, TLB_INVALID)
 681 #define SignalExceptionTLBInvalidLoad()      signal_exception (SD, CPU, cia, TLBLoad, TLB_INVALID)
 682 #define SignalExceptionTLBModification()     signal_exception (SD, CPU, cia, TLBModification)
 683 #define SignalExceptionMDMX()                signal_exception (SD, CPU, cia, MDMX)
 684 #define SignalExceptionWatch()               signal_exception (SD, CPU, cia, Watch)
 685 #define SignalExceptionMCheck()              signal_exception (SD, CPU, cia, MCheck)
 686 #define SignalExceptionCacheErr()            signal_exception (SD, CPU, cia, CacheErr)
 687
 688 /* Co-processor accesses */
 689
 690 /* XXX FIXME: For now, assume that FPU (cp1) is always usable.  */
 691 #define COP_Usable(coproc_num)          (coproc_num == 1)
 692
 693 void cop_lw  (SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, unsigned int memword);
 694 void cop_ld  (SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, uword64 memword);
 695 unsigned int cop_sw (SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg);
 696 uword64 cop_sd (SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg);
 697
 698 #define COP_LW(coproc_num,coproc_reg,memword) \
 699 cop_lw (SD, CPU, cia, coproc_num, coproc_reg, memword)
 700 #define COP_LD(coproc_num,coproc_reg,memword) \
 701 cop_ld (SD, CPU, cia, coproc_num, coproc_reg, memword)
 702 #define COP_SW(coproc_num,coproc_reg) \
 703 cop_sw (SD, CPU, cia, coproc_num, coproc_reg)
 704 #define COP_SD(coproc_num,coproc_reg) \
 705 cop_sd (SD, CPU, cia, coproc_num, coproc_reg)
 706
 707
 708 void decode_coproc (SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int instruction);
 709 #define DecodeCoproc(instruction) \
 710 decode_coproc (SD, CPU, cia, (instruction))
 711
 712 int sim_monitor (SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int arg);
 713
 714
 715 /* FPR access.  */
 716 unsigned64 value_fpr (SIM_STATE, int fpr, FP_formats);
 717 #define ValueFPR(FPR,FMT) value_fpr (SIM_ARGS, (FPR), (FMT))
 718 void store_fpr (SIM_STATE, int fpr, FP_formats fmt, unsigned64 value);
 719 #define StoreFPR(FPR,FMT,VALUE) store_fpr (SIM_ARGS, (FPR), (FMT), (VALUE))
 720 unsigned64 ps_lower (SIM_STATE, unsigned64 op);
 721 #define PSLower(op) ps_lower (SIM_ARGS, op)
 722 unsigned64 ps_upper (SIM_STATE, unsigned64 op);
 723 #define PSUpper(op) ps_upper (SIM_ARGS, op)
 724 unsigned64 pack_ps (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats from);
 725 #define PackPS(op1,op2) pack_ps (SIM_ARGS, op1, op2, fmt_single)
 726
 727
 728 /* FCR access.  */
 729 unsigned_word value_fcr (SIM_STATE, int fcr);
 730 #define ValueFCR(FCR) value_fcr (SIM_ARGS, (FCR))
 731 void store_fcr (SIM_STATE, int fcr, unsigned_word value);
 732 #define StoreFCR(FCR,VALUE) store_fcr (SIM_ARGS, (FCR), (VALUE))
 733 void test_fcsr (SIM_STATE);
 734 #define TestFCSR() test_fcsr (SIM_ARGS)
 735
 736
 737 /* FPU operations.  */
 738 void fp_cmp (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt, int abs, int cond, int cc);
 739 #define Compare(op1,op2,fmt,cond,cc) fp_cmp(SIM_ARGS, op1, op2, fmt, 0, cond, cc)
 740 unsigned64 fp_abs (SIM_STATE, unsigned64 op, FP_formats fmt);
 741 #define AbsoluteValue(op,fmt) fp_abs(SIM_ARGS, op, fmt)
 742 unsigned64 fp_neg (SIM_STATE, unsigned64 op, FP_formats fmt);
 743 #define Negate(op,fmt) fp_neg(SIM_ARGS, op, fmt)
 744 unsigned64 fp_add (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
 745 #define Add(op1,op2,fmt) fp_add(SIM_ARGS, op1, op2, fmt)
 746 unsigned64 fp_sub (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
 747 #define Sub(op1,op2,fmt) fp_sub(SIM_ARGS, op1, op2, fmt)
 748 unsigned64 fp_mul (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
 749 #define Multiply(op1,op2,fmt) fp_mul(SIM_ARGS, op1, op2, fmt)
 750 unsigned64 fp_div (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
 751 #define Divide(op1,op2,fmt) fp_div(SIM_ARGS, op1, op2, fmt)
 752 unsigned64 fp_recip (SIM_STATE, unsigned64 op, FP_formats fmt);
 753 #define Recip(op,fmt) fp_recip(SIM_ARGS, op, fmt)
 754 unsigned64 fp_sqrt (SIM_STATE, unsigned64 op, FP_formats fmt);
 755 #define SquareRoot(op,fmt) fp_sqrt(SIM_ARGS, op, fmt)
 756 unsigned64 fp_rsqrt (SIM_STATE, unsigned64 op, FP_formats fmt);
 757 #define RSquareRoot(op,fmt) fp_rsqrt(SIM_ARGS, op, fmt)
 758 unsigned64 fp_madd (SIM_STATE, unsigned64 op1, unsigned64 op2,
 759                     unsigned64 op3, FP_formats fmt);
 760 #define MultiplyAdd(op1,op2,op3,fmt) fp_madd(SIM_ARGS, op1, op2, op3, fmt)
 761 unsigned64 fp_msub (SIM_STATE, unsigned64 op1, unsigned64 op2,
 762                     unsigned64 op3, FP_formats fmt);
 763 #define MultiplySub(op1,op2,op3,fmt) fp_msub(SIM_ARGS, op1, op2, op3, fmt)
 764 unsigned64 fp_nmadd (SIM_STATE, unsigned64 op1, unsigned64 op2,
 765                      unsigned64 op3, FP_formats fmt);
 766 #define NegMultiplyAdd(op1,op2,op3,fmt) fp_nmadd(SIM_ARGS, op1, op2, op3, fmt)
 767 unsigned64 fp_nmsub (SIM_STATE, unsigned64 op1, unsigned64 op2,
 768                      unsigned64 op3, FP_formats fmt);
 769 #define NegMultiplySub(op1,op2,op3,fmt) fp_nmsub(SIM_ARGS, op1, op2, op3, fmt)
 770 unsigned64 convert (SIM_STATE, int rm, unsigned64 op, FP_formats from, FP_formats to);
 771 #define Convert(rm,op,from,to) convert (SIM_ARGS, rm, op, from, to)
 772 unsigned64 convert_ps (SIM_STATE, int rm, unsigned64 op, FP_formats from,
 773                        FP_formats to);
 774 #define ConvertPS(rm,op,from,to) convert_ps (SIM_ARGS, rm, op, from, to)
 775
 776
 777 /* MIPS-3D ASE operations.  */
 778 #define CompareAbs(op1,op2,fmt,cond,cc) \
 779 fp_cmp(SIM_ARGS, op1, op2, fmt, 1, cond, cc)
 780 unsigned64 fp_add_r (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
 781 #define AddR(op1,op2,fmt) fp_add_r(SIM_ARGS, op1, op2, fmt)
 782 unsigned64 fp_mul_r (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
 783 #define MultiplyR(op1,op2,fmt) fp_mul_r(SIM_ARGS, op1, op2, fmt)
 784 unsigned64 fp_recip1 (SIM_STATE, unsigned64 op, FP_formats fmt);
 785 #define Recip1(op,fmt) fp_recip1(SIM_ARGS, op, fmt)
 786 unsigned64 fp_recip2 (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
 787 #define Recip2(op1,op2,fmt) fp_recip2(SIM_ARGS, op1, op2, fmt)
 788 unsigned64 fp_rsqrt1 (SIM_STATE, unsigned64 op, FP_formats fmt);
 789 #define RSquareRoot1(op,fmt) fp_rsqrt1(SIM_ARGS, op, fmt)
 790 unsigned64 fp_rsqrt2 (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
 791 #define RSquareRoot2(op1,op2,fmt) fp_rsqrt2(SIM_ARGS, op1, op2, fmt)
 792
 793
 794 /* MDMX access.  */
 795
 796 typedef unsigned int MX_fmtsel;   /* MDMX format select field (5 bits).  */
 797 #define ob_fmtsel(sel) (((sel)<<1)|0x0)
 798 #define qh_fmtsel(sel) (((sel)<<2)|0x1)
 799
 800 #define fmt_mdmx fmt_uninterpreted
 801
 802 #define MX_VECT_AND  (0)
 803 #define MX_VECT_NOR  (1)
 804 #define MX_VECT_OR   (2)
 805 #define MX_VECT_XOR  (3)
 806 #define MX_VECT_SLL  (4)
 807 #define MX_VECT_SRL  (5)
 808 #define MX_VECT_ADD  (6)
 809 #define MX_VECT_SUB  (7)
 810 #define MX_VECT_MIN  (8)
 811 #define MX_VECT_MAX  (9)
 812 #define MX_VECT_MUL  (10)
 813 #define MX_VECT_MSGN (11)
 814 #define MX_VECT_SRA  (12)
 815 #define MX_VECT_ABSD (13)               /* SB-1 only.  */
 816 #define MX_VECT_AVG  (14)               /* SB-1 only.  */
 817
 818 unsigned64 mdmx_cpr_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmtsel);
 819 #define MX_Add(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_ADD, op1, vt, fmtsel)
 820 #define MX_And(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_AND, op1, vt, fmtsel)
 821 #define MX_Max(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MAX, op1, vt, fmtsel)
 822 #define MX_Min(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MIN, op1, vt, fmtsel)
 823 #define MX_Msgn(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MSGN, op1, vt, fmtsel)
 824 #define MX_Mul(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MUL, op1, vt, fmtsel)
 825 #define MX_Nor(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_NOR, op1, vt, fmtsel)
 826 #define MX_Or(op1,vt,fmtsel)  mdmx_cpr_op(SIM_ARGS, MX_VECT_OR,  op1, vt, fmtsel)
 827 #define MX_ShiftLeftLogical(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SLL, op1, vt, fmtsel)
 828 #define MX_ShiftRightArith(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SRA, op1, vt, fmtsel)
 829 #define MX_ShiftRightLogical(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SRL, op1, vt, fmtsel)
 830 #define MX_Sub(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SUB, op1, vt, fmtsel)
 831 #define MX_Xor(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_XOR, op1, vt, fmtsel)
 832 #define MX_AbsDiff(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_ABSD, op1, vt, fmtsel)
 833 #define MX_Avg(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_AVG, op1, vt, fmtsel)
 834
 835 #define MX_C_EQ  0x1
 836 #define MX_C_LT  0x4
 837
 838 void mdmx_cc_op (SIM_STATE, int cond, unsigned64 op1, int vt, MX_fmtsel fmtsel);
 839 #define MX_Comp(op1,cond,vt,fmtsel) mdmx_cc_op(SIM_ARGS, cond, op1, vt, fmtsel)
 840
 841 unsigned64 mdmx_pick_op (SIM_STATE, int tf, unsigned64 op1, int vt, MX_fmtsel fmtsel);
 842 #define MX_Pick(tf,op1,vt,fmtsel) mdmx_pick_op(SIM_ARGS, tf, op1, vt, fmtsel)
 843
 844 #define MX_VECT_ADDA  (0)
 845 #define MX_VECT_ADDL  (1)
 846 #define MX_VECT_MULA  (2)
 847 #define MX_VECT_MULL  (3)
 848 #define MX_VECT_MULS  (4)
 849 #define MX_VECT_MULSL (5)
 850 #define MX_VECT_SUBA  (6)
 851 #define MX_VECT_SUBL  (7)
 852 #define MX_VECT_ABSDA (8)               /* SB-1 only.  */
 853
 854 void mdmx_acc_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmtsel);
 855 #define MX_AddA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ADDA, op1, vt, fmtsel)
 856 #define MX_AddL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ADDL, op1, vt, fmtsel)
 857 #define MX_MulA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULA, op1, vt, fmtsel)
 858 #define MX_MulL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULL, op1, vt, fmtsel)
 859 #define MX_MulS(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULS, op1, vt, fmtsel)
 860 #define MX_MulSL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULSL, op1, vt, fmtsel)
 861 #define MX_SubA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_SUBA, op1, vt, fmtsel)
 862 #define MX_SubL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_SUBL, op1, vt, fmtsel)
 863 #define MX_AbsDiffC(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ABSDA, op1, vt, fmtsel)
 864
 865 #define MX_FMT_OB   (0)
 866 #define MX_FMT_QH   (1)
 867
 868 /* The following codes chosen to indicate the units of shift.  */
 869 #define MX_RAC_L    (0)
 870 #define MX_RAC_M    (1)
 871 #define MX_RAC_H    (2)
 872
 873 unsigned64 mdmx_rac_op (SIM_STATE, int, int);
 874 #define MX_RAC(op,fmt) mdmx_rac_op(SIM_ARGS, op, fmt)
 875
 876 void mdmx_wacl (SIM_STATE, int, unsigned64, unsigned64);
 877 #define MX_WACL(fmt,vs,vt) mdmx_wacl(SIM_ARGS, fmt, vs, vt)
 878 void mdmx_wach (SIM_STATE, int, unsigned64);
 879 #define MX_WACH(fmt,vs) mdmx_wach(SIM_ARGS, fmt, vs)
 880
 881 #define MX_RND_AS   (0)
 882 #define MX_RND_AU   (1)
 883 #define MX_RND_ES   (2)
 884 #define MX_RND_EU   (3)
 885 #define MX_RND_ZS   (4)
 886 #define MX_RND_ZU   (5)
 887
 888 unsigned64 mdmx_round_op (SIM_STATE, int, int, MX_fmtsel);
 889 #define MX_RNAS(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_AS, vt, fmt)
 890 #define MX_RNAU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_AU, vt, fmt)
 891 #define MX_RNES(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ES, vt, fmt)
 892 #define MX_RNEU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_EU, vt, fmt)
 893 #define MX_RZS(vt,fmt)  mdmx_round_op(SIM_ARGS, MX_RND_ZS, vt, fmt)
 894 #define MX_RZU(vt,fmt)  mdmx_round_op(SIM_ARGS, MX_RND_ZU, vt, fmt)
 895
 896 unsigned64 mdmx_shuffle (SIM_STATE, int, unsigned64, unsigned64);
 897 #define MX_SHFL(shop,op1,op2) mdmx_shuffle(SIM_ARGS, shop, op1, op2)
 898
 899
 900
 901 /* Memory accesses */
 902
 903 /* The following are generic to all versions of the MIPS architecture
 904    to date: */
 905
 906 /* Memory Access Types (for CCA): */
 907 #define Uncached                (0)
 908 #define CachedNoncoherent       (1)
 909 #define CachedCoherent          (2)
 910 #define Cached                  (3)
 911
 912 #define isINSTRUCTION   (1 == 0) /* FALSE */
 913 #define isDATA          (1 == 1) /* TRUE */
 914 #define isLOAD          (1 == 0) /* FALSE */
 915 #define isSTORE         (1 == 1) /* TRUE */
 916 #define isREAL          (1 == 0) /* FALSE */
 917 #define isRAW           (1 == 1) /* TRUE */
 918 /* The parameter HOST (isTARGET / isHOST) is ignored */
 919 #define isTARGET        (1 == 0) /* FALSE */
 920 /* #define isHOST          (1 == 1) TRUE */
 921
 922 /* The "AccessLength" specifications for Loads and Stores. NOTE: This
 923    is the number of bytes minus 1. */
 924 #define AccessLength_BYTE       (0)
 925 #define AccessLength_HALFWORD   (1)
 926 #define AccessLength_TRIPLEBYTE (2)
 927 #define AccessLength_WORD       (3)
 928 #define AccessLength_QUINTIBYTE (4)
 929 #define AccessLength_SEXTIBYTE  (5)
 930 #define AccessLength_SEPTIBYTE  (6)
 931 #define AccessLength_DOUBLEWORD (7)
 932 #define AccessLength_QUADWORD   (15)
 933
 934 #define LOADDRMASK (WITH_TARGET_WORD_BITSIZE == 64 \
 935                     ? AccessLength_DOUBLEWORD /*7*/ \
 936                     : AccessLength_WORD /*3*/)
 937 #define PSIZE (WITH_TARGET_ADDRESS_BITSIZE)
 938
 939
 940 INLINE_SIM_MAIN (int) address_translation (SIM_DESC sd, sim_cpu *, address_word cia, address_word vAddr, int IorD, int LorS, address_word *pAddr, int *CCA, int raw);
 941 #define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \
 942 address_translation (SD, CPU, cia, vAddr, IorD, LorS, pAddr, CCA, raw)
 943
 944 INLINE_SIM_MAIN (void) load_memory (SIM_DESC sd, sim_cpu *cpu, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, unsigned int AccessLength, address_word pAddr, address_word vAddr, int IorD);
 945 #define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \
 946 load_memory (SD, CPU, cia, memvalp, memval1p, CCA, AccessLength, pAddr, vAddr, IorD)
 947
 948 INLINE_SIM_MAIN (void) store_memory (SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, unsigned int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr);
 949 #define StoreMemory(CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \
 950 store_memory (SD, CPU, cia, CCA, AccessLength, MemElem, MemElem1, pAddr, vAddr)
 951
 952 INLINE_SIM_MAIN (void) cache_op (SIM_DESC sd, sim_cpu *cpu, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction);
 953 #define CacheOp(op,pAddr,vAddr,instruction) \
 954 cache_op (SD, CPU, cia, op, pAddr, vAddr, instruction)
 955
 956 INLINE_SIM_MAIN (void) sync_operation (SIM_DESC sd, sim_cpu *cpu, address_word cia, int stype);
 957 #define SyncOperation(stype) \
 958 sync_operation (SD, CPU, cia, (stype))
 959
 960 INLINE_SIM_MAIN (void) prefetch (SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, address_word pAddr, address_word vAddr, int DATA, int hint);
 961 #define Prefetch(CCA,pAddr,vAddr,DATA,hint) \
 962 prefetch (SD, CPU, cia, CCA, pAddr, vAddr, DATA, hint)
 963
 964 void unpredictable_action (sim_cpu *cpu, address_word cia);
 965 #define NotWordValue(val)       not_word_value (SD_, (val))
 966 #define Unpredictable()         unpredictable (SD_)
 967 #define UnpredictableResult()   /* For now, do nothing.  */
 968
 969 INLINE_SIM_MAIN (unsigned32) ifetch32 (SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr);
 970 #define IMEM32(CIA) ifetch32 (SD, CPU, (CIA), (CIA))
 971 INLINE_SIM_MAIN (unsigned16) ifetch16 (SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr);
 972 #define IMEM16(CIA) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1))
 973 #define IMEM16_IMMED(CIA,NR) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1) + 2 * (NR))
 974
 975 void dotrace (SIM_DESC sd, sim_cpu *cpu, FILE *tracefh, int type, SIM_ADDR address, int width, char *comment, ...);
 976 extern FILE *tracefh;
 977
 978 extern int DSPLO_REGNUM[4];
 979 extern int DSPHI_REGNUM[4];
 980
 981 INLINE_SIM_MAIN (void) pending_tick (SIM_DESC sd, sim_cpu *cpu, address_word cia);
 982 extern SIM_CORE_SIGNAL_FN mips_core_signal;
 983
 984 char* pr_addr (SIM_ADDR addr);
 985 char* pr_uword64 (uword64 addr);
 986
 987
 988 #define GPR_CLEAR(N) do { GPR_SET((N),0); } while (0)
 989
 990 void mips_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word pc);
 991 void mips_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception);
 992 void mips_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception);
 993
 994 #ifdef MIPS_MACH_MULTI
 995 extern int mips_mach_multi(SIM_DESC sd);
 996 #define MIPS_MACH(SD)   mips_mach_multi(SD)
 997 #else
 998 #define MIPS_MACH(SD)   MIPS_MACH_DEFAULT
 999 #endif
1000
1001 /* Macros for determining whether a MIPS IV or MIPS V part is subject
1002    to the hi/lo restrictions described in mips.igen.  */
1003
1004 #define MIPS_MACH_HAS_MT_HILO_HAZARD(SD) \
1005   (MIPS_MACH (SD) != bfd_mach_mips5500)
1006
1007 #define MIPS_MACH_HAS_MULT_HILO_HAZARD(SD) \
1008   (MIPS_MACH (SD) != bfd_mach_mips5500)
1009
1010 #define MIPS_MACH_HAS_DIV_HILO_HAZARD(SD) \
1011   (MIPS_MACH (SD) != bfd_mach_mips5500)
1012
1013 #if H_REVEALS_MODULE_P (SIM_MAIN_INLINE)
1014 #include "sim-main.c"
1015 #endif
1016
1017 #endif