sim/mips/sim-main.h

   1 /* MIPS Simulator definition.
   2    Copyright (C) 1997 Free Software Foundation, Inc.
   3    Contributed by Cygnus Support.
   4
   5 This file is part of GDB, the GNU debugger.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 2, or (at your option)
  10 any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License along
  18 with this program; if not, write to the Free Software Foundation, Inc.,
  19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  20
  21 #ifndef SIM_MAIN_H
  22 #define SIM_MAIN_H
  23
  24 /* This simulator doesn't cache the Current Instruction Address */
  25 /* #define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA) */
  26 /* #define SIM_ENGINE_RESUME_HOOK(SD, LAST_CPU, CIA) */
  27
  28 #define SIM_HAVE_BIENDIAN
  29
  30
  31 /* hobble some common features for moment */
  32 #define WITH_WATCHPOINTS 1
  33 #define WITH_MODULO_MEMORY 1
  34
  35 #include "sim-basics.h"
  36
  37 typedef address_word sim_cia;
  38
  39 #if (WITH_IGEN)
  40 /* Get the number of instructions.  FIXME: must be a more elegant way
  41    of doing this.  */
  42 #include "itable.h"
  43 #define MAX_INSNS (nr_itable_entries)
  44 #define INSN_NAME(i) itable[(i)].name
  45 #endif
  46
  47 #include "sim-base.h"
  48
  49
  50 /* Depreciated macros and types for manipulating 64bit values.  Use
  51    ../common/sim-bits.h and ../common/sim-endian.h macros instead. */
  52
  53 typedef signed64 word64;
  54 typedef unsigned64 uword64;
  55
  56 #define WORD64LO(t)     (unsigned int)((t)&0xFFFFFFFF)
  57 #define WORD64HI(t)     (unsigned int)(((uword64)(t))>>32)
  58 #define SET64LO(t)      (((uword64)(t))&0xFFFFFFFF)
  59 #define SET64HI(t)      (((uword64)(t))<<32)
  60 #define WORD64(h,l)     ((word64)((SET64HI(h)|SET64LO(l))))
  61 #define UWORD64(h,l)     (SET64HI(h)|SET64LO(l))
  62
  63 /* Sign-extend the given value (e) as a value (b) bits long. We cannot
  64    assume the HI32bits of the operand are zero, so we must perform a
  65    mask to ensure we can use the simple subtraction to sign-extend. */
  66 #define SIGNEXTEND(e,b) \
  67  ((unsigned_word) \
  68   (((e) & ((uword64) 1 << ((b) - 1))) \
  69    ? (((e) & (((uword64) 1 << (b)) - 1)) - ((uword64)1 << (b))) \
  70    : ((e) & (((((uword64) 1 << ((b) - 1)) - 1) << 1) | 1))))
  71
  72 /* Check if a value will fit within a halfword: */
  73 #define NOTHALFWORDVALUE(v) ((((((uword64)(v)>>16) == 0) && !((v) & ((unsigned)1 << 15))) || (((((uword64)(v)>>32) == 0xFFFFFFFF) && ((((uword64)(v)>>16) & 0xFFFF) == 0xFFFF)) && ((v) & ((unsigned)1 << 15)))) ? (1 == 0) : (1 == 1))
  74
  75 /* windows always looses */
  76 #include <signal.h>
  77 #ifndef SIGBUS
  78 #define SIGBUS SIGSEGV
  79 #endif
  80 #ifdef _WIN32
  81 #define SIGTRAP 5
  82 #define SIGQUIT 3
  83 #endif
  84
  85
  86
  87 /* Floating-point operations: */
  88
  89 /* FPU registers must be one of the following types. All other values
  90    are reserved (and undefined). */
  91 typedef enum {
  92  fmt_single  = 0,
  93  fmt_double  = 1,
  94  fmt_word    = 4,
  95  fmt_long    = 5,
  96  /* The following are well outside the normal acceptable format
  97     range, and are used in the register status vector. */
  98  fmt_unknown       = 0x10000000,
  99  fmt_uninterpreted = 0x20000000,
 100  fmt_uninterpreted_32 = 0x40000000,
 101  fmt_uninterpreted_64 = 0x80000000,
 102 } FP_formats;
 103
 104 unsigned64 value_fpr PARAMS ((SIM_DESC sd, address_word cia, int fpr, FP_formats));
 105 #define ValueFPR(FPR,FMT) value_fpr (sd, cia, (FPR), (FMT))
 106
 107 void store_fpr PARAMS ((SIM_DESC sd, address_word cia, int fpr, FP_formats fmt, unsigned64 value));
 108 #define StoreFPR(FPR,FMT,VALUE) store_fpr (sd, cia, (FPR), (FMT), (VALUE))
 109
 110 int NaN PARAMS ((unsigned64 op, FP_formats fmt));
 111 int Infinity PARAMS ((unsigned64 op, FP_formats fmt));
 112 int Less PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 113 int Equal PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 114 unsigned64 AbsoluteValue PARAMS ((unsigned64 op, FP_formats fmt));
 115 unsigned64 Negate PARAMS ((unsigned64 op, FP_formats fmt));
 116 unsigned64 Add PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 117 unsigned64 Sub PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 118 unsigned64 Multiply PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 119 unsigned64 Divide PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 120 unsigned64 Recip PARAMS ((unsigned64 op, FP_formats fmt));
 121 unsigned64 SquareRoot PARAMS ((unsigned64 op, FP_formats fmt));
 122 unsigned64 convert PARAMS ((SIM_DESC sd, address_word cia, int rm, unsigned64 op, FP_formats from, FP_formats to));
 123 #define Convert(rm,op,from,to) convert(sd,cia,rm,op,from,to)
 124
 125 /* Macro to update FPSR condition-code field. This is complicated by
 126    the fact that there is a hole in the index range of the bits within
 127    the FCSR register. Also, the number of bits visible depends on the
 128    MIPS ISA version being supported. */
 129
 130 #define SETFCC(cc,v) {\
 131   int bit = ((cc == 0) ? 23 : (24 + (cc)));\
 132   FCSR = ((FCSR & ~(1 << bit)) | ((v) << bit));\
 133 }
 134 #define GETFCC(cc) (((((cc) == 0) ? (FCSR & (1 << 23)) : (FCSR & (1 << (24 + (cc))))) != 0) ? 1 : 0)
 135
 136 /* This should be the COC1 value at the start of the preceding
 137    instruction: */
 138 #define PREVCOC1() ((STATE & simPCOC1) ? 1 : 0)
 139
 140 #if 1
 141 #define SizeFGR() (WITH_TARGET_WORD_BITSIZE)
 142 #else
 143 /* They depend on the CPU being simulated */
 144 #define SizeFGR() ((WITH_TARGET_WORD_BITSIZE == 64 && ((SR & status_FR) == 1)) ? 64 : 32)
 145 #endif
 146
 147 /* Standard FCRS bits: */
 148 #define IR (0) /* Inexact Result */
 149 #define UF (1) /* UnderFlow */
 150 #define OF (2) /* OverFlow */
 151 #define DZ (3) /* Division by Zero */
 152 #define IO (4) /* Invalid Operation */
 153 #define UO (5) /* Unimplemented Operation */
 154
 155 /* Get masks for individual flags: */
 156 #if 1 /* SAFE version */
 157 #define FP_FLAGS(b)  (((unsigned)(b) < 5) ? (1 << ((b) + 2)) : 0)
 158 #define FP_ENABLE(b) (((unsigned)(b) < 5) ? (1 << ((b) + 7)) : 0)
 159 #define FP_CAUSE(b)  (((unsigned)(b) < 6) ? (1 << ((b) + 12)) : 0)
 160 #else
 161 #define FP_FLAGS(b)  (1 << ((b) + 2))
 162 #define FP_ENABLE(b) (1 << ((b) + 7))
 163 #define FP_CAUSE(b)  (1 << ((b) + 12))
 164 #endif
 165
 166 #define FP_FS         (1 << 24) /* MIPS III onwards : Flush to Zero */
 167
 168 #define FP_MASK_RM    (0x3)
 169 #define FP_SH_RM      (0)
 170 #define FP_RM_NEAREST (0) /* Round to nearest        (Round) */
 171 #define FP_RM_TOZERO  (1) /* Round to zero           (Trunc) */
 172 #define FP_RM_TOPINF  (2) /* Round to Plus infinity  (Ceil) */
 173 #define FP_RM_TOMINF  (3) /* Round to Minus infinity (Floor) */
 174 #define GETRM()       (int)((FCSR >> FP_SH_RM) & FP_MASK_RM)
 175
 176
 177
 178 /* Integer ALU operations: */
 179
 180 #include "sim-alu.h"
 181
 182 #define ALU32_END(ANS) \
 183   if (ALU32_HAD_OVERFLOW) \
 184     SignalExceptionIntegerOverflow (); \
 185   (ANS) = ALU32_OVERFLOW_RESULT
 186
 187
 188 #define ALU64_END(ANS) \
 189   if (ALU64_HAD_OVERFLOW) \
 190     SignalExceptionIntegerOverflow (); \
 191   (ANS) = ALU64_OVERFLOW_RESULT;
 192
 193 /* start-sanitize-r5900 */
 194
 195 #define BYTES_IN_MMI_REGS       (sizeof(signed_word) + sizeof(signed_word))
 196 #define HALFWORDS_IN_MMI_REGS   (BYTES_IN_MMI_REGS/2)
 197 #define WORDS_IN_MMI_REGS       (BYTES_IN_MMI_REGS/4)
 198 #define DOUBLEWORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/8)
 199
 200 #define BYTES_IN_MIPS_REGS       (sizeof(signed_word))
 201 #define HALFWORDS_IN_MIPS_REGS   (BYTES_IN_MIPS_REGS/2)
 202 #define WORDS_IN_MIPS_REGS       (BYTES_IN_MIPS_REGS/4)
 203 #define DOUBLEWORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/8)
 204
 205 /* SUB_REG_FETCH - return as lvalue some sub-part of a "register"
 206    T  - type of the sub part
 207    TC - # of T's in the mips part of the "register"
 208    I  - index (from 0) of desired sub part
 209    A  - low part of "register"
 210    A1 - high part of register
 211 */
 212 #define SUB_REG_FETCH(T,TC,A,A1,I) \
 213 (*(((I) < (TC) ? (T*)(A) : (T*)(A1)) \
 214    + (CURRENT_HOST_BYTE_ORDER == BIG_ENDIAN \
 215       ? ((TC) - 1 - (I) % (TC)) \
 216       : ((I) % (TC)) \
 217       ) \
 218    ) \
 219  )
 220
 221 /*
 222 GPR_<type>(R,I) - return, as lvalue, the I'th <type> of general register R
 223             where <type> has two letters:
 224                   1 is S=signed or U=unsigned
 225                   2 is B=byte H=halfword W=word D=doubleword
 226 */
 227
 228 #define SUB_REG_SB(A,A1,I) SUB_REG_FETCH(signed8,  BYTES_IN_MIPS_REGS,       A, A1, I)
 229 #define SUB_REG_SH(A,A1,I) SUB_REG_FETCH(signed16, HALFWORDS_IN_MIPS_REGS,   A, A1, I)
 230 #define SUB_REG_SW(A,A1,I) SUB_REG_FETCH(signed32, WORDS_IN_MIPS_REGS,       A, A1, I)
 231 #define SUB_REG_SD(A,A1,I) SUB_REG_FETCH(signed64, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
 232
 233 #define SUB_REG_UB(A,A1,I) SUB_REG_FETCH(unsigned8,  BYTES_IN_MIPS_REGS,       A, A1, I)
 234 #define SUB_REG_UH(A,A1,I) SUB_REG_FETCH(unsigned16, HALFWORDS_IN_MIPS_REGS,   A, A1, I)
 235 #define SUB_REG_UW(A,A1,I) SUB_REG_FETCH(unsigned32, WORDS_IN_MIPS_REGS,       A, A1, I)
 236 #define SUB_REG_UD(A,A1,I) SUB_REG_FETCH(unsigned64, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
 237
 238 #define GPR_SB(R,I) SUB_REG_SB(&REGISTERS[R], &REGISTERS1[R], I)
 239 #define GPR_SH(R,I) SUB_REG_SH(&REGISTERS[R], &REGISTERS1[R], I)
 240 #define GPR_SW(R,I) SUB_REG_SW(&REGISTERS[R], &REGISTERS1[R], I)
 241 #define GPR_SD(R,I) SUB_REG_SD(&REGISTERS[R], &REGISTERS1[R], I)
 242
 243 #define GPR_UB(R,I) SUB_REG_UB(&REGISTERS[R], &REGISTERS1[R], I)
 244 #define GPR_UH(R,I) SUB_REG_UH(&REGISTERS[R], &REGISTERS1[R], I)
 245 #define GPR_UW(R,I) SUB_REG_UW(&REGISTERS[R], &REGISTERS1[R], I)
 246 #define GPR_UD(R,I) SUB_REG_UD(&REGISTERS[R], &REGISTERS1[R], I)
 247
 248
 249 #define RS_SB(I) SUB_REG_SB(&rs_reg, &rs_reg1, I)
 250 #define RS_SH(I) SUB_REG_SH(&rs_reg, &rs_reg1, I)
 251 #define RS_SW(I) SUB_REG_SW(&rs_reg, &rs_reg1, I)
 252 #define RS_SD(I) SUB_REG_SD(&rs_reg, &rs_reg1, I)
 253
 254 #define RS_UB(I) SUB_REG_UB(&rs_reg, &rs_reg1, I)
 255 #define RS_UH(I) SUB_REG_UH(&rs_reg, &rs_reg1, I)
 256 #define RS_UW(I) SUB_REG_UW(&rs_reg, &rs_reg1, I)
 257 #define RS_UD(I) SUB_REG_UD(&rs_reg, &rs_reg1, I)
 258
 259 #define RT_SB(I) SUB_REG_SB(&rt_reg, &rt_reg1, I)
 260 #define RT_SH(I) SUB_REG_SH(&rt_reg, &rt_reg1, I)
 261 #define RT_SW(I) SUB_REG_SW(&rt_reg, &rt_reg1, I)
 262 #define RT_SD(I) SUB_REG_SD(&rt_reg, &rt_reg1, I)
 263
 264 #define RT_UB(I) SUB_REG_UB(&rt_reg, &rt_reg1, I)
 265 #define RT_UH(I) SUB_REG_UH(&rt_reg, &rt_reg1, I)
 266 #define RT_UW(I) SUB_REG_UW(&rt_reg, &rt_reg1, I)
 267 #define RT_UD(I) SUB_REG_UD(&rt_reg, &rt_reg1, I)
 268
 269
 270
 271 #define LO_SB(I) SUB_REG_SB(&LO, &LO1, I)
 272 #define LO_SH(I) SUB_REG_SH(&LO, &LO1, I)
 273 #define LO_SW(I) SUB_REG_SW(&LO, &LO1, I)
 274 #define LO_SD(I) SUB_REG_SD(&LO, &LO1, I)
 275
 276 #define LO_UB(I) SUB_REG_UB(&LO, &LO1, I)
 277 #define LO_UH(I) SUB_REG_UH(&LO, &LO1, I)
 278 #define LO_UW(I) SUB_REG_UW(&LO, &LO1, I)
 279 #define LO_UD(I) SUB_REG_UD(&LO, &LO1, I)
 280
 281 #define HI_SB(I) SUB_REG_SB(&HI, &HI1, I)
 282 #define HI_SH(I) SUB_REG_SH(&HI, &HI1, I)
 283 #define HI_SW(I) SUB_REG_SW(&HI, &HI1, I)
 284 #define HI_SD(I) SUB_REG_SD(&HI, &HI1, I)
 285
 286 #define HI_UB(I) SUB_REG_UB(&HI, &HI1, I)
 287 #define HI_UH(I) SUB_REG_UH(&HI, &HI1, I)
 288 #define HI_UW(I) SUB_REG_UW(&HI, &HI1, I)
 289 #define HI_UD(I) SUB_REG_UD(&HI, &HI1, I)
 290
 291 /* end-sanitize-r5900 */
 292
 293
 294
 295
 296 struct _sim_cpu {
 297
 298
 299   /* The following are internal simulator state variables: */
 300 #define CPU_CIA(CPU) (PC)
 301   address_word dspc;  /* delay-slot PC */
 302 #define DSPC ((STATE_CPU (sd,0))->dspc)
 303
 304   /* Issue a delay slot instruction immediatly by re-calling
 305      idecode_issue */
 306 #define DELAY_SLOT(TARGET) \
 307   do { \
 308     address_word target = (TARGET); \
 309     instruction_word delay_insn; \
 310     sim_events_slip (sd, 1); \
 311     CIA = CIA + 4; \
 312     STATE |= simDELAYSLOT; \
 313     delay_insn = IMEM (CIA); \
 314     idecode_issue (sd, delay_insn, (CIA)); \
 315     STATE &= ~simDELAYSLOT; \
 316     NIA = target; \
 317   } while (0)
 318 #define NULLIFY_NEXT_INSTRUCTION() \
 319   do { \
 320     sim_events_slip (sd, 1); \
 321     dotrace (sd, tracefh, 2, NIA, 4, "load instruction"); \
 322     NIA = CIA + 8; \
 323   } while (0)
 324
 325
 326
 327   /* State of the simulator */
 328   unsigned int state;
 329   unsigned int dsstate;
 330 #define STATE ((STATE_CPU (sd,0))->state)
 331 #define DSSTATE ((STATE_CPU (sd,0))->dsstate)
 332
 333 /* Flags in the "state" variable: */
 334 #define simHALTEX       (1 << 2)  /* 0 = run; 1 = halt on exception */
 335 #define simHALTIN       (1 << 3)  /* 0 = run; 1 = halt on interrupt */
 336 #define simTRACE        (1 << 8)  /* 0 = do nothing; 1 = trace address activity */
 337 #define simPCOC0        (1 << 17) /* COC[1] from current */
 338 #define simPCOC1        (1 << 18) /* COC[1] from previous */
 339 #define simDELAYSLOT    (1 << 24) /* 0 = do nothing; 1 = delay slot entry exists */
 340 #define simSKIPNEXT     (1 << 25) /* 0 = do nothing; 1 = skip instruction */
 341 #define simSIGINT       (1 << 28)  /* 0 = do nothing; 1 = SIGINT has occured */
 342 #define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */
 343
 344 #define ENGINE_ISSUE_PREFIX_HOOK() \
 345   { \
 346     /* Set previous flag, depending on current: */ \
 347     if (STATE & simPCOC0) \
 348      STATE |= simPCOC1; \
 349     else \
 350      STATE &= ~simPCOC1; \
 351     /* and update the current value: */ \
 352     if (GETFCC(0)) \
 353      STATE |= simPCOC0; \
 354     else \
 355      STATE &= ~simPCOC0; \
 356   }
 357
 358
 359 /* This is nasty, since we have to rely on matching the register
 360    numbers used by GDB. Unfortunately, depending on the MIPS target
 361    GDB uses different register numbers. We cannot just include the
 362    relevant "gdb/tm.h" link, since GDB may not be configured before
 363    the sim world, and also the GDB header file requires too much other
 364    state. */
 365
 366 #ifndef TM_MIPS_H
 367 #define LAST_EMBED_REGNUM (89)
 368 #define NUM_REGS (LAST_EMBED_REGNUM + 1)
 369 /* start-sanitize-r5900 */
 370 #undef NUM_REGS
 371 #define NUM_REGS (128)
 372 /* end-sanitize-r5900 */
 373 #endif
 374
 375 /* To keep this default simulator simple, and fast, we use a direct
 376    vector of registers. The internal simulator engine then uses
 377    manifests to access the correct slot. */
 378
 379   unsigned_word registers[LAST_EMBED_REGNUM + 1];
 380   int register_widths[NUM_REGS];
 381 #define REGISTERS       ((STATE_CPU (sd,0))->registers)
 382
 383 #define GPR     (&REGISTERS[0])
 384 #define FGRIDX  (38)
 385 #define FGR     (&REGISTERS[FGRIDX])
 386 #define LO      (REGISTERS[33])
 387 #define HI      (REGISTERS[34])
 388 #define PC      (REGISTERS[37])
 389 #define CAUSE   (REGISTERS[36])
 390 #define SRIDX   (32)
 391 #define SR      (REGISTERS[SRIDX])      /* CPU status register */
 392 #define FCR0IDX  (71)
 393 #define FCR0    (REGISTERS[FCR0IDX])    /* really a 32bit register */
 394 #define FCR31IDX (70)
 395 #define FCR31   (REGISTERS[FCR31IDX])   /* really a 32bit register */
 396 #define FCSR    (FCR31)
 397 #define Debug   (REGISTERS[86])
 398 #define DEPC    (REGISTERS[87])
 399 #define EPC     (REGISTERS[88])
 400 #define COCIDX  (LAST_EMBED_REGNUM + 2) /* special case : outside the normal range */
 401
 402   unsigned_word c0_config_reg;
 403 #define C0_CONFIG ((STATE_CPU (sd,0))->c0_config_reg)
 404
 405 /* The following are pseudonyms for standard registers */
 406 #define ZERO    (REGISTERS[0])
 407 #define V0      (REGISTERS[2])
 408 #define A0      (REGISTERS[4])
 409 #define A1      (REGISTERS[5])
 410 #define A2      (REGISTERS[6])
 411 #define A3      (REGISTERS[7])
 412 #define SP      (REGISTERS[29])
 413 #define RA      (REGISTERS[31])
 414
 415   /* Keep the current format state for each register: */
 416   FP_formats fpr_state[32];
 417 #define FPR_STATE ((STATE_CPU (sd, 0))->fpr_state)
 418
 419
 420   /* Slots for delayed register updates. For the moment we just have a
 421      fixed number of slots (rather than a more generic, dynamic
 422      system). This keeps the simulator fast. However, we only allow
 423      for the register update to be delayed for a single instruction
 424      cycle. */
 425 #define PSLOTS (5) /* Maximum number of instruction cycles */
 426   int pending_in;
 427   int pending_out;
 428   int pending_total;
 429   int pending_slot_count[PSLOTS];
 430   int pending_slot_reg[PSLOTS];
 431   unsigned_word pending_slot_value[PSLOTS];
 432 #define PENDING_IN ((STATE_CPU (sd, 0))->pending_in)
 433 #define PENDING_OUT ((STATE_CPU (sd, 0))->pending_out)
 434 #define PENDING_TOTAL ((STATE_CPU (sd, 0))->pending_total)
 435 #define PENDING_SLOT_COUNT ((STATE_CPU (sd, 0))->pending_slot_count)
 436 #define PENDING_SLOT_REG ((STATE_CPU (sd, 0))->pending_slot_reg)
 437 #define PENDING_SLOT_VALUE ((STATE_CPU (sd, 0))->pending_slot_value)
 438
 439   /* The following are not used for MIPS IV onwards: */
 440 #define PENDING_FILL(r,v) {\
 441 /* printf("DBG: FILL BEFORE pending_in = %d, pending_out = %d, pending_total = %d\n",PENDING_IN,PENDING_OUT,PENDING_TOTAL); */\
 442                             if (PENDING_SLOT_REG[PENDING_IN] != (LAST_EMBED_REGNUM + 1))\
 443                              sim_io_eprintf(sd,"Attempt to over-write pending value\n");\
 444                             PENDING_SLOT_COUNT[PENDING_IN] = 2;\
 445                             PENDING_SLOT_REG[PENDING_IN] = (r);\
 446                             PENDING_SLOT_VALUE[PENDING_IN] = (uword64)(v);\
 447 /*printf("DBG: FILL        reg %d value = 0x%s\n",(r),pr_addr(v));*/\
 448                             PENDING_TOTAL++;\
 449                             PENDING_IN++;\
 450                             if (PENDING_IN == PSLOTS)\
 451                              PENDING_IN = 0;\
 452 /*printf("DBG: FILL AFTER  pending_in = %d, pending_out = %d, pending_total = %d\n",PENDING_IN,PENDING_OUT,PENDING_TOTAL);*/\
 453                           }
 454
 455
 456   /* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic
 457      read-write instructions. It is set when a linked load occurs. It
 458      is tested and cleared by the conditional store. It is cleared
 459      (during other CPU operations) when a store to the location would
 460      no longer be atomic. In particular, it is cleared by exception
 461      return instructions. */
 462   int llbit;
 463 #define LLBIT ((STATE_CPU (sd, 0))->llbit)
 464
 465
 466 /* The HIACCESS and LOACCESS counts are used to ensure that
 467    corruptions caused by using the HI or LO register to close to a
 468    following operation are spotted. */
 469
 470   int hiaccess;
 471   int loaccess;
 472 #define HIACCESS ((STATE_CPU (sd, 0))->hiaccess)
 473 #define LOACCESS ((STATE_CPU (sd, 0))->loaccess)
 474   /* start-sanitize-r5900 */
 475   int hi1access;
 476   int lo1access;
 477 #define HI1ACCESS ((STATE_CPU (sd, 0))->hi1access)
 478 #define LO1ACCESS ((STATE_CPU (sd, 0))->lo1access)
 479   /* end-sanitize-r5900 */
 480 #if 1
 481   /* The 4300 and a few other processors have interlocks on hi/lo
 482      register reads, and hence do not have this problem.  To avoid
 483      spurious warnings, we just disable this always.  */
 484 #define CHECKHILO(s)
 485 #else
 486   unsigned_word HLPC;
 487   /* If either of the preceding two instructions have accessed the HI
 488      or LO registers, then the values they see should be
 489      undefined. However, to keep the simulator world simple, we just
 490      let them use the value read and raise a warning to notify the
 491      user: */
 492 #define CHECKHILO(s) {\
 493   if ((HIACCESS != 0) || (LOACCESS != 0)) \
 494     sim_io_eprintf(sd,"%s over-writing HI and LO registers values (PC = 0x%s HLPC = 0x%s)\n",(s),pr_addr(PC),pr_addr(HLPC));\
 495 }
 496   /* start-sanitize-r5900 */
 497 #undef CHECKHILO
 498 #define CHECKHILO(s) {\
 499   if ((HIACCESS != 0) || (LOACCESS != 0) || (HI1ACCESS != 0) || (LO1ACCESS != 0))\
 500     sim_io_eprintf(sd,"%s over-writing HI and LO registers values (PC = 0x%s HLPC = 0x%s)\n",(s),pr_addr(PC),pr_addr(HLPC));\
 501 }
 502   /* end-sanitize-r5900 */
 503 #endif
 504
 505
 506   /* start-sanitize-r5900 */
 507   /* The R5900 has 128 bit registers, but the hi 64 bits are only
 508      touched by multimedia (MMI) instructions.  The normal mips
 509      instructions just use the lower 64 bits.  To avoid changing the
 510      older parts of the simulator to handle this weirdness, the high
 511      64 bits of each register are kept in a separate array
 512      (registers1).  The high 64 bits of any register are by convention
 513      refered by adding a '1' to the end of the normal register's name.
 514      So LO still refers to the low 64 bits of the LO register, LO1
 515      refers to the high 64 bits of that same register.  */
 516
 517   signed_word registers1[LAST_EMBED_REGNUM + 1];
 518 #define REGISTERS1 ((STATE_CPU (sd, 0))->registers1)
 519 #define GPR1     (&REGISTERS1[0])
 520 #define LO1      (REGISTERS1[32])
 521 #define HI1      (REGISTERS1[33])
 522 #define REGISTER_SA     (124)
 523
 524   unsigned_word sa;        /* the shift amount register */
 525 #define SA ((STATE_CPU (sd, 0))->sa)
 526
 527   /* end-sanitize-r5900 */
 528   /* start-sanitize-vr5400 */
 529
 530   /* end-sanitize-vr5400 */
 531
 532
 533
 534   sim_cpu_base base;
 535 };
 536
 537
 538 /* MIPS specific simulator watch config */
 539
 540 void watch_options_install PARAMS ((SIM_DESC sd));
 541
 542 struct swatch {
 543   sim_event *pc;
 544   sim_event *clock;
 545   sim_event *cycles;
 546 };
 547
 548
 549 /* FIXME: At present much of the simulator is still static */
 550 struct sim_state {
 551
 552   struct swatch watch;
 553
 554   sim_cpu cpu[1];
 555 #if (WITH_SMP)
 556 #define STATE_CPU(sd,n) (&(sd)->cpu[n])
 557 #else
 558 #define STATE_CPU(sd,n) (&(sd)->cpu[0])
 559 #endif
 560
 561   sim_state_base base;
 562 };
 563
 564
 565
 566 /* Status information: */
 567
 568 /* TODO : these should be the bitmasks for these bits within the
 569    status register. At the moment the following are VR4300
 570    bit-positions: */
 571 #define status_KSU_mask  (0x3)          /* mask for KSU bits */
 572 #define status_KSU_shift (3)            /* shift for field */
 573 #define ksu_kernel       (0x0)
 574 #define ksu_supervisor   (0x1)
 575 #define ksu_user         (0x2)
 576 #define ksu_unknown      (0x3)
 577
 578 #define status_IE        (1 <<  0)      /* Interrupt enable */
 579 #define status_EXL       (1 <<  1)      /* Exception level */
 580 #define status_RE        (1 << 25)      /* Reverse Endian in user mode */
 581 #define status_FR        (1 << 26)      /* enables MIPS III additional FP registers */
 582 #define status_SR        (1 << 20)      /* soft reset or NMI */
 583 #define status_BEV       (1 << 22)      /* Location of general exception vectors */
 584 #define status_TS        (1 << 21)      /* TLB shutdown has occurred */
 585 #define status_ERL       (1 <<  2)      /* Error level */
 586 #define status_RP        (1 << 27)      /* Reduced Power mode */
 587
 588 #define cause_BD        ((unsigned)1 << 31)     /* Exception in branch delay slot */
 589
 590 /* NOTE: We keep the following status flags as bit values (1 for true,
 591    0 for false). This allows them to be used in binary boolean
 592    operations without worrying about what exactly the non-zero true
 593    value is. */
 594
 595 /* UserMode */
 596 #define UserMode        ((((SR & status_KSU_mask) >> status_KSU_shift) == ksu_user) ? 1 : 0)
 597
 598 /* BigEndianMem */
 599 /* Hardware configuration. Affects endianness of LoadMemory and
 600    StoreMemory and the endianness of Kernel and Supervisor mode
 601    execution. The value is 0 for little-endian; 1 for big-endian. */
 602 #define BigEndianMem    (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
 603 /*(state & simBE) ? 1 : 0)*/
 604
 605 /* ReverseEndian */
 606 /* This mode is selected if in User mode with the RE bit being set in
 607    SR (Status Register). It reverses the endianness of load and store
 608    instructions. */
 609 #define ReverseEndian   (((SR & status_RE) && UserMode) ? 1 : 0)
 610
 611 /* BigEndianCPU */
 612 /* The endianness for load and store instructions (0=little;1=big). In
 613    User mode this endianness may be switched by setting the state_RE
 614    bit in the SR register. Thus, BigEndianCPU may be computed as
 615    (BigEndianMem EOR ReverseEndian). */
 616 #define BigEndianCPU    (BigEndianMem ^ ReverseEndian) /* Already bits */
 617
 618
 619
 620 /* Exceptions: */
 621
 622 /* NOTE: These numbers depend on the processor architecture being
 623    simulated: */
 624 #define Interrupt               (0)
 625 #define TLBModification         (1)
 626 #define TLBLoad                 (2)
 627 #define TLBStore                (3)
 628 #define AddressLoad             (4)
 629 #define AddressStore            (5)
 630 #define InstructionFetch        (6)
 631 #define DataReference           (7)
 632 #define SystemCall              (8)
 633 #define BreakPoint              (9)
 634 #define ReservedInstruction     (10)
 635 #define CoProcessorUnusable     (11)
 636 #define IntegerOverflow         (12)    /* Arithmetic overflow (IDT monitor raises SIGFPE) */
 637 #define Trap                    (13)
 638 #define FPE                     (15)
 639 #define DebugBreakPoint         (16)
 640 #define Watch                   (23)
 641
 642 /* The following exception code is actually private to the simulator
 643    world. It is *NOT* a processor feature, and is used to signal
 644    run-time errors in the simulator. */
 645 #define SimulatorFault      (0xFFFFFFFF)
 646
 647 void signal_exception (SIM_DESC sd, address_word cia, int exception, ...);
 648 #define SignalException(exc,instruction)     signal_exception (sd, cia, (exc), (instruction))
 649 #define SignalExceptionInterrupt()           signal_exception (sd, NULL_CIA, Interrupt)
 650 #define SignalExceptionInstructionFetch()    signal_exception (sd, cia, InstructionFetch)
 651 #define SignalExceptionAddressStore()        signal_exception (sd, cia, AddressStore)
 652 #define SignalExceptionAddressLoad()         signal_exception (sd, cia, AddressLoad)
 653 #define SignalExceptionSimulatorFault(buf)   signal_exception (sd, cia, SimulatorFault, buf)
 654 #define SignalExceptionFPE()                 signal_exception (sd, cia, FPE)
 655 #define SignalExceptionIntegerOverflow()     signal_exception (sd, cia, IntegerOverflow)
 656 #define SignalExceptionCoProcessorUnusable() signal_exception (sd, cia, CoProcessorUnusable)
 657
 658
 659 /* Co-processor accesses */
 660
 661 void cop_lw  PARAMS ((SIM_DESC sd, address_word cia, int coproc_num, int coproc_reg, unsigned int memword));
 662 void cop_ld  PARAMS ((SIM_DESC sd, address_word cia, int coproc_num, int coproc_reg, uword64 memword));
 663 unsigned int cop_sw PARAMS ((SIM_DESC sd, address_word cia, int coproc_num, int coproc_reg));
 664 uword64 cop_sd PARAMS ((SIM_DESC sd, address_word cia, int coproc_num, int coproc_reg));
 665
 666 #define COP_LW(coproc_num,coproc_reg,memword) cop_lw(sd,cia,coproc_num,coproc_reg,memword)
 667 #define COP_LD(coproc_num,coproc_reg,memword) cop_ld(sd,cia,coproc_num,coproc_reg,memword)
 668 #define COP_SW(coproc_num,coproc_reg) cop_sw(sd,cia,coproc_num,coproc_reg)
 669 #define COP_SD(coproc_num,coproc_reg) cop_sd(sd,cia,coproc_num,coproc_reg)
 670
 671 void decode_coproc PARAMS ((SIM_DESC sd, address_word cia, unsigned int instruction));
 672 #define DecodeCoproc(instruction) decode_coproc(sd, cia, (instruction))
 673
 674
 675
 676 /* Memory accesses */
 677
 678 /* The following are generic to all versions of the MIPS architecture
 679    to date: */
 680
 681 /* Memory Access Types (for CCA): */
 682 #define Uncached                (0)
 683 #define CachedNoncoherent       (1)
 684 #define CachedCoherent          (2)
 685 #define Cached                  (3)
 686
 687 #define isINSTRUCTION   (1 == 0) /* FALSE */
 688 #define isDATA          (1 == 1) /* TRUE */
 689 #define isLOAD          (1 == 0) /* FALSE */
 690 #define isSTORE         (1 == 1) /* TRUE */
 691 #define isREAL          (1 == 0) /* FALSE */
 692 #define isRAW           (1 == 1) /* TRUE */
 693 /* The parameter HOST (isTARGET / isHOST) is ignored */
 694 #define isTARGET        (1 == 0) /* FALSE */
 695 /* #define isHOST          (1 == 1) TRUE */
 696
 697 /* The "AccessLength" specifications for Loads and Stores. NOTE: This
 698    is the number of bytes minus 1. */
 699 #define AccessLength_BYTE       (0)
 700 #define AccessLength_HALFWORD   (1)
 701 #define AccessLength_TRIPLEBYTE (2)
 702 #define AccessLength_WORD       (3)
 703 #define AccessLength_QUINTIBYTE (4)
 704 #define AccessLength_SEXTIBYTE  (5)
 705 #define AccessLength_SEPTIBYTE  (6)
 706 #define AccessLength_DOUBLEWORD (7)
 707 #define AccessLength_QUADWORD   (15)
 708
 709 int address_translation PARAMS ((SIM_DESC sd, address_word cia, address_word vAddr, int IorD, int LorS, address_word *pAddr, int *CCA, int raw));
 710 #define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \
 711 address_translation(sd,cia,vAddr,IorD,LorS,pAddr,CCA,raw)
 712
 713 void load_memory PARAMS ((SIM_DESC sd, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, int AccessLength, address_word pAddr, address_word vAddr, int IorD));
 714 #define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \
 715 load_memory(sd,cia,memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD)
 716
 717 void store_memory PARAMS ((SIM_DESC sd, address_word cia, int CCA, int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr));
 718 #define StoreMemory(CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \
 719 store_memory(sd,cia,CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr)
 720
 721 void cache_op PARAMS ((SIM_DESC sd, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction));
 722 #define CacheOp(op,pAddr,vAddr,instruction) cache_op(sd,cia,op,pAddr,vAddr,instruction)
 723
 724 void sync_operation PARAMS ((SIM_DESC sd, address_word cia, int stype));
 725 #define SyncOperation(stype) sync_operation (sd, cia, (stype))
 726
 727 void prefetch PARAMS ((SIM_DESC sd, address_word cia, int CCA, address_word pAddr, address_word vAddr, int DATA, int hint));
 728 #define Prefetch(CCA,pAddr,vAddr,DATA,hint) prefetch(sd,cia,CCA,pAddr,vAddr,DATA,hint)
 729
 730 unsigned32 ifetch32 PARAMS ((SIM_DESC sd, address_word cia, address_word vaddr));
 731 #define IMEM(CIA) ifetch32 (SD, (CIA), (CIA))
 732
 733 void dotrace PARAMS ((SIM_DESC sd, FILE *tracefh, int type, SIM_ADDR address, int width, char *comment, ...));
 734 FILE *tracefh;
 735
 736 #endif