sim/mips/sim-main.h

   1 /* MIPS Simulator definition.
   2    Copyright (C) 1997, 1998 Free Software Foundation, Inc.
   3    Contributed by Cygnus Support.
   4
   5 This file is part of GDB, the GNU debugger.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 2, or (at your option)
  10 any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License along
  18 with this program; if not, write to the Free Software Foundation, Inc.,
  19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  20
  21 #ifndef SIM_MAIN_H
  22 #define SIM_MAIN_H
  23
  24 /* This simulator doesn't cache the Current Instruction Address */
  25 /* #define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA) */
  26 /* #define SIM_ENGINE_RESUME_HOOK(SD, LAST_CPU, CIA) */
  27
  28 #define SIM_HAVE_BIENDIAN
  29
  30
  31 /* hobble some common features for moment */
  32 #define WITH_WATCHPOINTS 1
  33 #define WITH_MODULO_MEMORY 1
  34
  35
  36 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
  37 mips_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR))
  38
  39 #include "sim-basics.h"
  40
  41 typedef address_word sim_cia;
  42
  43 #include "sim-base.h"
  44
  45
  46 /* Deprecated macros and types for manipulating 64bit values.  Use
  47    ../common/sim-bits.h and ../common/sim-endian.h macros instead. */
  48
  49 typedef signed64 word64;
  50 typedef unsigned64 uword64;
  51
  52 #define WORD64LO(t)     (unsigned int)((t)&0xFFFFFFFF)
  53 #define WORD64HI(t)     (unsigned int)(((uword64)(t))>>32)
  54 #define SET64LO(t)      (((uword64)(t))&0xFFFFFFFF)
  55 #define SET64HI(t)      (((uword64)(t))<<32)
  56 #define WORD64(h,l)     ((word64)((SET64HI(h)|SET64LO(l))))
  57 #define UWORD64(h,l)     (SET64HI(h)|SET64LO(l))
  58
  59 /* Check if a value will fit within a halfword: */
  60 #define NOTHALFWORDVALUE(v) ((((((uword64)(v)>>16) == 0) && !((v) & ((unsigned)1 << 15))) || (((((uword64)(v)>>32) == 0xFFFFFFFF) && ((((uword64)(v)>>16) & 0xFFFF) == 0xFFFF)) && ((v) & ((unsigned)1 << 15)))) ? (1 == 0) : (1 == 1))
  61
  62
  63
  64 /* Floating-point operations: */
  65
  66 #include "sim-fpu.h"
  67 #include "cp1.h"
  68
  69 /* FPU registers must be one of the following types. All other values
  70    are reserved (and undefined). */
  71 typedef enum {
  72  fmt_single  = 0,
  73  fmt_double  = 1,
  74  fmt_word    = 4,
  75  fmt_long    = 5,
  76  /* The following are well outside the normal acceptable format
  77     range, and are used in the register status vector. */
  78  fmt_unknown       = 0x10000000,
  79  fmt_uninterpreted = 0x20000000,
  80  fmt_uninterpreted_32 = 0x40000000,
  81  fmt_uninterpreted_64 = 0x80000000U,
  82 } FP_formats;
  83
  84 /* This should be the COC1 value at the start of the preceding
  85    instruction: */
  86 #define PREVCOC1() ((STATE & simPCOC1) ? 1 : 0)
  87
  88 #ifdef TARGET_ENABLE_FR
  89 /* FIXME: this should be enabled for all targets, but needs testing first. */
  90 #define SizeFGR() (((WITH_TARGET_FLOATING_POINT_BITSIZE) == 64) \
  91    ? ((SR & status_FR) ? 64 : 32) \
  92    : (WITH_TARGET_FLOATING_POINT_BITSIZE))
  93 #else
  94 #define SizeFGR() (WITH_TARGET_FLOATING_POINT_BITSIZE)
  95 #endif
  96
  97
  98
  99
 100
 101 /* HI/LO register accesses */
 102
 103 /* For some MIPS targets, the HI/LO registers have certain timing
 104    restrictions in that, for instance, a read of a HI register must be
 105    separated by at least three instructions from a preceeding read.
 106
 107    The struct below is used to record the last access by each of A MT,
 108    MF or other OP instruction to a HI/LO register.  See mips.igen for
 109    more details. */
 110
 111 typedef struct _hilo_access {
 112   signed64 timestamp;
 113   address_word cia;
 114 } hilo_access;
 115
 116 typedef struct _hilo_history {
 117   hilo_access mt;
 118   hilo_access mf;
 119   hilo_access op;
 120 } hilo_history;
 121
 122
 123
 124
 125 /* Integer ALU operations: */
 126
 127 #include "sim-alu.h"
 128
 129 #define ALU32_END(ANS) \
 130   if (ALU32_HAD_OVERFLOW) \
 131     SignalExceptionIntegerOverflow (); \
 132   (ANS) = (signed32) ALU32_OVERFLOW_RESULT
 133
 134
 135 #define ALU64_END(ANS) \
 136   if (ALU64_HAD_OVERFLOW) \
 137     SignalExceptionIntegerOverflow (); \
 138   (ANS) = ALU64_OVERFLOW_RESULT;
 139
 140
 141
 142
 143
 144 /* The following is probably not used for MIPS IV onwards: */
 145 /* Slots for delayed register updates. For the moment we just have a
 146    fixed number of slots (rather than a more generic, dynamic
 147    system). This keeps the simulator fast. However, we only allow
 148    for the register update to be delayed for a single instruction
 149    cycle. */
 150 #define PSLOTS (8) /* Maximum number of instruction cycles */
 151
 152 typedef struct _pending_write_queue {
 153   int in;
 154   int out;
 155   int total;
 156   int slot_delay[PSLOTS];
 157   int slot_size[PSLOTS];
 158   int slot_bit[PSLOTS];
 159   void *slot_dest[PSLOTS];
 160   unsigned64 slot_value[PSLOTS];
 161 } pending_write_queue;
 162
 163 #ifndef PENDING_TRACE
 164 #define PENDING_TRACE 0
 165 #endif
 166 #define PENDING_IN ((CPU)->pending.in)
 167 #define PENDING_OUT ((CPU)->pending.out)
 168 #define PENDING_TOTAL ((CPU)->pending.total)
 169 #define PENDING_SLOT_SIZE ((CPU)->pending.slot_size)
 170 #define PENDING_SLOT_BIT ((CPU)->pending.slot_bit)
 171 #define PENDING_SLOT_DELAY ((CPU)->pending.slot_delay)
 172 #define PENDING_SLOT_DEST ((CPU)->pending.slot_dest)
 173 #define PENDING_SLOT_VALUE ((CPU)->pending.slot_value)
 174
 175 /* Invalidate the pending write queue, all pending writes are
 176    discarded. */
 177
 178 #define PENDING_INVALIDATE() \
 179 memset (&(CPU)->pending, 0, sizeof ((CPU)->pending))
 180
 181 /* Schedule a write to DEST for N cycles time.  For 64 bit
 182    destinations, schedule two writes.  For floating point registers,
 183    the caller should schedule a write to both the dest register and
 184    the FPR_STATE register.  When BIT is non-negative, only BIT of DEST
 185    is updated. */
 186
 187 #define PENDING_SCHED(DEST,VAL,DELAY,BIT)                               \
 188   do {                                                                  \
 189     if (PENDING_SLOT_DEST[PENDING_IN] != NULL)                          \
 190       sim_engine_abort (SD, CPU, cia,                                   \
 191                         "PENDING_SCHED - buffer overflow\n");           \
 192     if (PENDING_TRACE)                                                  \
 193       sim_io_eprintf (SD, "PENDING_SCHED - 0x%lx - dest 0x%lx, val 0x%lx, bit %d, size %d, pending_in %d, pending_out %d, pending_total %d\n",                  \
 194                       (unsigned long) cia, (unsigned long) &(DEST),     \
 195                       (unsigned long) (VAL), (BIT), (int) sizeof (DEST),\
 196                       PENDING_IN, PENDING_OUT, PENDING_TOTAL);          \
 197     PENDING_SLOT_DELAY[PENDING_IN] = (DELAY) + 1;                       \
 198     PENDING_SLOT_DEST[PENDING_IN] = &(DEST);                            \
 199     PENDING_SLOT_VALUE[PENDING_IN] = (VAL);                             \
 200     PENDING_SLOT_SIZE[PENDING_IN] = sizeof (DEST);                      \
 201     PENDING_SLOT_BIT[PENDING_IN] = (BIT);                               \
 202     PENDING_IN = (PENDING_IN + 1) % PSLOTS;                             \
 203     PENDING_TOTAL += 1;                                                 \
 204   } while (0)
 205
 206 #define PENDING_WRITE(DEST,VAL,DELAY) PENDING_SCHED(DEST,VAL,DELAY,-1)
 207 #define PENDING_BIT(DEST,VAL,DELAY,BIT) PENDING_SCHED(DEST,VAL,DELAY,BIT)
 208
 209 #define PENDING_TICK() pending_tick (SD, CPU, cia)
 210
 211 #define PENDING_FLUSH() abort () /* think about this one */
 212 #define PENDING_FP() abort () /* think about this one */
 213
 214 /* For backward compatibility */
 215 #define PENDING_FILL(R,VAL)                                             \
 216 do {                                                                    \
 217   if ((R) >= FGR_BASE && (R) < FGR_BASE + NR_FGR)                       \
 218     {                                                                   \
 219       PENDING_SCHED(FGR[(R) - FGR_BASE], VAL, 1, -1);                   \
 220       PENDING_SCHED(FPR_STATE[(R) - FGR_BASE], fmt_uninterpreted, 1, -1); \
 221     }                                                                   \
 222   else                                                                  \
 223     PENDING_SCHED(GPR[(R)], VAL, 1, -1);                                \
 224 } while (0)
 225
 226
 227 enum float_operation
 228   {
 229     FLOP_ADD,    FLOP_SUB,    FLOP_MUL,    FLOP_MADD,
 230     FLOP_MSUB,   FLOP_MAX=10, FLOP_MIN,    FLOP_ABS,
 231     FLOP_ITOF0=14, FLOP_FTOI0=18, FLOP_NEG=23
 232   };
 233
 234
 235 /* The internal representation of an MDMX accumulator.
 236    Note that 24 and 48 bit accumulator elements are represented in
 237    32 or 64 bits.  Since the accumulators are 2's complement with
 238    overflow suppressed, high-order bits can be ignored in most contexts.  */
 239
 240 typedef signed32 signed24;
 241 typedef signed64 signed48;
 242
 243 typedef union {
 244   signed24  ob[8];
 245   signed48  qh[4];
 246 } MDMX_accumulator;
 247
 248
 249 /* Conventional system arguments.  */
 250 #define SIM_STATE  sim_cpu *cpu, address_word cia
 251 #define SIM_ARGS   CPU, cia
 252
 253 struct _sim_cpu {
 254
 255
 256   /* The following are internal simulator state variables: */
 257 #define CIA_GET(CPU) ((CPU)->registers[PCIDX] + 0)
 258 #define CIA_SET(CPU,CIA) ((CPU)->registers[PCIDX] = (CIA))
 259   address_word dspc;  /* delay-slot PC */
 260 #define DSPC ((CPU)->dspc)
 261
 262 #define DELAY_SLOT(TARGET) NIA = delayslot32 (SD_, (TARGET))
 263 #define NULLIFY_NEXT_INSTRUCTION() NIA = nullify_next_insn32 (SD_)
 264
 265
 266   /* State of the simulator */
 267   unsigned int state;
 268   unsigned int dsstate;
 269 #define STATE ((CPU)->state)
 270 #define DSSTATE ((CPU)->dsstate)
 271
 272 /* Flags in the "state" variable: */
 273 #define simHALTEX       (1 << 2)  /* 0 = run; 1 = halt on exception */
 274 #define simHALTIN       (1 << 3)  /* 0 = run; 1 = halt on interrupt */
 275 #define simTRACE        (1 << 8)  /* 0 = do nothing; 1 = trace address activity */
 276 #define simPCOC0        (1 << 17) /* COC[1] from current */
 277 #define simPCOC1        (1 << 18) /* COC[1] from previous */
 278 #define simDELAYSLOT    (1 << 24) /* 0 = do nothing; 1 = delay slot entry exists */
 279 #define simSKIPNEXT     (1 << 25) /* 0 = do nothing; 1 = skip instruction */
 280 #define simSIGINT       (1 << 28)  /* 0 = do nothing; 1 = SIGINT has occured */
 281 #define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */
 282
 283 #ifndef ENGINE_ISSUE_PREFIX_HOOK
 284 #define ENGINE_ISSUE_PREFIX_HOOK() \
 285   { \
 286     /* Perform any pending writes */ \
 287     PENDING_TICK(); \
 288     /* Set previous flag, depending on current: */ \
 289     if (STATE & simPCOC0) \
 290      STATE |= simPCOC1; \
 291     else \
 292      STATE &= ~simPCOC1; \
 293     /* and update the current value: */ \
 294     if (GETFCC(0)) \
 295      STATE |= simPCOC0; \
 296     else \
 297      STATE &= ~simPCOC0; \
 298   }
 299 #endif /* ENGINE_ISSUE_PREFIX_HOOK */
 300
 301
 302 /* This is nasty, since we have to rely on matching the register
 303    numbers used by GDB. Unfortunately, depending on the MIPS target
 304    GDB uses different register numbers. We cannot just include the
 305    relevant "gdb/tm.h" link, since GDB may not be configured before
 306    the sim world, and also the GDB header file requires too much other
 307    state. */
 308
 309 #ifndef TM_MIPS_H
 310 #define LAST_EMBED_REGNUM (89)
 311 #define NUM_REGS (LAST_EMBED_REGNUM + 1)
 312
 313 #define FP0_REGNUM 38           /* Floating point register 0 (single float) */
 314 #define FCRCS_REGNUM 70         /* FP control/status */
 315 #define FCRIR_REGNUM 71         /* FP implementation/revision */
 316 #endif
 317
 318
 319 /* To keep this default simulator simple, and fast, we use a direct
 320    vector of registers. The internal simulator engine then uses
 321    manifests to access the correct slot. */
 322
 323   unsigned_word registers[LAST_EMBED_REGNUM + 1];
 324
 325   int register_widths[NUM_REGS];
 326 #define REGISTERS       ((CPU)->registers)
 327
 328 #define GPR     (&REGISTERS[0])
 329 #define GPR_SET(N,VAL) (REGISTERS[(N)] = (VAL))
 330
 331 #define LO      (REGISTERS[33])
 332 #define HI      (REGISTERS[34])
 333 #define PCIDX   37
 334 #define PC      (REGISTERS[PCIDX])
 335 #define CAUSE   (REGISTERS[36])
 336 #define SRIDX   (32)
 337 #define SR      (REGISTERS[SRIDX])      /* CPU status register */
 338 #define FCR0IDX  (71)
 339 #define FCR0    (REGISTERS[FCR0IDX])    /* really a 32bit register */
 340 #define FCR31IDX (70)
 341 #define FCR31   (REGISTERS[FCR31IDX])   /* really a 32bit register */
 342 #define FCSR    (FCR31)
 343 #define Debug   (REGISTERS[86])
 344 #define DEPC    (REGISTERS[87])
 345 #define EPC     (REGISTERS[88])
 346
 347   /* All internal state modified by signal_exception() that may need to be
 348      rolled back for passing moment-of-exception image back to gdb. */
 349   unsigned_word exc_trigger_registers[LAST_EMBED_REGNUM + 1];
 350   unsigned_word exc_suspend_registers[LAST_EMBED_REGNUM + 1];
 351   int exc_suspended;
 352
 353 #define SIM_CPU_EXCEPTION_TRIGGER(SD,CPU,CIA) mips_cpu_exception_trigger(SD,CPU,CIA)
 354 #define SIM_CPU_EXCEPTION_SUSPEND(SD,CPU,EXC) mips_cpu_exception_suspend(SD,CPU,EXC)
 355 #define SIM_CPU_EXCEPTION_RESUME(SD,CPU,EXC) mips_cpu_exception_resume(SD,CPU,EXC)
 356
 357   unsigned_word c0_config_reg;
 358 #define C0_CONFIG ((CPU)->c0_config_reg)
 359
 360 /* The following are pseudonyms for standard registers */
 361 #define ZERO    (REGISTERS[0])
 362 #define V0      (REGISTERS[2])
 363 #define A0      (REGISTERS[4])
 364 #define A1      (REGISTERS[5])
 365 #define A2      (REGISTERS[6])
 366 #define A3      (REGISTERS[7])
 367 #define T8IDX   24
 368 #define T8      (REGISTERS[T8IDX])
 369 #define SPIDX   29
 370 #define SP      (REGISTERS[SPIDX])
 371 #define RAIDX   31
 372 #define RA      (REGISTERS[RAIDX])
 373
 374   /* While space is allocated in the main registers arrray for some of
 375      the COP0 registers, that space isn't sufficient.  Unknown COP0
 376      registers overflow into the array below */
 377
 378 #define NR_COP0_GPR     32
 379   unsigned_word cop0_gpr[NR_COP0_GPR];
 380 #define COP0_GPR        ((CPU)->cop0_gpr)
 381 #define COP0_BADVADDR ((unsigned32)(COP0_GPR[8]))
 382
 383   /* While space is allocated for the floating point registers in the
 384      main registers array, they are stored separatly.  This is because
 385      their size may not necessarily match the size of either the
 386      general-purpose or system specific registers.  */
 387 #define NR_FGR    (32)
 388 #define FGR_BASE  FP0_REGNUM
 389   fp_word fgr[NR_FGR];
 390 #define FGR       ((CPU)->fgr)
 391
 392   /* Keep the current format state for each register: */
 393   FP_formats fpr_state[32];
 394 #define FPR_STATE ((CPU)->fpr_state)
 395
 396   pending_write_queue pending;
 397
 398   /* The MDMX accumulator (used only for MDMX ASE).  */
 399   MDMX_accumulator acc;
 400 #define ACC             ((CPU)->acc)
 401
 402   /* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic
 403      read-write instructions. It is set when a linked load occurs. It
 404      is tested and cleared by the conditional store. It is cleared
 405      (during other CPU operations) when a store to the location would
 406      no longer be atomic. In particular, it is cleared by exception
 407      return instructions. */
 408   int llbit;
 409 #define LLBIT ((CPU)->llbit)
 410
 411
 412 /* The HIHISTORY and LOHISTORY timestamps are used to ensure that
 413    corruptions caused by using the HI or LO register too close to a
 414    following operation is spotted. See mips.igen for more details. */
 415
 416   hilo_history hi_history;
 417 #define HIHISTORY (&(CPU)->hi_history)
 418   hilo_history lo_history;
 419 #define LOHISTORY (&(CPU)->lo_history)
 420
 421 #define check_branch_bug()
 422 #define mark_branch_bug(TARGET)
 423
 424
 425
 426   sim_cpu_base base;
 427 };
 428
 429
 430 /* MIPS specific simulator watch config */
 431
 432 void watch_options_install PARAMS ((SIM_DESC sd));
 433
 434 struct swatch {
 435   sim_event *pc;
 436   sim_event *clock;
 437   sim_event *cycles;
 438 };
 439
 440
 441 /* FIXME: At present much of the simulator is still static */
 442 struct sim_state {
 443
 444   struct swatch watch;
 445
 446   sim_cpu cpu[MAX_NR_PROCESSORS];
 447 #if (WITH_SMP)
 448 #define STATE_CPU(sd,n) (&(sd)->cpu[n])
 449 #else
 450 #define STATE_CPU(sd,n) (&(sd)->cpu[0])
 451 #endif
 452
 453
 454   sim_state_base base;
 455 };
 456
 457
 458
 459 /* Status information: */
 460
 461 /* TODO : these should be the bitmasks for these bits within the
 462    status register. At the moment the following are VR4300
 463    bit-positions: */
 464 #define status_KSU_mask  (0x18)         /* mask for KSU bits */
 465 #define status_KSU_shift (3)            /* shift for field */
 466 #define ksu_kernel       (0x0)
 467 #define ksu_supervisor   (0x1)
 468 #define ksu_user         (0x2)
 469 #define ksu_unknown      (0x3)
 470
 471 #define SR_KSU           ((SR & status_KSU_mask) >> status_KSU_shift)
 472
 473 #define status_IE        (1 <<  0)      /* Interrupt enable */
 474 #define status_EIE       (1 << 16)      /* Enable Interrupt Enable */
 475 #define status_EXL       (1 <<  1)      /* Exception level */
 476 #define status_RE        (1 << 25)      /* Reverse Endian in user mode */
 477 #define status_FR        (1 << 26)      /* enables MIPS III additional FP registers */
 478 #define status_SR        (1 << 20)      /* soft reset or NMI */
 479 #define status_BEV       (1 << 22)      /* Location of general exception vectors */
 480 #define status_TS        (1 << 21)      /* TLB shutdown has occurred */
 481 #define status_ERL       (1 <<  2)      /* Error level */
 482 #define status_IM7       (1 << 15)      /* Timer Interrupt Mask */
 483 #define status_RP        (1 << 27)      /* Reduced Power mode */
 484
 485 /* Specializations for TX39 family */
 486 #define status_IEc       (1 << 0)       /* Interrupt enable (current) */
 487 #define status_KUc       (1 << 1)       /* Kernel/User mode */
 488 #define status_IEp       (1 << 2)       /* Interrupt enable (previous) */
 489 #define status_KUp       (1 << 3)       /* Kernel/User mode */
 490 #define status_IEo       (1 << 4)       /* Interrupt enable (old) */
 491 #define status_KUo       (1 << 5)       /* Kernel/User mode */
 492 #define status_IM_mask   (0xff)         /* Interrupt mask */
 493 #define status_IM_shift  (8)
 494 #define status_NMI       (1 << 20)      /* NMI */
 495 #define status_NMI       (1 << 20)      /* NMI */
 496
 497 /* Status bits used by MIPS32/MIPS64.  */
 498 #define status_UX        (1 <<  5)      /* 64-bit user addrs */
 499 #define status_SX        (1 <<  6)      /* 64-bit supervisor addrs */
 500 #define status_KX        (1 <<  7)      /* 64-bit kernel addrs */
 501 #define status_TS        (1 << 21)      /* TLB shutdown has occurred */
 502 #define status_PX        (1 << 23)      /* Enable 64 bit operations */
 503 #define status_MX        (1 << 24)      /* Enable MDMX resources */
 504 #define status_CU0       (1 << 28)      /* Coprocessor 0 usable */
 505 #define status_CU1       (1 << 29)      /* Coprocessor 1 usable */
 506 #define status_CU2       (1 << 30)      /* Coprocessor 2 usable */
 507 #define status_CU3       (1 << 31)      /* Coprocessor 3 usable */
 508 /* Bits reserved for implementations:  */
 509 #define status_SBX       (1 << 16)      /* Enable SiByte SB-1 extensions.  */
 510
 511 #define cause_BD ((unsigned)1 << 31)    /* L1 Exception in branch delay slot */
 512 #define cause_BD2         (1 << 30)     /* L2 Exception in branch delay slot */
 513 #define cause_CE_mask     0x30000000    /* Coprocessor exception */
 514 #define cause_CE_shift    28
 515 #define cause_EXC2_mask   0x00070000
 516 #define cause_EXC2_shift  16
 517 #define cause_IP7         (1 << 15)     /* Interrupt pending */
 518 #define cause_SIOP        (1 << 12)     /* SIO pending */
 519 #define cause_IP3         (1 << 11)     /* Int 0 pending */
 520 #define cause_IP2         (1 << 10)     /* Int 1 pending */
 521
 522 #define cause_EXC_mask  (0x1c)          /* Exception code */
 523 #define cause_EXC_shift (2)
 524
 525 #define cause_SW0       (1 << 8)        /* Software interrupt 0 */
 526 #define cause_SW1       (1 << 9)        /* Software interrupt 1 */
 527 #define cause_IP_mask   (0x3f)          /* Interrupt pending field */
 528 #define cause_IP_shift  (10)
 529
 530 #define cause_set_EXC(x)  CAUSE = (CAUSE & ~cause_EXC_mask)  | ((x << cause_EXC_shift)  & cause_EXC_mask)
 531 #define cause_set_EXC2(x) CAUSE = (CAUSE & ~cause_EXC2_mask) | ((x << cause_EXC2_shift) & cause_EXC2_mask)
 532
 533
 534 /* NOTE: We keep the following status flags as bit values (1 for true,
 535    0 for false). This allows them to be used in binary boolean
 536    operations without worrying about what exactly the non-zero true
 537    value is. */
 538
 539 /* UserMode */
 540 #ifdef SUBTARGET_R3900
 541 #define UserMode        ((SR & status_KUc) ? 1 : 0)
 542 #else
 543 #define UserMode        ((((SR & status_KSU_mask) >> status_KSU_shift) == ksu_user) ? 1 : 0)
 544 #endif /* SUBTARGET_R3900 */
 545
 546 /* BigEndianMem */
 547 /* Hardware configuration. Affects endianness of LoadMemory and
 548    StoreMemory and the endianness of Kernel and Supervisor mode
 549    execution. The value is 0 for little-endian; 1 for big-endian. */
 550 #define BigEndianMem    (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
 551 /*(state & simBE) ? 1 : 0)*/
 552
 553 /* ReverseEndian */
 554 /* This mode is selected if in User mode with the RE bit being set in
 555    SR (Status Register). It reverses the endianness of load and store
 556    instructions. */
 557 #define ReverseEndian   (((SR & status_RE) && UserMode) ? 1 : 0)
 558
 559 /* BigEndianCPU */
 560 /* The endianness for load and store instructions (0=little;1=big). In
 561    User mode this endianness may be switched by setting the state_RE
 562    bit in the SR register. Thus, BigEndianCPU may be computed as
 563    (BigEndianMem EOR ReverseEndian). */
 564 #define BigEndianCPU    (BigEndianMem ^ ReverseEndian) /* Already bits */
 565
 566
 567
 568 /* Exceptions: */
 569
 570 /* NOTE: These numbers depend on the processor architecture being
 571    simulated: */
 572 enum ExceptionCause {
 573   Interrupt               = 0,
 574   TLBModification         = 1,
 575   TLBLoad                 = 2,
 576   TLBStore                = 3,
 577   AddressLoad             = 4,
 578   AddressStore            = 5,
 579   InstructionFetch        = 6,
 580   DataReference           = 7,
 581   SystemCall              = 8,
 582   BreakPoint              = 9,
 583   ReservedInstruction     = 10,
 584   CoProcessorUnusable     = 11,
 585   IntegerOverflow         = 12,    /* Arithmetic overflow (IDT monitor raises SIGFPE) */
 586   Trap                    = 13,
 587   FPE                     = 15,
 588   DebugBreakPoint         = 16,    /* Impl. dep. in MIPS32/MIPS64.  */
 589   MDMX                    = 22,
 590   Watch                   = 23,
 591   MCheck                  = 24,
 592   CacheErr                = 30,
 593   NMIReset                = 31,    /* Reserved in MIPS32/MIPS64.  */
 594
 595
 596 /* The following exception code is actually private to the simulator
 597    world. It is *NOT* a processor feature, and is used to signal
 598    run-time errors in the simulator. */
 599   SimulatorFault          = 0xFFFFFFFF
 600 };
 601
 602 #define TLB_REFILL  (0)
 603 #define TLB_INVALID (1)
 604
 605
 606 /* The following break instructions are reserved for use by the
 607    simulator.  The first is used to halt the simulation.  The second
 608    is used by gdb for break-points.  NOTE: Care must be taken, since
 609    this value may be used in later revisions of the MIPS ISA. */
 610 #define HALT_INSTRUCTION_MASK   (0x03FFFFC0)
 611
 612 #define HALT_INSTRUCTION        (0x03ff000d)
 613 #define HALT_INSTRUCTION2       (0x0000ffcd)
 614
 615
 616 #define BREAKPOINT_INSTRUCTION  (0x0005000d)
 617 #define BREAKPOINT_INSTRUCTION2 (0x0000014d)
 618
 619
 620
 621 void interrupt_event (SIM_DESC sd, void *data);
 622
 623 void signal_exception (SIM_DESC sd, sim_cpu *cpu, address_word cia, int exception, ...);
 624 #define SignalException(exc,instruction)     signal_exception (SD, CPU, cia, (exc), (instruction))
 625 #define SignalExceptionInterrupt(level)      signal_exception (SD, CPU, cia, Interrupt, level)
 626 #define SignalExceptionInstructionFetch()    signal_exception (SD, CPU, cia, InstructionFetch)
 627 #define SignalExceptionAddressStore()        signal_exception (SD, CPU, cia, AddressStore)
 628 #define SignalExceptionAddressLoad()         signal_exception (SD, CPU, cia, AddressLoad)
 629 #define SignalExceptionDataReference()       signal_exception (SD, CPU, cia, DataReference)
 630 #define SignalExceptionSimulatorFault(buf)   signal_exception (SD, CPU, cia, SimulatorFault, buf)
 631 #define SignalExceptionFPE()                 signal_exception (SD, CPU, cia, FPE)
 632 #define SignalExceptionIntegerOverflow()     signal_exception (SD, CPU, cia, IntegerOverflow)
 633 #define SignalExceptionCoProcessorUnusable(cop) signal_exception (SD, CPU, cia, CoProcessorUnusable)
 634 #define SignalExceptionNMIReset()            signal_exception (SD, CPU, cia, NMIReset)
 635 #define SignalExceptionTLBRefillStore()      signal_exception (SD, CPU, cia, TLBStore, TLB_REFILL)
 636 #define SignalExceptionTLBRefillLoad()       signal_exception (SD, CPU, cia, TLBLoad, TLB_REFILL)
 637 #define SignalExceptionTLBInvalidStore()     signal_exception (SD, CPU, cia, TLBStore, TLB_INVALID)
 638 #define SignalExceptionTLBInvalidLoad()      signal_exception (SD, CPU, cia, TLBLoad, TLB_INVALID)
 639 #define SignalExceptionTLBModification()     signal_exception (SD, CPU, cia, TLBModification)
 640 #define SignalExceptionMDMX()                signal_exception (SD, CPU, cia, MDMX)
 641 #define SignalExceptionWatch()               signal_exception (SD, CPU, cia, Watch)
 642 #define SignalExceptionMCheck()              signal_exception (SD, CPU, cia, MCheck)
 643 #define SignalExceptionCacheErr()            signal_exception (SD, CPU, cia, CacheErr)
 644
 645 /* Co-processor accesses */
 646
 647 /* XXX FIXME: For now, assume that FPU (cp1) is always usable.  */
 648 #define COP_Usable(coproc_num)          (coproc_num == 1)
 649
 650 void cop_lw  PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, unsigned int memword));
 651 void cop_ld  PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, uword64 memword));
 652 unsigned int cop_sw PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg));
 653 uword64 cop_sd PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg));
 654
 655 #define COP_LW(coproc_num,coproc_reg,memword) \
 656 cop_lw (SD, CPU, cia, coproc_num, coproc_reg, memword)
 657 #define COP_LD(coproc_num,coproc_reg,memword) \
 658 cop_ld (SD, CPU, cia, coproc_num, coproc_reg, memword)
 659 #define COP_SW(coproc_num,coproc_reg) \
 660 cop_sw (SD, CPU, cia, coproc_num, coproc_reg)
 661 #define COP_SD(coproc_num,coproc_reg) \
 662 cop_sd (SD, CPU, cia, coproc_num, coproc_reg)
 663
 664
 665 void decode_coproc PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int instruction));
 666 #define DecodeCoproc(instruction) \
 667 decode_coproc (SD, CPU, cia, (instruction))
 668
 669 int sim_monitor (SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int arg);
 670
 671
 672 /* FPR access.  */
 673 unsigned64 value_fpr (SIM_STATE, int fpr, FP_formats);
 674 #define ValueFPR(FPR,FMT) value_fpr (SIM_ARGS, (FPR), (FMT))
 675 void store_fpr (SIM_STATE, int fpr, FP_formats fmt, unsigned64 value);
 676 #define StoreFPR(FPR,FMT,VALUE) store_fpr (SIM_ARGS, (FPR), (FMT), (VALUE))
 677
 678
 679 /* FCR access.  */
 680 unsigned_word value_fcr (SIM_STATE, int fcr);
 681 #define ValueFCR(FCR) value_fcr (SIM_ARGS, (FCR))
 682 void store_fcr (SIM_STATE, int fcr, unsigned_word value);
 683 #define StoreFCR(FCR,VALUE) store_fcr (SIM_ARGS, (FCR), (VALUE))
 684 void test_fcsr (SIM_STATE);
 685 #define TestFCSR() test_fcsr (SIM_ARGS)
 686
 687
 688 /* FPU operations.  */
 689 void fp_cmp (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt, int abs, int cond, int cc);
 690 #define Compare(op1,op2,fmt,cond,cc) fp_cmp(SIM_ARGS, op1, op2, fmt, 0, cond, cc)
 691 unsigned64 fp_abs (SIM_STATE, unsigned64 op, FP_formats fmt);
 692 #define AbsoluteValue(op,fmt) fp_abs(SIM_ARGS, op, fmt)
 693 unsigned64 fp_neg (SIM_STATE, unsigned64 op, FP_formats fmt);
 694 #define Negate(op,fmt) fp_neg(SIM_ARGS, op, fmt)
 695 unsigned64 fp_add (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
 696 #define Add(op1,op2,fmt) fp_add(SIM_ARGS, op1, op2, fmt)
 697 unsigned64 fp_sub (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
 698 #define Sub(op1,op2,fmt) fp_sub(SIM_ARGS, op1, op2, fmt)
 699 unsigned64 fp_mul (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
 700 #define Multiply(op1,op2,fmt) fp_mul(SIM_ARGS, op1, op2, fmt)
 701 unsigned64 fp_div (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
 702 #define Divide(op1,op2,fmt) fp_div(SIM_ARGS, op1, op2, fmt)
 703 unsigned64 fp_recip (SIM_STATE, unsigned64 op, FP_formats fmt);
 704 #define Recip(op,fmt) fp_recip(SIM_ARGS, op, fmt)
 705 unsigned64 fp_sqrt (SIM_STATE, unsigned64 op, FP_formats fmt);
 706 #define SquareRoot(op,fmt) fp_sqrt(SIM_ARGS, op, fmt)
 707 unsigned64 convert (SIM_STATE, int rm, unsigned64 op, FP_formats from, FP_formats to);
 708 #define Convert(rm,op,from,to) convert (SIM_ARGS, rm, op, from, to)
 709
 710
 711 /* MDMX access.  */
 712
 713 typedef unsigned int MX_fmtsel;   /* MDMX format select field (5 bits).  */
 714 #define ob_fmtsel(sel) (((sel)<<1)|0x0)
 715 #define qh_fmtsel(sel) (((sel)<<2)|0x1)
 716
 717 #define fmt_mdmx fmt_uninterpreted
 718
 719 #define MX_VECT_AND  (0)
 720 #define MX_VECT_NOR  (1)
 721 #define MX_VECT_OR   (2)
 722 #define MX_VECT_XOR  (3)
 723 #define MX_VECT_SLL  (4)
 724 #define MX_VECT_SRL  (5)
 725 #define MX_VECT_ADD  (6)
 726 #define MX_VECT_SUB  (7)
 727 #define MX_VECT_MIN  (8)
 728 #define MX_VECT_MAX  (9)
 729 #define MX_VECT_MUL  (10)
 730 #define MX_VECT_MSGN (11)
 731 #define MX_VECT_SRA  (12)
 732 #define MX_VECT_ABSD (13)               /* SB-1 only.  */
 733 #define MX_VECT_AVG  (14)               /* SB-1 only.  */
 734
 735 unsigned64 mdmx_cpr_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmtsel);
 736 #define MX_Add(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_ADD, op1, vt, fmtsel)
 737 #define MX_And(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_AND, op1, vt, fmtsel)
 738 #define MX_Max(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MAX, op1, vt, fmtsel)
 739 #define MX_Min(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MIN, op1, vt, fmtsel)
 740 #define MX_Msgn(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MSGN, op1, vt, fmtsel)
 741 #define MX_Mul(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MUL, op1, vt, fmtsel)
 742 #define MX_Nor(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_NOR, op1, vt, fmtsel)
 743 #define MX_Or(op1,vt,fmtsel)  mdmx_cpr_op(SIM_ARGS, MX_VECT_OR,  op1, vt, fmtsel)
 744 #define MX_ShiftLeftLogical(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SLL, op1, vt, fmtsel)
 745 #define MX_ShiftRightArith(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SRA, op1, vt, fmtsel)
 746 #define MX_ShiftRightLogical(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SRL, op1, vt, fmtsel)
 747 #define MX_Sub(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SUB, op1, vt, fmtsel)
 748 #define MX_Xor(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_XOR, op1, vt, fmtsel)
 749 #define MX_AbsDiff(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_ABSD, op1, vt, fmtsel)
 750 #define MX_Avg(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_AVG, op1, vt, fmtsel)
 751
 752 #define MX_C_EQ  0x1
 753 #define MX_C_LT  0x4
 754
 755 void mdmx_cc_op (SIM_STATE, int cond, unsigned64 op1, int vt, MX_fmtsel fmtsel);
 756 #define MX_Comp(op1,cond,vt,fmtsel) mdmx_cc_op(SIM_ARGS, cond, op1, vt, fmtsel)
 757
 758 unsigned64 mdmx_pick_op (SIM_STATE, int tf, unsigned64 op1, int vt, MX_fmtsel fmtsel);
 759 #define MX_Pick(tf,op1,vt,fmtsel) mdmx_pick_op(SIM_ARGS, tf, op1, vt, fmtsel)
 760
 761 #define MX_VECT_ADDA  (0)
 762 #define MX_VECT_ADDL  (1)
 763 #define MX_VECT_MULA  (2)
 764 #define MX_VECT_MULL  (3)
 765 #define MX_VECT_MULS  (4)
 766 #define MX_VECT_MULSL (5)
 767 #define MX_VECT_SUBA  (6)
 768 #define MX_VECT_SUBL  (7)
 769 #define MX_VECT_ABSDA (8)               /* SB-1 only.  */
 770
 771 void mdmx_acc_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmtsel);
 772 #define MX_AddA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ADDA, op1, vt, fmtsel)
 773 #define MX_AddL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ADDL, op1, vt, fmtsel)
 774 #define MX_MulA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULA, op1, vt, fmtsel)
 775 #define MX_MulL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULL, op1, vt, fmtsel)
 776 #define MX_MulS(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULS, op1, vt, fmtsel)
 777 #define MX_MulSL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULSL, op1, vt, fmtsel)
 778 #define MX_SubA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_SUBA, op1, vt, fmtsel)
 779 #define MX_SubL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_SUBL, op1, vt, fmtsel)
 780 #define MX_AbsDiffC(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ABSDA, op1, vt, fmtsel)
 781
 782 #define MX_FMT_OB   (0)
 783 #define MX_FMT_QH   (1)
 784
 785 /* The following codes chosen to indicate the units of shift.  */
 786 #define MX_RAC_L    (0)
 787 #define MX_RAC_M    (1)
 788 #define MX_RAC_H    (2)
 789
 790 unsigned64 mdmx_rac_op (SIM_STATE, int, int);
 791 #define MX_RAC(op,fmt) mdmx_rac_op(SIM_ARGS, op, fmt)
 792
 793 void mdmx_wacl (SIM_STATE, int, unsigned64, unsigned64);
 794 #define MX_WACL(fmt,vs,vt) mdmx_wacl(SIM_ARGS, fmt, vs, vt)
 795 void mdmx_wach (SIM_STATE, int, unsigned64);
 796 #define MX_WACH(fmt,vs) mdmx_wach(SIM_ARGS, fmt, vs)
 797
 798 #define MX_RND_AS   (0)
 799 #define MX_RND_AU   (1)
 800 #define MX_RND_ES   (2)
 801 #define MX_RND_EU   (3)
 802 #define MX_RND_ZS   (4)
 803 #define MX_RND_ZU   (5)
 804
 805 unsigned64 mdmx_round_op (SIM_STATE, int, int, MX_fmtsel);
 806 #define MX_RNAS(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_AS, vt, fmt)
 807 #define MX_RNAU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_AU, vt, fmt)
 808 #define MX_RNES(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ES, vt, fmt)
 809 #define MX_RNEU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_EU, vt, fmt)
 810 #define MX_RZS(vt,fmt)  mdmx_round_op(SIM_ARGS, MX_RND_ZS, vt, fmt)
 811 #define MX_RZU(vt,fmt)  mdmx_round_op(SIM_ARGS, MX_RND_ZU, vt, fmt)
 812
 813 unsigned64 mdmx_shuffle (SIM_STATE, int, unsigned64, unsigned64);
 814 #define MX_SHFL(shop,op1,op2) mdmx_shuffle(SIM_ARGS, shop, op1, op2)
 815
 816
 817
 818 /* Memory accesses */
 819
 820 /* The following are generic to all versions of the MIPS architecture
 821    to date: */
 822
 823 /* Memory Access Types (for CCA): */
 824 #define Uncached                (0)
 825 #define CachedNoncoherent       (1)
 826 #define CachedCoherent          (2)
 827 #define Cached                  (3)
 828
 829 #define isINSTRUCTION   (1 == 0) /* FALSE */
 830 #define isDATA          (1 == 1) /* TRUE */
 831 #define isLOAD          (1 == 0) /* FALSE */
 832 #define isSTORE         (1 == 1) /* TRUE */
 833 #define isREAL          (1 == 0) /* FALSE */
 834 #define isRAW           (1 == 1) /* TRUE */
 835 /* The parameter HOST (isTARGET / isHOST) is ignored */
 836 #define isTARGET        (1 == 0) /* FALSE */
 837 /* #define isHOST          (1 == 1) TRUE */
 838
 839 /* The "AccessLength" specifications for Loads and Stores. NOTE: This
 840    is the number of bytes minus 1. */
 841 #define AccessLength_BYTE       (0)
 842 #define AccessLength_HALFWORD   (1)
 843 #define AccessLength_TRIPLEBYTE (2)
 844 #define AccessLength_WORD       (3)
 845 #define AccessLength_QUINTIBYTE (4)
 846 #define AccessLength_SEXTIBYTE  (5)
 847 #define AccessLength_SEPTIBYTE  (6)
 848 #define AccessLength_DOUBLEWORD (7)
 849 #define AccessLength_QUADWORD   (15)
 850
 851 #define LOADDRMASK (WITH_TARGET_WORD_BITSIZE == 64 \
 852                     ? AccessLength_DOUBLEWORD /*7*/ \
 853                     : AccessLength_WORD /*3*/)
 854 #define PSIZE (WITH_TARGET_ADDRESS_BITSIZE)
 855
 856
 857 INLINE_SIM_MAIN (int) address_translation PARAMS ((SIM_DESC sd, sim_cpu *, address_word cia, address_word vAddr, int IorD, int LorS, address_word *pAddr, int *CCA, int raw));
 858 #define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \
 859 address_translation (SD, CPU, cia, vAddr, IorD, LorS, pAddr, CCA, raw)
 860
 861 INLINE_SIM_MAIN (void) load_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, unsigned int AccessLength, address_word pAddr, address_word vAddr, int IorD));
 862 #define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \
 863 load_memory (SD, CPU, cia, memvalp, memval1p, CCA, AccessLength, pAddr, vAddr, IorD)
 864
 865 INLINE_SIM_MAIN (void) store_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, unsigned int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr));
 866 #define StoreMemory(CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \
 867 store_memory (SD, CPU, cia, CCA, AccessLength, MemElem, MemElem1, pAddr, vAddr)
 868
 869 INLINE_SIM_MAIN (void) cache_op PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction));
 870 #define CacheOp(op,pAddr,vAddr,instruction) \
 871 cache_op (SD, CPU, cia, op, pAddr, vAddr, instruction)
 872
 873 INLINE_SIM_MAIN (void) sync_operation PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int stype));
 874 #define SyncOperation(stype) \
 875 sync_operation (SD, CPU, cia, (stype))
 876
 877 INLINE_SIM_MAIN (void) prefetch PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, address_word pAddr, address_word vAddr, int DATA, int hint));
 878 #define Prefetch(CCA,pAddr,vAddr,DATA,hint) \
 879 prefetch (SD, CPU, cia, CCA, pAddr, vAddr, DATA, hint)
 880
 881 void unpredictable_action (sim_cpu *cpu, address_word cia);
 882 #define NotWordValue(val)       not_word_value (SD_, (val))
 883 #define Unpredictable()         unpredictable (SD_)
 884 #define UnpredictableResult()   /* For now, do nothing.  */
 885
 886 INLINE_SIM_MAIN (unsigned32) ifetch32 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr));
 887 #define IMEM32(CIA) ifetch32 (SD, CPU, (CIA), (CIA))
 888 INLINE_SIM_MAIN (unsigned16) ifetch16 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr));
 889 #define IMEM16(CIA) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1))
 890 #define IMEM16_IMMED(CIA,NR) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1) + 2 * (NR))
 891
 892 void dotrace PARAMS ((SIM_DESC sd, sim_cpu *cpu, FILE *tracefh, int type, SIM_ADDR address, int width, char *comment, ...));
 893 extern FILE *tracefh;
 894
 895 INLINE_SIM_MAIN (void) pending_tick PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia));
 896 extern SIM_CORE_SIGNAL_FN mips_core_signal;
 897
 898 char* pr_addr PARAMS ((SIM_ADDR addr));
 899 char* pr_uword64 PARAMS ((uword64 addr));
 900
 901
 902 #define GPR_CLEAR(N) do { GPR_SET((N),0); } while (0)
 903
 904 void mips_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word pc);
 905 void mips_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception);
 906 void mips_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception);
 907
 908
 909 #if H_REVEALS_MODULE_P (SIM_MAIN_INLINE)
 910 #include "sim-main.c"
 911 #endif
 912
 913 #endif