sim/mips/sky-pke.h

   1 /* Copyright (C) 1998, Cygnus Solutions */
   2
   3 #ifndef H_PKE_H
   4 #define H_PKE_H
   5
   6 #include "sim-main.h"
   7 #include "sky-device.h"
   8
   9
  10
  11 /* External functions */
  12
  13 void pke0_attach(SIM_DESC sd);
  14 void pke0_issue(SIM_DESC sd);
  15 void pke1_attach(SIM_DESC sd);
  16 void pke1_issue(SIM_DESC sd);
  17
  18
  19 /* structs declared below */
  20 struct pke_fifo;
  21 struct fifo_quadword;
  22
  23
  24 /* Quadword data type */
  25
  26 typedef unsigned_4 quadword[4];
  27
  28 /* truncate address to quadword */
  29 #define ADDR_TRUNC_QW(addr) ((addr) & ~0x0f)
  30 /* extract offset in quadword */
  31 #define ADDR_OFFSET_QW(addr) ((addr) & 0x0f)
  32
  33
  34 /* SCEI memory mapping information */
  35
  36 #define PKE0_REGISTER_WINDOW_START 0x10003800
  37 #define PKE1_REGISTER_WINDOW_START 0x10003C00
  38 #define PKE0_FIFO_ADDR             0x10004000
  39 #define PKE1_FIFO_ADDR             0x10005000
  40
  41
  42 /* VU source-addr tracking tables */ /* changed from 1998-01-22 e-mail plans */
  43 #define VU0_MEM0_SRCADDR_START 0x21000000
  44 #define VU0_MEM1_SRCADDR_START 0x21004000
  45 #define VU1_MEM0_SRCADDR_START 0x21008000
  46 #define VU1_MEM1_SRCADDR_START 0x2100C000
  47
  48 #define VU0_CIA (VU0_REGISTER_WINDOW_START + VU_REG_CIA)
  49 #define VU1_CIA (VU1_REGISTER_WINDOW_START + VU_REG_CIA)
  50
  51 /* GPUIF STAT register */
  52 #define GPUIF_REG_STAT_APATH_E 11
  53 #define GPUIF_REG_STAT_APATH_B 10
  54
  55 /* COP2 STAT register */
  56 #define COP2_REG_STAT_ADDR VPU_STAT
  57 #define COP2_REG_STAT_VBS1_E 8
  58 #define COP2_REG_STAT_VBS1_B 8
  59 #define COP2_REG_STAT_VBS0_E 0
  60 #define COP2_REG_STAT_VBS0_B 0
  61
  62
  63 /* Quadword indices of PKE registers.  Actual registers sit at bottom
  64    32 bits of each quadword. */
  65 #define PKE_REG_STAT    0x00
  66 #define PKE_REG_FBRST   0x01
  67 #define PKE_REG_ERR     0x02
  68 #define PKE_REG_MARK    0x03
  69 #define PKE_REG_CYCLE   0x04
  70 #define PKE_REG_MODE    0x05
  71 #define PKE_REG_NUM     0x06
  72 #define PKE_REG_MASK    0x07
  73 #define PKE_REG_CODE    0x08
  74 #define PKE_REG_ITOPS   0x09
  75 #define PKE_REG_BASE    0x0a /* pke1 only */
  76 #define PKE_REG_OFST    0x0b /* pke1 only */
  77 #define PKE_REG_TOPS    0x0c /* pke1 only */
  78 #define PKE_REG_ITOP    0x0d
  79 #define PKE_REG_TOP     0x0e /* pke1 only */
  80 #define PKE_REG_DBF     0x0f /* pke1 only */
  81 #define PKE_REG_R0      0x10 /* R0 .. R3 must be contiguous */
  82 #define PKE_REG_R1      0x11
  83 #define PKE_REG_R2      0x12
  84 #define PKE_REG_R3      0x13
  85 #define PKE_REG_C0      0x14 /* C0 .. C3 must be contiguous */
  86 #define PKE_REG_C1      0x15
  87 #define PKE_REG_C2      0x16
  88 #define PKE_REG_C3      0x17
  89 /* one plus last index */
  90 #define PKE_NUM_REGS    0x18
  91
  92 #define PKE_REGISTER_WINDOW_SIZE  (sizeof(quadword) * PKE_NUM_REGS)
  93
  94
  95
  96 /* PKE commands */
  97
  98 #define PKE_CMD_PKENOP_MASK 0x7F
  99 #define PKE_CMD_PKENOP_BITS 0x00
 100 #define PKE_CMD_STCYCL_MASK 0x7F
 101 #define PKE_CMD_STCYCL_BITS 0x01
 102 #define PKE_CMD_OFFSET_MASK 0x7F
 103 #define PKE_CMD_OFFSET_BITS 0x02
 104 #define PKE_CMD_BASE_MASK 0x7F
 105 #define PKE_CMD_BASE_BITS 0x03
 106 #define PKE_CMD_ITOP_MASK 0x7F
 107 #define PKE_CMD_ITOP_BITS 0x04
 108 #define PKE_CMD_STMOD_MASK 0x7F
 109 #define PKE_CMD_STMOD_BITS 0x05
 110 #define PKE_CMD_MSKPATH3_MASK 0x7F
 111 #define PKE_CMD_MSKPATH3_BITS 0x06
 112 #define PKE_CMD_PKEMARK_MASK 0x7F
 113 #define PKE_CMD_PKEMARK_BITS 0x07
 114 #define PKE_CMD_FLUSHE_MASK 0x7F
 115 #define PKE_CMD_FLUSHE_BITS 0x10
 116 #define PKE_CMD_FLUSH_MASK 0x7F
 117 #define PKE_CMD_FLUSH_BITS 0x11
 118 #define PKE_CMD_FLUSHA_MASK 0x7F
 119 #define PKE_CMD_FLUSHA_BITS 0x13
 120 #define PKE_CMD_PKEMSCAL_MASK 0x7F  /* CAL == "call" */
 121 #define PKE_CMD_PKEMSCAL_BITS 0x14
 122 #define PKE_CMD_PKEMSCNT_MASK 0x7F  /* CNT == "continue" */
 123 #define PKE_CMD_PKEMSCNT_BITS 0x17
 124 #define PKE_CMD_PKEMSCALF_MASK 0x7F /* CALF == "call after flush" */
 125 #define PKE_CMD_PKEMSCALF_BITS 0x15
 126 #define PKE_CMD_STMASK_MASK 0x7F
 127 #define PKE_CMD_STMASK_BITS 0x20
 128 #define PKE_CMD_STROW_MASK 0x7F
 129 #define PKE_CMD_STROW_BITS 0x30
 130 #define PKE_CMD_STCOL_MASK 0x7F
 131 #define PKE_CMD_STCOL_BITS 0x31
 132 #define PKE_CMD_MPG_MASK 0x7F
 133 #define PKE_CMD_MPG_BITS 0x4A
 134 #define PKE_CMD_DIRECT_MASK 0x7F
 135 #define PKE_CMD_DIRECT_BITS 0x50
 136 #define PKE_CMD_DIRECTHL_MASK 0x7F
 137 #define PKE_CMD_DIRECTHL_BITS 0x51
 138 #define PKE_CMD_UNPACK_MASK 0x60
 139 #define PKE_CMD_UNPACK_BITS 0x60
 140
 141 /* test given word for particular PKE command bit pattern */
 142 #define IS_PKE_CMD(word,cmd) (((word) & PKE_CMD_##cmd##_MASK) == PKE_CMD_##cmd##_BITS)
 143
 144
 145 /* register bitmasks: bit numbers for end and beginning of fields */
 146
 147 /* PKE opcode */
 148 #define PKE_OPCODE_I_E 31
 149 #define PKE_OPCODE_I_B 31
 150 #define PKE_OPCODE_CMD_E 30
 151 #define PKE_OPCODE_CMD_B 24
 152 #define PKE_OPCODE_NUM_E 23
 153 #define PKE_OPCODE_NUM_B 16
 154 #define PKE_OPCODE_IMM_E 15
 155 #define PKE_OPCODE_IMM_B 0
 156
 157 /* STAT register */
 158 #define PKE_REG_STAT_FQC_E 28
 159 #define PKE_REG_STAT_FQC_B 24
 160 #define PKE_REG_STAT_FDR_E 23
 161 #define PKE_REG_STAT_FDR_B 23
 162 #define PKE_REG_STAT_ER1_E 13
 163 #define PKE_REG_STAT_ER1_B 13
 164 #define PKE_REG_STAT_ER0_E 12
 165 #define PKE_REG_STAT_ER0_B 12
 166 #define PKE_REG_STAT_INT_E 11
 167 #define PKE_REG_STAT_INT_B 11
 168 #define PKE_REG_STAT_PIS_E 10
 169 #define PKE_REG_STAT_PIS_B 10
 170 #define PKE_REG_STAT_PFS_E 9
 171 #define PKE_REG_STAT_PFS_B 9
 172 #define PKE_REG_STAT_PSS_E 8
 173 #define PKE_REG_STAT_PSS_B 8
 174 #define PKE_REG_STAT_DBF_E 7
 175 #define PKE_REG_STAT_DBF_B 7
 176 #define PKE_REG_STAT_MRK_E 6
 177 #define PKE_REG_STAT_MRK_B 6
 178 #define PKE_REG_STAT_PGW_E 3
 179 #define PKE_REG_STAT_PGW_B 3
 180 #define PKE_REG_STAT_PEW_E 2
 181 #define PKE_REG_STAT_PEW_B 2
 182 #define PKE_REG_STAT_PPS_E 1
 183 #define PKE_REG_STAT_PPS_B 0
 184
 185 #define PKE_REG_STAT_PPS_IDLE 0x00 /* ready to execute next instruction */
 186 #define PKE_REG_STAT_PPS_WAIT 0x01 /* not enough words in FIFO */
 187 #define PKE_REG_STAT_PPS_DECODE 0x02 /* decoding instruction */
 188 #define PKE_REG_STAT_PPS_STALL 0x02 /* alias state for stall (e.g., FLUSHE) */
 189 #define PKE_REG_STAT_PPS_XFER 0x03 /* transferring instruction operands */
 190
 191 /* DBF register */
 192 #define PKE_REG_DBF_DF_E 0
 193 #define PKE_REG_DBF_DF_B 0
 194
 195 /* OFST register */
 196 #define PKE_REG_OFST_OFFSET_E 9
 197 #define PKE_REG_OFST_OFFSET_B 0
 198
 199 /* OFST register */
 200 #define PKE_REG_TOPS_TOPS_E 9
 201 #define PKE_REG_TOPS_TOPS_B 0
 202
 203 /* BASE register */
 204 #define PKE_REG_BASE_BASE_E 9
 205 #define PKE_REG_BASE_BASE_B 0
 206
 207 /* ITOPS register */
 208 #define PKE_REG_ITOPS_ITOPS_E 9
 209 #define PKE_REG_ITOPS_ITOPS_B 0
 210
 211 /* MODE register */
 212 #define PKE_REG_MODE_MDE_E 1
 213 #define PKE_REG_MODE_MDE_B 0
 214
 215 /* NUM register */
 216 #define PKE_REG_NUM_NUM_E 9
 217 #define PKE_REG_NUM_NUM_B 0
 218
 219 /* MARK register */
 220 #define PKE_REG_MARK_MARK_E 15
 221 #define PKE_REG_MARK_MARK_B 0
 222
 223 /* ITOP register */
 224 #define PKE_REG_ITOP_ITOP_E 9
 225 #define PKE_REG_ITOP_ITOP_B 0
 226
 227 /* TOP register */
 228 #define PKE_REG_TOP_TOP_E 9
 229 #define PKE_REG_TOP_TOP_B 0
 230
 231 /* MASK register */
 232 #define PKE_REG_MASK_MASK_E 31
 233 #define PKE_REG_MASK_MASK_B 0
 234
 235 /* CYCLE register */
 236 #define PKE_REG_CYCLE_WL_E 15
 237 #define PKE_REG_CYCLE_WL_B 8
 238 #define PKE_REG_CYCLE_CL_E 7
 239 #define PKE_REG_CYCLE_CL_B 0
 240
 241 /* ERR register */
 242 #define PKE_REG_ERR_ME1_E 2
 243 #define PKE_REG_ERR_ME1_B 2
 244 #define PKE_REG_ERR_ME0_E 1
 245 #define PKE_REG_ERR_ME0_B 1
 246 #define PKE_REG_ERR_MII_E 0
 247 #define PKE_REG_ERR_MII_B 0
 248
 249 /* FBRST command bitfields */
 250 #define PKE_REG_FBRST_STC_E 3
 251 #define PKE_REG_FBRST_STC_B 3
 252 #define PKE_REG_FBRST_STP_E 2
 253 #define PKE_REG_FBRST_STP_B 2
 254 #define PKE_REG_FBRST_FBK_E 1
 255 #define PKE_REG_FBRST_FBK_B 1
 256 #define PKE_REG_FBRST_RST_E 0
 257 #define PKE_REG_FBRST_RST_B 0
 258
 259 /* MSKPATH3 command bitfields */
 260 #define PKE_REG_MSKPATH3_E 15
 261 #define PKE_REG_MSKPATH3_B 15
 262
 263
 264 /* UNPACK opcodes */
 265 #define PKE_UNPACK(vn,vl) ((vn) << 2 | (vl))
 266 #define PKE_UNPACK_S_32  PKE_UNPACK(0, 0)
 267 #define PKE_UNPACK_S_16  PKE_UNPACK(0, 1)
 268 #define PKE_UNPACK_S_8   PKE_UNPACK(0, 2)
 269 #define PKE_UNPACK_V2_32 PKE_UNPACK(1, 0)
 270 #define PKE_UNPACK_V2_16 PKE_UNPACK(1, 1)
 271 #define PKE_UNPACK_V2_8  PKE_UNPACK(1, 2)
 272 #define PKE_UNPACK_V3_32 PKE_UNPACK(2, 0)
 273 #define PKE_UNPACK_V3_16 PKE_UNPACK(2, 1)
 274 #define PKE_UNPACK_V3_8  PKE_UNPACK(2, 2)
 275 #define PKE_UNPACK_V4_32 PKE_UNPACK(3, 0)
 276 #define PKE_UNPACK_V4_16 PKE_UNPACK(3, 1)
 277 #define PKE_UNPACK_V4_8  PKE_UNPACK(3, 2)
 278 #define PKE_UNPACK_V4_5  PKE_UNPACK(3, 3)
 279
 280
 281 /* MASK register sub-field definitions */
 282 #define PKE_MASKREG_INPUT 0
 283 #define PKE_MASKREG_ROW 1
 284 #define PKE_MASKREG_COLUMN 2
 285 #define PKE_MASKREG_NOTHING 3
 286
 287
 288 /* STMOD register field definitions */
 289 #define PKE_MODE_INPUT 0
 290 #define PKE_MODE_ADDROW 1
 291 #define PKE_MODE_ACCROW 2
 292
 293
 294 /* extract a MASK register sub-field for row [0..3] and column [0..3] */
 295 /* MASK register is laid out of 2-bit values in this r-c order */
 296 /* m33 m32 m31 m30 m23 m22 m21 m20 m13 m12 m11 m10 m03 m02 m01 m00 */
 297 #define PKE_MASKREG_GET(me,row,col) \
 298 ((((me)->regs[PKE_REG_MASK][0]) >> (8*(row) + 2*(col))) & 0x03)
 299
 300
 301 /* operations - replace with those in sim-bits.h when convenient */
 302
 303 /* unsigned 32-bit mask of given width */
 304 #define BIT_MASK(width) ((width) == 31 ? 0xffffffff : (((unsigned_4)1) << (width+1)) - 1)
 305 /* e.g.: BIT_MASK(4) = 00011111 */
 306
 307 /* mask between given given bits numbers (MSB) */
 308 #define BIT_MASK_BTW(begin,end) ((BIT_MASK(end) & ~((begin) == 0 ? 0 : BIT_MASK((begin)-1))))
 309 /* e.g.: BIT_MASK_BTW(4,11) = 0000111111110000 */
 310
 311 /* set bitfield value */
 312 #define BIT_MASK_SET(lvalue,begin,end,value) \
 313 do { \
 314   ASSERT((begin) <= (end)); \
 315   (lvalue) &= ~BIT_MASK_BTW((begin),(end)); \
 316   (lvalue) |= ((value) << (begin)) & BIT_MASK_BTW((begin),(end)); \
 317 } while(0)
 318
 319 /* get bitfield value */
 320 #define BIT_MASK_GET(rvalue,begin,end) \
 321   (((rvalue) & BIT_MASK_BTW(begin,end)) >> (begin))
 322 /* e.g., BIT_MASK_GET(0000111100001111, 2, 8) = 0000000100001100 */
 323
 324 /* These ugly macro hacks allow succinct bitfield accesses */
 325 /* set a bitfield in a register by "name" */
 326 #define PKE_REG_MASK_SET(me,reg,flag,value) \
 327      do { \
 328        unsigned_4 old = BIT_MASK_GET(((me)->regs[PKE_REG_##reg][0]), \
 329                     PKE_REG_##reg##_##flag##_B, PKE_REG_##reg##_##flag##_E); \
 330        BIT_MASK_SET(((me)->regs[PKE_REG_##reg][0]), \
 331                     PKE_REG_##reg##_##flag##_B, PKE_REG_##reg##_##flag##_E, \
 332                     (value)); \
 333        if((me)->fifo_trace_file != NULL) \
 334          { \
 335            if(old != (value)) \
 336              fprintf((me)->fifo_trace_file, "# Reg %s:%s = 0x%x\n", #reg, #flag, (unsigned)(value)); \
 337          } \
 338      } while(0)
 339
 340 /* get a bitfield from a register by "name" */
 341 #define PKE_REG_MASK_GET(me,reg,flag) \
 342      BIT_MASK_GET(((me)->regs[PKE_REG_##reg][0]), \
 343                   PKE_REG_##reg##_##flag##_B, PKE_REG_##reg##_##flag##_E)
 344
 345
 346 #define PKE_LIMIT(value,max) ((value) > (max) ? (max) : (value))
 347
 348
 349 /* Classify words in a FIFO quadword */
 350 enum wordclass
 351 {
 352   wc_dma = 'D',
 353   wc_pkecode = 'P',
 354   wc_unknown = '?',
 355   wc_pkedata = '.',
 356   wc_gpuiftag = 'g'
 357 };
 358
 359
 360 /* One row in the FIFO */
 361 struct fifo_quadword
 362 {
 363   /* 128 bits of data */
 364   quadword data;
 365   /* source main memory address (or 0: unknown) */
 366   unsigned_4 source_address;
 367   /* classification of words in quadword; wc_dma set on DMA tags at FIFO write */
 368   enum wordclass word_class[4];
 369 };
 370
 371
 372 /* quadword FIFO structure for PKE */
 373 typedef struct pke_fifo
 374 {
 375   struct fifo_quadword** quadwords; /* pointer to fifo quadwords */
 376   unsigned_4 origin; /* quadword serial number of quadwords[0] */
 377   unsigned_4 length; /* length of quadword pointer array: 0..N */
 378   unsigned_4 next;   /* relative index of first unfilled quadword: 0..length-1 */
 379 } pke_fifo;
 380
 381 #define PKE_FIFO_GROW_SIZE 1000 /* number of quadword pointers to allocate */
 382 #define PKE_FIFO_ARCHEOLOGY 1000 /* number of old quadwords to keep as history */
 383
 384
 385 /* PKE internal state: FIFOs, registers, handle to VU friend */
 386 struct pke_device
 387 {
 388   /* common device info */
 389   device dev;
 390
 391   /* identity: 0=PKE0, 1=PKE1 */
 392   int pke_number;
 393   int flags;
 394
 395   /* quadword registers: data in [0] word only */
 396   quadword regs[PKE_NUM_REGS];
 397
 398   /* write buffer for FIFO address */
 399   quadword fifo_qw_in_progress;
 400   int fifo_qw_done; /* bitfield */
 401
 402   /* FIFO - private: use only pke_fifo_* routines to access */
 403   struct pke_fifo fifo;  /* array of FIFO quadword pointers */
 404   FILE* fifo_trace_file; /* stdio stream open in append mode, or 0 for no trace */
 405
 406   /* FIFO cache -- curry last search pke_pcrel_fifo results */
 407   unsigned_4 last_fifo_pc;
 408   unsigned_4 last_qw_pc;
 409   unsigned_4 last_num;
 410   unsigned_4 last_new_fifo_pc;
 411   unsigned_4 last_new_qw_pc;
 412
 413   /* PC */
 414   int fifo_pc;  /* 0 .. (fifo_num_elements-1): quadword index of next instruction */
 415   int qw_pc;    /* 0 .. 3:                     word index of next instruction */
 416 };
 417
 418 extern struct pke_device pke0_device;
 419 extern struct pke_device pke1_device;
 420
 421 int read_pke_reg (struct pke_device *device, int regno, void *buf);
 422 int write_pke_reg (struct pke_device *device, int regno, const void *buf);
 423 int read_pke_pc (struct pke_device *device, void *buf);
 424
 425
 426 /* Flags for PKE.flags */
 427
 428 #define PKE_FLAG_NONE        0x00
 429 #define PKE_FLAG_PENDING_PSS 0x01 /* PSS bit written-to; set STAT:PSS after current instruction */
 430 #define PKE_FLAG_INT_NOLOOP  0x02 /* INT PKEcode received; INT/PIS set; suppress loop after resumption */
 431
 432
 433 /* Kludge alert */
 434
 435 #define PKE_MEM_READ(me,addr,data,size) \
 436     do { \
 437       sim_cpu* cpu = STATE_CPU(CURRENT_STATE, 0); \
 438       unsigned_##size value = \
 439         sim_core_read_aligned_##size(cpu, CIA_GET(cpu), read_map, \
 440                                      (SIM_ADDR)(addr)); \
 441       memcpy((unsigned_##size*) (data), (void*) & value, size); \
 442      } while(0)
 443
 444 #define PKE_MEM_WRITE(me,addr,data,size) \
 445     do { sim_cpu* cpu = STATE_CPU(CURRENT_STATE, 0); \
 446          unsigned_##size value; \
 447          memcpy((void*) & value, (unsigned_##size*)(data), size); \
 448          sim_core_write_aligned_##size(cpu, CIA_GET(cpu), write_map, \
 449                                        (SIM_ADDR)(addr), value); \
 450          if((me)->fifo_trace_file != NULL) \
 451            { \
 452              int i; \
 453              unsigned_##size value_te; \
 454              value_te = H2T_##size(value); \
 455              fprintf((me)->fifo_trace_file, "# Write %2d bytes  to  ", size); \
 456              fprintf((me)->fifo_trace_file, "0x%08lx: ", (unsigned long)(addr)); \
 457              for(i=0; i<size; i++) \
 458                fprintf((me)->fifo_trace_file, " %02x", ((unsigned_1*)(& value_te))[i]); \
 459              fprintf((me)->fifo_trace_file, "\n"); \
 460            } \
 461         } while(0)
 462
 463
 464
 465 #endif /* H_PKE_H */