sim/mips/vr4320.igen

   1
   2
   3 // Integer Instructions
   4 // --------------------
   5 //
   6 // MulAcc is the Multiply Accumulator.
   7 //     This register is mapped on the the HI and LO registers.
   8 //     Upper 32 bits of MulAcc is mapped on to lower 32 bits of HI register.
   9 //     Lower 32 bits of MulAcc is mapped on to lower 32 bits of LO register.
  10
  11
  12 :function:::unsigned64:MulAcc:
  13 {
  14   unsigned64 result = U8_4 (HI, LO);
  15   return result;
  16 }
  17
  18 :function:::void:SET_MulAcc:unsigned64 value
  19 {
  20   *AL4_8 (&HI) = VH4_8 (value);
  21   *AL4_8 (&LO) = VL4_8 (value);
  22 }
  23
  24 :function:::signed64:SignedMultiply:signed32 l, signed32 r
  25 {
  26   signed64 result = (signed64) l * (signed64) r;
  27   return result;
  28 }
  29
  30 :function:::unsigned64:UnsignedMultiply:unsigned32 l, unsigned32 r
  31 {
  32   unsigned64 result = (unsigned64) l * (unsigned64) r;
  33   return result;
  34 }
  35
  36 :function:::unsigned64:Low32Bits:unsigned64 value
  37 {
  38   unsigned64 result = (signed64) (signed32) VL4_8 (value);
  39   return result;
  40 }
  41
  42 :function:::unsigned64:High32Bits:unsigned64 value
  43 {
  44   unsigned64 result = (signed64) (signed32) VH4_8 (value);
  45   return result;
  46 }
  47
  48
  49
  50 // Multiply, Accumulate
  51 000000,5.RS,5.RT,00000,00000,101000::::MAC
  52 "mac r<RS>, r<RT>"
  53 *vr4320:
  54 {
  55   SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]));
  56 }
  57
  58 // D-Multiply, Accumulate
  59 000000,5.RS,5.RT,00000,00000,101001::::DMAC
  60 "dmac r<RS>, r<RT>"
  61 *vr4320:
  62 {
  63   LO = LO + SignedMultiply (SD_, GPR[RS], GPR[RT]);
  64 }
  65
  66 // Count Leading Zeros
  67 000000,5.RS,00000,5.RD,00000,110101::::CLZ
  68 "clz r<RD>, r<RS>"
  69 *vr4320:
  70 {
  71   unsigned32 t = Low32Bits (SD_, GPR[RS]);
  72   signed64 c = 0;
  73
  74   while (! (t & ( 1 << 31))
  75         && c < 32)
  76     {
  77     c++;
  78     t <<= 1;
  79     }
  80
  81   GPR[RD] = c;
  82 }
  83
  84 // D-Count Leading Zeros
  85 000000,5.RS,00000,5.RD,00000,111101::::DCLZ
  86 "dclz r<RD>, r<RS>"
  87 *vr4320:
  88 {
  89   unsigned64 t = GPR[RS];
  90   signed64 c = 0;
  91
  92   while (! (t & ( (unsigned64)1 << 63))
  93         && c < 64)
  94     {
  95     c++;
  96     t <<= 1;
  97     }
  98
  99   printf("lo %d\n", c);
 100   GPR[RD] = c;
 101 }
 102
 103
 104
 105
 106
 107
 108
 109 // Multiply and Move LO.
 110 000000,5.RS,5.RT,5.RD,00100,101000::::MUL
 111 "mul r<RD>, r<RS>, r<RT>"
 112 *vr4320:
 113 {
 114   SET_MulAcc (SD_, 0 + SignedMultiply (SD_, GPR[RS], GPR[RT]));
 115   GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
 116 }
 117
 118 // Unsigned Multiply and Move LO.
 119 000000,5.RS,5.RT,5.RD,00101,101000::::MULU
 120 "mulu r<RD>, r<RS>, r<RT>"
 121 *vr4320:
 122 {
 123   SET_MulAcc (SD_, 0 + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
 124   GPR[RD] = Low32Bits  (SD_, MulAcc (SD_));
 125 }
 126
 127 // Multiply and Move HI.
 128 000000,5.RS,5.RT,5.RD,01100,101000::::MULHI
 129 "mulhi r<RD>, r<RS>, r<RT>"
 130 *vr4320:
 131 {
 132   SET_MulAcc (SD_, 0 + SignedMultiply (SD_, GPR[RS], GPR[RT]));
 133   GPR[RD] = High32Bits (SD_, MulAcc (SD_));
 134 }
 135
 136 // Unsigned Multiply and Move HI.
 137 000000,5.RS,5.RT,5.RD,01101,101000::::MULHIU
 138 "mulhiu r<RD>, r<RS>, r<RT>"
 139 *vr4320:
 140 {
 141   SET_MulAcc (SD_, 0 + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
 142   GPR[RD] = High32Bits (SD_, MulAcc (SD_));
 143 }
 144
 145
 146
 147
 148
 149
 150 // Multiply, Accumulate and Move LO.
 151 000000,5.RS,5.RT,5.RD,00010,101000::::MACC
 152 "macc r<RD>, r<RS>, r<RT>"
 153 *vr4320:
 154 {
 155   SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]));
 156   GPR[RD] = Low32Bits  (SD_, MulAcc (SD_));
 157 }
 158
 159 // Unsigned Multiply, Accumulate and Move LO.
 160 000000,5.RS,5.RT,5.RD,00011,101000::::MACCU
 161 "maccu r<RD>, r<RS>, r<RT>"
 162 *vr4320:
 163 {
 164   SET_MulAcc (SD_, MulAcc (SD_) + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
 165   GPR[RD] = Low32Bits  (SD_, MulAcc (SD_));
 166 }
 167
 168 // Multiply, Accumulate and Move HI.
 169 000000,5.RS,5.RT,5.RD,01010,101000::::MACCHI
 170 "macchi r<RD>, r<RS>, r<RT>"
 171 *vr4320:
 172 {
 173   SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]));
 174   GPR[RD] = High32Bits (SD_, MulAcc (SD_));
 175 }
 176
 177 // Unsigned Multiply, Accumulate and Move HI.
 178 000000,5.RS,5.RT,5.RD,01011,101000::::MACCHIU
 179 "macchiu r<RD>, r<RS>, r<RT>"
 180 *vr4320:
 181 {
 182   SET_MulAcc (SD_, MulAcc (SD_) + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
 183   GPR[RD] = High32Bits (SD_, MulAcc (SD_));
 184
 185 }
 186