Initial creation of sourceware repository
[deliverable/binutils-gdb.git] / sim / mn10200 / mn10200_sim.h
1 #include <stdio.h>
2 #include <ctype.h>
3 #include "ansidecl.h"
4 #include "callback.h"
5 #include "opcode/mn10200.h"
6 #include <limits.h>
7 #include "remote-sim.h"
8
9 #ifndef INLINE
10 #ifdef __GNUC__
11 #define INLINE inline
12 #else
13 #define INLINE
14 #endif
15 #endif
16
17 extern host_callback *mn10200_callback;
18
19 #define DEBUG_TRACE 0x00000001
20 #define DEBUG_VALUES 0x00000002
21
22 extern int mn10200_debug;
23
24 #ifdef __STDC__
25 #define SIGNED signed
26 #else
27 #define SIGNED
28 #endif
29
30 #if UCHAR_MAX == 255
31 typedef unsigned char uint8;
32 typedef SIGNED char int8;
33 #else
34 error "Char is not an 8-bit type"
35 #endif
36
37 #if SHRT_MAX == 32767
38 typedef unsigned short uint16;
39 typedef SIGNED short int16;
40 #else
41 error "Short is not a 16-bit type"
42 #endif
43
44 #if INT_MAX == 2147483647
45
46 typedef unsigned int uint32;
47 typedef SIGNED int int32;
48
49 #else
50 # if LONG_MAX == 2147483647
51
52 typedef unsigned long uint32;
53 typedef SIGNED long int32;
54
55 # else
56 error "Neither int nor long is a 32-bit type"
57 # endif
58 #endif
59
60 typedef uint32 reg_t;
61
62 struct simops
63 {
64 long opcode;
65 long mask;
66 void (*func)();
67 int length;
68 int format;
69 int numops;
70 int operands[16];
71 };
72
73 /* The current state of the processor; registers, memory, etc. */
74
75 struct _state
76 {
77 reg_t regs[11]; /* registers, d0-d3, a0-a3, pc, mdr, psw */
78 uint8 *mem; /* main memory */
79 int exception; /* Actually a signal number. */
80 int exited; /* Did the program exit? */
81 } State;
82
83 extern uint32 OP[4];
84 extern struct simops Simops[];
85
86 #define PC (State.regs[8])
87
88 #define PSW (State.regs[10])
89 #define PSW_ZF 0x1
90 #define PSW_NF 0x2
91 #define PSW_CF 0x4
92 #define PSW_VF 0x8
93 #define PSW_ZX 0x10
94 #define PSW_NX 0x20
95 #define PSW_CX 0x40
96 #define PSW_VX 0x80
97
98 #define REG_D0 0
99 #define REG_A0 4
100 #define REG_SP 7
101 #define REG_PC 8
102 #define REG_MDR 9
103 #define REG_PSW 10
104
105 #define SEXT3(x) ((((x)&0x7)^(~0x3))+0x4)
106
107 /* sign-extend a 4-bit number */
108 #define SEXT4(x) ((((x)&0xf)^(~0x7))+0x8)
109
110 /* sign-extend a 5-bit number */
111 #define SEXT5(x) ((((x)&0x1f)^(~0xf))+0x10)
112
113 /* sign-extend an 8-bit number */
114 #define SEXT8(x) ((((x)&0xff)^(~0x7f))+0x80)
115
116 /* sign-extend a 9-bit number */
117 #define SEXT9(x) ((((x)&0x1ff)^(~0xff))+0x100)
118
119 /* sign-extend a 16-bit number */
120 #define SEXT16(x) ((((x)&0xffff)^(~0x7fff))+0x8000)
121
122 /* sign-extend a 22-bit number */
123 #define SEXT22(x) ((((x)&0x3fffff)^(~0x1fffff))+0x200000)
124
125 /* sign-extend a 24-bit number */
126 #define SEXT24(x) ((((x)&0xffffff)^(~0x7fffff))+0x800000)
127
128 #ifdef _WIN32
129 #define SIGTRAP 5
130 #define SIGQUIT 3
131 #endif
132
133 extern int max_mem;
134
135 #define load_mem_big(addr,len) \
136 (len == 1 ? *(((addr) & 0xffffff) + State.mem) : \
137 len == 2 ? ((*(((addr) & 0xffffff) + State.mem) << 8) \
138 | *((((addr) + 1) & 0xffffff) + State.mem)) : \
139 ((*(((addr) & 0xffffff) + State.mem) << 16) \
140 | (*((((addr) + 1) & 0xffffff) + State.mem) << 8) \
141 | *((((addr) + 2) & 0xffffff) + State.mem)))
142
143 static INLINE uint32
144 load_byte (addr)
145 SIM_ADDR addr;
146 {
147 uint8 *p = (addr & 0xffffff) + State.mem;
148
149 #ifdef CHECK_ADDR
150 if ((addr & 0xffffff) > max_mem)
151 abort ();
152 #endif
153
154 return p[0];
155 }
156
157 static INLINE uint32
158 load_half (addr)
159 SIM_ADDR addr;
160 {
161 uint8 *p = (addr & 0xffffff) + State.mem;
162
163 #ifdef CHECK_ADDR
164 if ((addr & 0xffffff) > max_mem)
165 abort ();
166 #endif
167
168 return p[1] << 8 | p[0];
169 }
170
171 static INLINE uint32
172 load_3_byte (addr)
173 SIM_ADDR addr;
174 {
175 uint8 *p = (addr & 0xffffff) + State.mem;
176
177 #ifdef CHECK_ADDR
178 if ((addr & 0xffffff) > max_mem)
179 abort ();
180 #endif
181
182 return p[2] << 16 | p[1] << 8 | p[0];
183 }
184
185 static INLINE uint32
186 load_word (addr)
187 SIM_ADDR addr;
188 {
189 uint8 *p = (addr & 0xffffff) + State.mem;
190
191 #ifdef CHECK_ADDR
192 if ((addr & 0xffffff) > max_mem)
193 abort ();
194 #endif
195
196 return p[3] << 24 | p[2] << 16 | p[1] << 8 | p[0];
197 }
198
199 static INLINE uint32
200 load_mem (addr, len)
201 SIM_ADDR addr;
202 int len;
203 {
204 uint8 *p = (addr & 0xffffff) + State.mem;
205
206 #ifdef CHECK_ADDR
207 if ((addr & 0xffffff) > max_mem)
208 abort ();
209 #endif
210
211 switch (len)
212 {
213 case 1:
214 return p[0];
215 case 2:
216 return p[1] << 8 | p[0];
217 case 3:
218 return p[2] << 16 | p[1] << 8 | p[0];
219 case 4:
220 return p[3] << 24 | p[2] << 16 | p[1] << 8 | p[0];
221 default:
222 abort ();
223 }
224 }
225
226 static INLINE void
227 store_byte (addr, data)
228 SIM_ADDR addr;
229 uint32 data;
230 {
231 uint8 *p = (addr & 0xffffff) + State.mem;
232
233 #ifdef CHECK_ADDR
234 if ((addr & 0xffffff) > max_mem)
235 abort ();
236 #endif
237
238 p[0] = data;
239 }
240
241 static INLINE void
242 store_half (addr, data)
243 SIM_ADDR addr;
244 uint32 data;
245 {
246 uint8 *p = (addr & 0xffffff) + State.mem;
247
248 #ifdef CHECK_ADDR
249 if ((addr & 0xffffff) > max_mem)
250 abort ();
251 #endif
252
253 p[0] = data;
254 p[1] = data >> 8;
255 }
256
257 static INLINE void
258 store_3_byte (addr, data)
259 SIM_ADDR addr;
260 uint32 data;
261 {
262 uint8 *p = (addr & 0xffffff) + State.mem;
263
264 #ifdef CHECK_ADDR
265 if ((addr & 0xffffff) > max_mem)
266 abort ();
267 #endif
268
269 p[0] = data;
270 p[1] = data >> 8;
271 p[2] = data >> 16;
272 }
273
274 static INLINE void
275 store_word (addr, data)
276 SIM_ADDR addr;
277 uint32 data;
278 {
279 uint8 *p = (addr & 0xffffff) + State.mem;
280
281 #ifdef CHECK_ADDR
282 if ((addr & 0xffffff) > max_mem)
283 abort ();
284 #endif
285
286 p[0] = data;
287 p[1] = data >> 8;
288 p[2] = data >> 16;
289 p[3] = data >> 24;
290 }
291
292 /* Function declarations. */
293
294 uint32 get_word PARAMS ((uint8 *));
295 void put_word PARAMS ((uint8 *, uint32));
296
297 extern uint8 *map PARAMS ((SIM_ADDR addr));
This page took 0.035191 seconds and 4 git commands to generate.