sim/mn10300/ChangeLog

   1 Mon Dec 16 10:03:52 1996  Jeffrey A Law  (law@cygnus.com)
   2
   3         * simops.c: Handle "break" instruction.
   4
   5         * simops.c: Fix restoring the PC for "ret" and "retf" instructions.
   6
   7 Wed Dec 11 09:53:10 1996  Jeffrey A Law  (law@cygnus.com)
   8
   9         * gencode.c (write_opcodes): Also write out the format of the
  10         opcode.
  11         * mn10300_sim.h (simops): Add "format" field.
  12         * interp.c (sim_resume): Deal with endianness issues here.
  13
  14 Tue Dec 10 15:05:37 1996  Jeffrey A Law  (law@cygnus.com)
  15
  16         * simops.c (REG0_4): Define.
  17         Use REG0_4 for indexed loads/stores.
  18
  19 Sat Dec  7 09:50:28 1996  Jeffrey A Law  (law@cygnus.com)
  20
  21         * simops.c (REG0_16): Fix typo.
  22
  23 Fri Dec  6 14:13:34 1996  Jeffrey A Law  (law@cygnus.com)
  24
  25         * simops.c: Call abort for any instruction that's not currently
  26         simulated.
  27
  28         * simops.c: Define accessor macros to extract register
  29         values from instructions.  Use them consistently.
  30
  31         * interp.c: Delete unused global variable "OP".
  32         (sim_resume): Remove unused variable "opcode".
  33         * simops.c: Fix some uninitialized variable problems, add
  34         parens to fix various -Wall warnings.
  35
  36         * gencode.c (write_header): Add "insn" and "extension" arguments
  37         to the OP_* declarations.
  38         (write_template): Similarly for function templates.
  39         * interp.c (insn, extension): Remove global variables.  Instead
  40         pass them as arguments to the OP_* functions.
  41         * mn10300_sim.h: Remove decls for "insn" and "extension".
  42         * simops.c (OP_*): Accept "insn" and "extension" as arguments
  43         instead of using globals.
  44
  45 Thu Dec  5 22:26:31 1996  Jeffrey A Law  (law@cygnus.com)
  46
  47         * simops.c: Fix typos in "mov am,(d16,an)" and "mov am,(d32,an)"
  48
  49         * simops.c: Fix thinkos in last change to "inc dn".
  50
  51 Wed Dec  4 10:57:53 1996  Jeffrey A Law  (law@cygnus.com)
  52
  53         * simops.c: "add imm,sp" does not effect the condition codes.
  54         "inc dn" does effect the condition codes.
  55
  56 Tue Dec  3 17:37:45 1996  Jeffrey A Law  (law@cygnus.com)
  57
  58         * simops.c: Treat both operands as signed values for
  59         "div" instruction.
  60
  61         * simops.c: Fix simulation of division instructions.
  62         Fix typos/thinkos in several "cmp" and "sub" instructions.
  63
  64 Mon Dec  2 12:31:40 1996  Jeffrey A Law  (law@cygnus.com)
  65
  66         * simops.c: Fix carry bit handling in "sub" and "cmp"
  67         instructions.
  68
  69         * simops.c: Fix "mov imm8,an" and "mov imm16,dn".
  70
  71 Sun Dec  1 16:05:42 1996  Jeffrey A Law  (law@cygnus.com)
  72
  73         * simops.c: Fix overflow computation for many instructions.
  74
  75         * simops.c: Fix "mov dm, an", "movbu dm, (an)", and "movhu dm, (an)".
  76
  77         * simops.c: Fix "mov am, dn".
  78
  79         * simops.c: Fix more bugs in "add imm,an" and
  80         "add imm,dn".
  81
  82 Wed Nov 27 09:20:42 1996  Jeffrey A Law  (law@cygnus.com)
  83
  84         * simops.c: Fix bugs in "movm" and "add imm,an".
  85
  86         * simops.c: Don't lose the upper 24 bits of the return
  87         pointer in "call" and "calls" instructions.  Rough cut
  88         at emulated system calls.
  89
  90         * simops.c: Implement the remaining 5, 6 and 7 byte instructions.
  91
  92         * simops.c: Implement remaining 4 byte instructions.
  93
  94         * simops.c: Implement remaining 3 byte instructions.
  95
  96         * simops.c: Implement remaining 2 byte instructions.  Call
  97         abort for instructions we're not implementing now.
  98
  99 Tue Nov 26 15:43:41 1996  Jeffrey A Law  (law@cygnus.com)
 100
 101         * simops.c: Implement lots of random instructions.
 102
 103         * simops.c: Implement "movm" and "bCC" insns.
 104
 105         * mn10300_sim.h (_state): Add another register (MDR).
 106         (REG_MDR): Define.
 107         * simops.c: Implement "cmp", "calls", "rets", "jmp" and
 108         a few additional random insns.
 109
 110         * mn10300_sim.h (PSW_*): Define for CC status tracking.
 111         (REG_D0, REG_A0, REG_SP): Define.
 112         * simops.c: Implement "add", "addc" and a few other random
 113         instructions.
 114
 115         * gencode.c, interp.c: Snapshot current simulator code.
 116
 117 Mon Nov 25 12:46:38 1996  Jeffrey A Law  (law@cygnus.com)
 118
 119         * Makefile.in, config.in, configure, configure.in: New files.
 120         * gencode.c, interp.c, mn10300_sim.h, simops.c: New files.
 121