sim/mn10300/ChangeLog

   1 Wed Dec 18 10:10:45 1996  Jeffrey A Law  (law@cygnus.com)
   2
   3         * interp.c (sim_resume): Handle 0xff as a single byte insn.
   4
   5         * simops.c: Fix overflow computation for "add" and "inc"
   6         instructions.
   7
   8 Mon Dec 16 10:03:52 1996  Jeffrey A Law  (law@cygnus.com)
   9
  10         * simops.c: Handle "break" instruction.
  11
  12         * simops.c: Fix restoring the PC for "ret" and "retf" instructions.
  13
  14 Wed Dec 11 09:53:10 1996  Jeffrey A Law  (law@cygnus.com)
  15
  16         * gencode.c (write_opcodes): Also write out the format of the
  17         opcode.
  18         * mn10300_sim.h (simops): Add "format" field.
  19         * interp.c (sim_resume): Deal with endianness issues here.
  20
  21 Tue Dec 10 15:05:37 1996  Jeffrey A Law  (law@cygnus.com)
  22
  23         * simops.c (REG0_4): Define.
  24         Use REG0_4 for indexed loads/stores.
  25
  26 Sat Dec  7 09:50:28 1996  Jeffrey A Law  (law@cygnus.com)
  27
  28         * simops.c (REG0_16): Fix typo.
  29
  30 Fri Dec  6 14:13:34 1996  Jeffrey A Law  (law@cygnus.com)
  31
  32         * simops.c: Call abort for any instruction that's not currently
  33         simulated.
  34
  35         * simops.c: Define accessor macros to extract register
  36         values from instructions.  Use them consistently.
  37
  38         * interp.c: Delete unused global variable "OP".
  39         (sim_resume): Remove unused variable "opcode".
  40         * simops.c: Fix some uninitialized variable problems, add
  41         parens to fix various -Wall warnings.
  42
  43         * gencode.c (write_header): Add "insn" and "extension" arguments
  44         to the OP_* declarations.
  45         (write_template): Similarly for function templates.
  46         * interp.c (insn, extension): Remove global variables.  Instead
  47         pass them as arguments to the OP_* functions.
  48         * mn10300_sim.h: Remove decls for "insn" and "extension".
  49         * simops.c (OP_*): Accept "insn" and "extension" as arguments
  50         instead of using globals.
  51
  52 Thu Dec  5 22:26:31 1996  Jeffrey A Law  (law@cygnus.com)
  53
  54         * simops.c: Fix typos in "mov am,(d16,an)" and "mov am,(d32,an)"
  55
  56         * simops.c: Fix thinkos in last change to "inc dn".
  57
  58 Wed Dec  4 10:57:53 1996  Jeffrey A Law  (law@cygnus.com)
  59
  60         * simops.c: "add imm,sp" does not effect the condition codes.
  61         "inc dn" does effect the condition codes.
  62
  63 Tue Dec  3 17:37:45 1996  Jeffrey A Law  (law@cygnus.com)
  64
  65         * simops.c: Treat both operands as signed values for
  66         "div" instruction.
  67
  68         * simops.c: Fix simulation of division instructions.
  69         Fix typos/thinkos in several "cmp" and "sub" instructions.
  70
  71 Mon Dec  2 12:31:40 1996  Jeffrey A Law  (law@cygnus.com)
  72
  73         * simops.c: Fix carry bit handling in "sub" and "cmp"
  74         instructions.
  75
  76         * simops.c: Fix "mov imm8,an" and "mov imm16,dn".
  77
  78 Sun Dec  1 16:05:42 1996  Jeffrey A Law  (law@cygnus.com)
  79
  80         * simops.c: Fix overflow computation for many instructions.
  81
  82         * simops.c: Fix "mov dm, an", "movbu dm, (an)", and "movhu dm, (an)".
  83
  84         * simops.c: Fix "mov am, dn".
  85
  86         * simops.c: Fix more bugs in "add imm,an" and
  87         "add imm,dn".
  88
  89 Wed Nov 27 09:20:42 1996  Jeffrey A Law  (law@cygnus.com)
  90
  91         * simops.c: Fix bugs in "movm" and "add imm,an".
  92
  93         * simops.c: Don't lose the upper 24 bits of the return
  94         pointer in "call" and "calls" instructions.  Rough cut
  95         at emulated system calls.
  96
  97         * simops.c: Implement the remaining 5, 6 and 7 byte instructions.
  98
  99         * simops.c: Implement remaining 4 byte instructions.
 100
 101         * simops.c: Implement remaining 3 byte instructions.
 102
 103         * simops.c: Implement remaining 2 byte instructions.  Call
 104         abort for instructions we're not implementing now.
 105
 106 Tue Nov 26 15:43:41 1996  Jeffrey A Law  (law@cygnus.com)
 107
 108         * simops.c: Implement lots of random instructions.
 109
 110         * simops.c: Implement "movm" and "bCC" insns.
 111
 112         * mn10300_sim.h (_state): Add another register (MDR).
 113         (REG_MDR): Define.
 114         * simops.c: Implement "cmp", "calls", "rets", "jmp" and
 115         a few additional random insns.
 116
 117         * mn10300_sim.h (PSW_*): Define for CC status tracking.
 118         (REG_D0, REG_A0, REG_SP): Define.
 119         * simops.c: Implement "add", "addc" and a few other random
 120         instructions.
 121
 122         * gencode.c, interp.c: Snapshot current simulator code.
 123
 124 Mon Nov 25 12:46:38 1996  Jeffrey A Law  (law@cygnus.com)
 125
 126         * Makefile.in, config.in, configure, configure.in: New files.
 127         * gencode.c, interp.c, mn10300_sim.h, simops.c: New files.
 128