3 // Given an extended register number, translate it into an index into the
4 // register array. This is necessary as the upper 8 extended registers are
5 // actually synonyms for the d0-d3/a0-a3 registers.
9 :function:::int:translate_rreg:int rreg
12 /* The higher register numbers actually correspond to the
13 basic machine's address and data registers. */
14 if (rreg > 7 && rreg < 12)
15 return REG_A0 + rreg - 8;
16 else if (rreg > 11 && rreg < 16)
17 return REG_D0 + rreg - 12;
22 :function:::int:translate_xreg:int xreg
41 // 1111 0000 0010 00An; mov USP,An
42 8.0xf0+4.0x2,00,2.AN0:D0m:::mov
47 State.regs[REG_A0 + AN0] = State.regs[REG_USP];
51 // 1111 0000 0010 01An; mov SSP,An
52 8.0xf0+4.0x2,01,2.AN0:D0n:::mov
57 State.regs[REG_A0 + AN0] = State.regs[REG_SSP];
61 // 1111 0000 0010 10An; mov MSP,An
62 8.0xf0+4.0x2,10,2.AN0:D0o:::mov
67 State.regs[REG_A0 + AN0] = State.regs[REG_MSP];
71 // 1111 0000 0010 11An; mov PC,An
72 8.0xf0+4.0x2,11,2.AN0:D0p:::mov
77 State.regs[REG_A0 + AN0] = PC;
81 // 1111 0000 0011 Am00; mov Am,USP
82 8.0xf0+4.0x3,2.AM1,00:D0q:::mov
87 State.regs[REG_USP] = State.regs[REG_A0 + AM1];
90 // 1111 0000 0011 Am01; mov Am,SSP
91 8.0xf0+4.0x3,2.AM1,01:D0r:::mov
96 State.regs[REG_SSP] = State.regs[REG_A0 + AM1];
99 // 1111 0000 0011 Am10; mov Am,MSP
100 8.0xf0+4.0x3,2.AM1,10:D0s:::mov
105 State.regs[REG_MSP] = State.regs[REG_A0 + AM1];
109 // 1111 0000 1110 imm4; syscall
110 8.0xf0+4.0xe,IMM4:D0t:::syscall
114 unsigned int sp, next_pc;
117 sp = State.regs[REG_SP];
118 next_pc = State.regs[REG_PC] + 2;
119 store_word (sp - 4, next_pc);
120 store_word (sp - 8, PSW);
121 State.regs[REG_PC] = 0x40000000 + IMM4 * 8;
126 // 1111 0010 1110 11Dn; mov EPSW,Dn
127 8.0xf2+4.0xe,11,2.DN0:D0u:::mov
132 State.regs[REG_D0 + DN0] = PSW;
136 // 1111 0010 1111 Dm01; mov Dm,EPSW
137 8.0xf2+4.0xf,2.DM1,01:D0v:::mov
142 PSW = State.regs[REG_D0 + DM1];
145 // 1111 0101 00Am Rn; mov Am,Rn
146 8.0xf5+00,2.AM1,4.RN0:D0w:::mov
150 int destreg = translate_rreg (SD_, RN0);
153 State.regs[destreg] = State.regs[REG_A0 + AM1];
156 // 1111 0101 01Dm Rn; mov Dm,Rn
157 8.0xf5+01,2.DM1,4.RN0:D0x:::mov
161 int destreg = translate_rreg (SD_, RN0);
164 State.regs[destreg] = State.regs[REG_D0 + DM1];
167 // 1111 0101 10Rm An; mov Rm,An
168 8.0xf5+10,4.RM1,2.AN0:D0y:::mov
172 int destreg = translate_rreg (SD_, RM1);
175 State.regs[REG_A0 + AN0] = State.regs[destreg];
178 // 1111 0101 11Rm Dn; mov Rm,Dn
179 8.0xf5+11,4.RM1,2.DN0:D0z:::mov
183 int destreg = translate_rreg (SD_, RM1);
186 State.regs[REG_D0 + DN0] = State.regs[destreg];
190 // 1111 1000 1100 1110 regs....; movm (USP),regs
191 8.0xf8+8.0xce+8.REGS:D1a:::movm
195 unsigned long usp = State.regs[REG_USP];
204 State.regs[REG_LAR] = load_word (usp);
206 State.regs[REG_LIR] = load_word (usp);
208 State.regs[REG_MDR] = load_word (usp);
210 State.regs[REG_A0 + 1] = load_word (usp);
212 State.regs[REG_A0] = load_word (usp);
214 State.regs[REG_D0 + 1] = load_word (usp);
216 State.regs[REG_D0] = load_word (usp);
222 State.regs[REG_A0 + 3] = load_word (usp);
228 State.regs[REG_A0 + 2] = load_word (usp);
234 State.regs[REG_D0 + 3] = load_word (usp);
240 State.regs[REG_D0 + 2] = load_word (usp);
244 /* start-sanitize-am33 */
245 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
249 /* Need to restore MDQR, MCRH, MCRL, and MCVF */
251 State.regs[REG_E0 + 1] = load_word (usp);
253 State.regs[REG_E0 + 0] = load_word (usp);
259 State.regs[REG_E0 + 7] = load_word (usp);
261 State.regs[REG_E0 + 6] = load_word (usp);
263 State.regs[REG_E0 + 5] = load_word (usp);
265 State.regs[REG_E0 + 4] = load_word (usp);
271 State.regs[REG_E0 + 3] = load_word (usp);
273 State.regs[REG_E0 + 2] = load_word (usp);
277 /* end-sanitize-am33 */
279 /* And make sure to update the stack pointer. */
280 State.regs[REG_USP] = usp;
283 // 1111 1000 1100 1111 regs....; movm (USP),regs
284 8.0xf8+8.0xcf+8.REGS:D1b:::movm
288 unsigned long usp = State.regs[REG_USP];
291 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
296 store_word (usp, State.regs[REG_E0 + 2]);
298 store_word (usp, State.regs[REG_E0 + 3]);
304 store_word (usp, State.regs[REG_E0 + 4]);
306 store_word (usp, State.regs[REG_E0 + 5]);
308 store_word (usp, State.regs[REG_E0 + 6]);
310 store_word (usp, State.regs[REG_E0 + 7]);
316 store_word (usp, State.regs[REG_E0 + 0]);
318 store_word (usp, State.regs[REG_E0 + 1]);
320 /* Need to save MDQR, MCRH, MCRL, and MCVF */
323 /* end-sanitize-am33 */
328 store_word (usp, State.regs[REG_D0 + 2]);
334 store_word (usp, State.regs[REG_D0 + 3]);
340 store_word (usp, State.regs[REG_A0 + 2]);
346 store_word (usp, State.regs[REG_A0 + 3]);
352 store_word (usp, State.regs[REG_D0]);
354 store_word (usp, State.regs[REG_D0 + 1]);
356 store_word (usp, State.regs[REG_A0]);
358 store_word (usp, State.regs[REG_A0 + 1]);
360 store_word (usp, State.regs[REG_MDR]);
362 store_word (usp, State.regs[REG_LIR]);
364 store_word (usp, State.regs[REG_LAR]);
368 /* And make sure to update the stack pointer. */
369 State.regs[REG_USP] = usp;
372 // 1111 1100 1111 1100 imm32...; and imm32,EPSW
373 8.0xfc+8.0xfc+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:4a:::and
378 PSW &= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
381 // 1111 1100 1111 1101 imm32...; or imm32,EPSW
382 8.0xfc+8.0xfd+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::or
387 PSW |= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
390 // 1111 1001 0000 1000 Rm Rn; mov Rm,Rn (Rm != Rn)
391 8.0xf9+8.0x08+4.RM2,4.RN0!RM2:D1g:::mov
399 srcreg = translate_rreg (SD_, RM2);
400 dstreg = translate_rreg (SD_, RN0);
401 State.regs[dstreg] = State.regs[srcreg];
404 // 1111 1001 0001 1000 Rn Rn; ext Rn
405 8.0xf9+8.0x18+4.RN0,4.RN2=RN0:D1:::ext
412 srcreg = translate_rreg (SD_, RN0);
413 if (State.regs[srcreg] & 0x80000000)
414 State.regs[REG_MDR] = -1;
416 State.regs[REG_MDR] = 0;
419 // 1111 1001 0010 1000 Rm Rn; extb Rm,Rn
420 8.0xf9+8.0x28+4.RM2,4.RN0!RM2:D1:::extb
427 srcreg = translate_rreg (SD_, RM2);
428 dstreg = translate_rreg (SD_, RN0);
429 State.regs[dstreg] = EXTEND8 (State.regs[srcreg]);
432 // 1111 1001 0011 1000 Rm Rn; extbu Rm,Rn
433 8.0xf9+8.0x38+4.RM2,4.RN0!RM2:D1:::extbu
440 srcreg = translate_rreg (SD_, RM2);
441 dstreg = translate_rreg (SD_, RN0);
442 State.regs[dstreg] = State.regs[srcreg] & 0xff;
445 // 1111 1001 0100 1000 Rm Rn; exth Rm,Rn
446 8.0xf9+8.0x48+4.RM2,4.RN0!RM2:D1:::exth
453 srcreg = translate_rreg (SD_, RM2);
454 dstreg = translate_rreg (SD_, RN0);
455 State.regs[dstreg] = EXTEND16 (State.regs[srcreg]);
458 // 1111 1001 0101 1000 Rm Rn; exthu Rm,Rn
459 8.0xf9+8.0x58+4.RM2,4.RN0!RM2:D1:::exthu
466 srcreg = translate_rreg (SD_, RM2);
467 dstreg = translate_rreg (SD_, RN0);
468 State.regs[dstreg] = State.regs[srcreg] & 0xffff;
471 // 1111 1001 0110 1000 Rn Rn; clr Rn
472 8.0xf9+8.0x68+4.RM2,4.RN0=RM2:D1:::clr
479 dstreg = translate_rreg (SD_, RN0);
480 State.regs[dstreg] = 0;
482 PSW &= ~(PSW_V | PSW_C | PSW_N);
485 // 1111 1001 0111 1000 Rm Rn; add Rm,Rn
486 8.0xf9+8.0x78+4.RM2,4.RN0:D1b:::add
493 srcreg = translate_rreg (SD_, RM2);
494 dstreg = translate_rreg (SD_, RN0);
495 genericAdd (State.regs[srcreg], dstreg);
498 // 1111 1001 1000 1000 Rm Rn; addc Rm,Rn
499 8.0xf9+8.0x88+4.RM2,4.RN0:D1b:::addc
505 unsigned long reg1, reg2, sum;
508 srcreg = translate_rreg (SD_, RM2);
509 dstreg = translate_rreg (SD_, RN0);
511 reg1 = State.regs[srcreg];
512 reg2 = State.regs[dstreg];
513 sum = reg1 + reg2 + ((PSW & PSW_C) != 0);
514 State.regs[dstreg] = sum;
516 z = ((PSW & PSW_Z) != 0) && (sum == 0);
517 n = (sum & 0x80000000);
518 c = (sum < reg1) || (sum < reg2);
519 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
520 && (reg2 & 0x80000000) != (sum & 0x80000000));
522 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
523 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
524 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
527 // 1111 1001 1001 1000 Rm Rn; sub Rm,Rn
528 8.0xf9+8.0x98+4.RM2,4.RN0:D1b:::sub
535 srcreg = translate_rreg (SD_, RM2);
536 dstreg = translate_rreg (SD_, RN0);
537 genericSub (State.regs[srcreg], dstreg);
540 // 1111 1001 1010 1000 Rm Rn; subc Rm,Rn
541 8.0xf9+8.0xa8+4.RM2,4.RN0:D1b:::subc
547 unsigned long reg1, reg2, difference;
550 srcreg = translate_rreg (SD_, RM2);
551 dstreg = translate_rreg (SD_, RN0);
553 reg1 = State.regs[srcreg];
554 reg2 = State.regs[dstreg];
555 difference = reg2 - reg1 - ((PSW & PSW_C) != 0);
556 State.regs[dstreg] = difference;
558 z = ((PSW & PSW_Z) != 0) && (difference == 0);
559 n = (difference & 0x80000000);
561 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
562 && (reg2 & 0x80000000) != (difference & 0x80000000));
564 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
565 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
566 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
569 // 1111 1001 1011 1000 Rn Rn; inc Rn
570 8.0xf9+8.0xb8+4.RN0,4.RN2=RN0:D1:::inc
577 dstreg = translate_rreg (SD_, RN0);
578 genericAdd (1, dstreg);
581 // 1111 1001 1101 1000 Rn Rn; inc Rn
582 8.0xf9+8.0xc8+4.RN0,4.RN2=RN0:D1:::inc4
589 dstreg = translate_rreg (SD_, RN0);
590 State.regs[dstreg] += 4;
593 // 1111 1001 1101 1000 Rm Rn; cmp Rm,Rn
594 8.0xf9+8.0xd8+4.RM2,4.RN0:D1:::cmp
598 int srcreg1, srcreg2;
601 srcreg1 = translate_rreg (SD_, RN0);
602 srcreg2 = translate_rreg (SD_, RM2);
603 genericCmp (State.regs[srcreg2], State.regs[srcreg1]);
606 // 1111 1001 1110 1000 XRm Rn; mov XRm,Rn
607 8.0xf9+8.0xe8+4.XRM2,4.RN0:D1l:::mov
614 dstreg = translate_rreg (SD_, RN0);
615 srcreg = translate_xreg (SD_, XRM2);
617 State.regs[dstreg] = State.regs[srcreg];
620 // 1111 1001 1111 1000 Rm XRn; mov Rm,XRn
621 8.0xf9+8.0xf8+4.RM2,4.XRN0:D1m:::mov
628 srcreg = translate_rreg (SD_, RM2);
629 dstreg = translate_xreg (SD_, XRN0);
631 State.regs[dstreg] = State.regs[srcreg];
634 // 1111 1001 0000 1001 Rm Rn; and Rm,Rn
635 8.0xf9+8.0x09+4.RM2,4.RN0:D1a:::and
644 srcreg = translate_rreg (SD_, RM2);
645 dstreg = translate_rreg (SD_, RN0);
647 State.regs[dstreg] &= State.regs[srcreg];
648 z = (State.regs[dstreg] == 0);
649 n = (State.regs[dstreg] & 0x80000000) != 0;
650 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
651 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
654 // 1111 1001 0001 1001 Rm Rn; or Rm,Rn
655 8.0xf9+8.0x19+4.RM2,4.RN0:D1a:::or
663 srcreg = translate_rreg (SD_, RM2);
664 dstreg = translate_rreg (SD_, RN0);
666 State.regs[dstreg] |= State.regs[srcreg];
667 z = (State.regs[dstreg] == 0);
668 n = (State.regs[dstreg] & 0x80000000) != 0;
669 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
670 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
673 // 1111 1001 0010 1001 Rm Rn; xor Rm,Rn
674 8.0xf9+8.0x29+4.RM2,4.RN0:D1a:::xor
682 srcreg = translate_rreg (SD_, RM2);
683 dstreg = translate_rreg (SD_, RN0);
685 State.regs[dstreg] ^= State.regs[srcreg];
686 z = (State.regs[dstreg] == 0);
687 n = (State.regs[dstreg] & 0x80000000) != 0;
688 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
689 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
692 // 1111 1001 0011 1001 Rn Rn; not Rn
693 8.0xf9+8.0x39+4.RM2,4.RN0=RM2:D1:::not
701 dstreg = translate_rreg (SD_, RN0);
703 State.regs[dstreg] = ~State.regs[dstreg];
704 z = (State.regs[dstreg] == 0);
705 n = (State.regs[dstreg] & 0x80000000) != 0;
706 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
707 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
710 // 1111 1001 0100 1001 Rm Rn; asr Rm,Rn
711 8.0xf9+8.0x49+4.RM2,4.RN0:D1a:::asr
720 srcreg = translate_rreg (SD_, RM2);
721 dstreg = translate_rreg (SD_, RN0);
723 temp = State.regs[dstreg];
725 temp >>= State.regs[srcreg];
726 State.regs[dstreg] = temp;
727 z = (State.regs[dstreg] == 0);
728 n = (State.regs[dstreg] & 0x80000000) != 0;
729 PSW &= ~(PSW_Z | PSW_N | PSW_C);
730 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
733 // 1111 1001 0101 1001 Rm Rn; lsr Rm,Rn
734 8.0xf9+8.0x59+4.RM2,4.RN0:D1a:::lsr
743 srcreg = translate_rreg (SD_, RM2);
744 dstreg = translate_rreg (SD_, RN0);
746 c = State.regs[dstreg] & 1;
747 State.regs[dstreg] >>= State.regs[srcreg];
748 z = (State.regs[dstreg] == 0);
749 n = (State.regs[dstreg] & 0x80000000) != 0;
750 PSW &= ~(PSW_Z | PSW_N | PSW_C);
751 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
754 // 1111 1001 0110 1001 Rm Rn; asl Rm,Rn
755 8.0xf9+8.0x69+4.RM2,4.RN0:D1a:::asl
763 srcreg = translate_rreg (SD_, RM2);
764 dstreg = translate_rreg (SD_, RN0);
766 State.regs[dstreg] <<= State.regs[srcreg];
767 z = (State.regs[dstreg] == 0);
768 n = (State.regs[dstreg] & 0x80000000) != 0;
769 PSW &= ~(PSW_Z | PSW_N);
770 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
773 // 1111 1001 0111 1001 Rn Rn; asl2 Rn
774 8.0xf9+8.0x79+4.RM2,4.RN0=RM2:D1:::asl2
782 dstreg = translate_rreg (SD_, RN0);
784 State.regs[dstreg] <<= 2;
785 z = (State.regs[dstreg] == 0);
786 n = (State.regs[dstreg] & 0x80000000) != 0;
787 PSW &= ~(PSW_Z | PSW_N);
788 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
791 // 1111 1001 1000 1001 Rn Rn; ror Rn
792 8.0xf9+8.0x89+4.RM2,4.RN0=RM2:D1:::ror
801 dstreg = translate_rreg (SD_, RN0);
803 value = State.regs[dstreg];
807 value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0;
808 State.regs[dstreg] = value;
810 n = (value & 0x80000000) != 0;
811 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
812 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
815 // 1111 1001 1001 1001 Rn Rn; rol Rn
816 8.0xf9+8.0x99+4.RM2,4.RN0=RM2:D1:::rol
825 dstreg = translate_rreg (SD_, RN0);
827 value = State.regs[dstreg];
828 c = (value & 0x80000000) ? 1 : 0;
831 value |= ((PSW & PSW_C) != 0);
832 State.regs[dstreg] = value;
834 n = (value & 0x80000000) != 0;
835 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
836 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
839 // 1111 1001 1010 1001 Rm Rn; mul Rm,Rn
840 8.0xf9+8.0xa9+4.RM2,4.RN0:D1b:::mul
845 unsigned long long temp;
849 srcreg = translate_rreg (SD_, RM2);
850 dstreg = translate_rreg (SD_, RN0);
852 temp = ((signed64)(signed32)State.regs[dstreg]
853 * (signed64)(signed32)State.regs[srcreg]);
854 State.regs[dstreg] = temp & 0xffffffff;
855 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
856 z = (State.regs[dstreg] == 0);
857 n = (State.regs[dstreg] & 0x80000000) != 0;
858 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
859 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
862 // 1111 1001 1011 1001 Rm Rn; mulu Rm,Rn
863 8.0xf9+8.0xb9+4.RM2,4.RN0:D1b:::mulu
868 unsigned long long temp;
872 srcreg = translate_rreg (SD_, RM2);
873 dstreg = translate_rreg (SD_, RN0);
875 temp = ((unsigned64)State.regs[dstreg]
876 * (unsigned64)State.regs[srcreg]);
877 State.regs[dstreg] = temp & 0xffffffff;
878 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
879 z = (State.regs[dstreg] == 0);
880 n = (State.regs[dstreg] & 0x80000000) != 0;
881 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
882 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
885 // 1111 1001 1100 1001 Rm Rn; div Rm,Rn
886 8.0xf9+8.0xc9+4.RM2,4.RN0:D1b:::div
895 srcreg = translate_rreg (SD_, RM2);
896 dstreg = translate_rreg (SD_, RN0);
898 temp = State.regs[REG_MDR];
900 temp |= State.regs[dstreg];
901 State.regs[REG_MDR] = temp % (signed32)State.regs[srcreg];
902 temp /= (signed32)State.regs[srcreg];
903 State.regs[dstreg] = temp & 0xffffffff;
904 z = (State.regs[dstreg] == 0);
905 n = (State.regs[dstreg] & 0x80000000) != 0;
906 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
907 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
910 // 1111 1001 1101 1001 Rm Rn; divu Rm,Rn
911 8.0xf9+8.0xd9+4.RM2,4.RN0:D1b:::divu
916 unsigned long long temp;
920 srcreg = translate_rreg (SD_, RM2);
921 dstreg = translate_rreg (SD_, RN0);
923 temp = State.regs[REG_MDR];
925 temp |= State.regs[dstreg];
926 State.regs[REG_MDR] = temp % State.regs[srcreg];
927 temp /= State.regs[srcreg];
928 State.regs[dstreg] = temp & 0xffffffff;
929 z = (State.regs[dstreg] == 0);
930 n = (State.regs[dstreg] & 0x80000000) != 0;
931 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
932 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
936 // 1111 1001 0000 1010 Rm Rn; mov (Rm),Rn
937 8.0xf9+8.0x0a+4.RN2,4.RM0:D1h:::mov
944 srcreg = translate_rreg (SD_, RM0);
945 dstreg = translate_rreg (SD_, RN2);
946 State.regs[dstreg] = load_word (State.regs[srcreg]);
949 // 1111 1001 0001 1010 Rm Rn; mov Rm,(Rn)
950 8.0xf9+8.0x1a+4.RM2,4.RN0:D1i:::mov
957 srcreg = translate_rreg (SD_, RM2);
958 dstreg = translate_rreg (SD_, RN0);
959 store_word (State.regs[dstreg], State.regs[srcreg]);
962 // 1111 1001 0010 1010 Rm Rn; movbu (Rm),Rn
963 8.0xf9+8.0x2a+4.RN2,4.RM0:D1g:::movbu
970 srcreg = translate_rreg (SD_, RM0);
971 dstreg = translate_rreg (SD_, RN2);
972 State.regs[dstreg] = load_byte (State.regs[srcreg]);
975 // 1111 1001 0011 1010 Rm Rn; movbu Rm,(Rn)
976 8.0xf9+8.0x3a+4.RM2,4.RN0:D1i:::movbu
983 srcreg = translate_rreg (SD_, RM2);
984 dstreg = translate_rreg (SD_, RN0);
985 store_byte (State.regs[dstreg], State.regs[srcreg]);
988 // 1111 1001 0100 1010 Rm Rn; movhu (Rm),Rn
989 8.0xf9+8.0x4a+4.RN2,4.RM0:D1g:::movhu
996 srcreg = translate_rreg (SD_, RM0);
997 dstreg = translate_rreg (SD_, RN2);
998 State.regs[dstreg] = load_half (State.regs[srcreg]);
1001 // 1111 1001 0101 1010 Rm Rn; movhu Rm,(Rn)
1002 8.0xf9+8.0x5a+4.RM2,4.RN0:D1i:::movhu
1009 srcreg = translate_rreg (SD_, RM2);
1010 dstreg = translate_rreg (SD_, RN0);
1011 store_half (State.regs[dstreg], State.regs[srcreg]);
1014 // 1111 1001 0110 1010 Rm Rn; mov (Rm+),Rn
1015 8.0xf9+8.0x6a+4.RN2,4.RM0!RN2:D1y:::mov
1022 srcreg = translate_rreg (SD_, RM0);
1023 dstreg = translate_rreg (SD_, RN2);
1024 State.regs[dstreg] = load_word (State.regs[srcreg]);
1025 State.regs[srcreg] += 4;
1028 // 1111 1001 0111 1010 Rm Rn; mov Rm,(Rn+)
1029 8.0xf9+8.0x7a+4.RM2,4.RN0!RM2:D1z:::mov
1036 srcreg = translate_rreg (SD_, RM2);
1037 dstreg = translate_rreg (SD_, RN0);
1038 store_word (State.regs[dstreg], State.regs[srcreg]);
1039 State.regs[dstreg] += 4;
1042 // 1111 1001 1000 1010 Rn 0000; mov (sp),Rn
1043 8.0xf9+8.0x8a+4.RN2,4.0000:D1j:::mov
1050 dstreg = translate_rreg (SD_, RN2);
1051 State.regs[dstreg] = load_word (State.regs[REG_SP]);
1054 // 1111 1001 1001 1010 Rm 0000; mov Rm, (sp)
1055 8.0xf9+8.0x9a+4.RM2,4.0000:D1k:::mov
1062 srcreg = translate_rreg (SD_, RM2);
1063 store_word (State.regs[REG_SP], State.regs[srcreg]);
1066 // 1111 1001 1010 1010 Rn 0000; mobvu (sp),Rn
1067 8.0xf9+8.0xaa+4.RN2,4.0000:D1j:::movbu
1074 dstreg = translate_rreg (SD_, RN2);
1075 State.regs[dstreg] = load_byte (State.regs[REG_SP]);
1078 // 1111 1001 1011 1010 Rm 0000; movbu Rm, (sp)
1079 8.0xf9+8.0xba+4.RM2,4.0000:D1k:::movbu
1086 srcreg = translate_rreg (SD_, RM2);
1087 store_byte (State.regs[REG_SP], State.regs[srcreg]);
1090 // 1111 1001 1000 1100 Rn 0000; movhu (sp),Rn
1091 8.0xf9+8.0xca+4.RN2,4.0000:D1j:::movhu
1098 dstreg = translate_rreg (SD_, RN2);
1099 State.regs[dstreg] = load_half (State.regs[REG_SP]);
1102 // 1111 1001 1001 1101 Rm 0000; movhu Rm, (sp)
1103 8.0xf9+8.0xda+4.RM2,4.0000:D1k:::movhu
1110 srcreg = translate_rreg (SD_, RM2);
1111 store_half (State.regs[REG_SP], State.regs[srcreg]);
1114 // 1111 1001 1110 1010 Rm Rn; movhu (Rm+),Rn
1115 8.0xf9+8.0xea+4.RN2,4.RM0!RN2:D1y:::movhu
1122 srcreg = translate_rreg (SD_, RM0);
1123 dstreg = translate_rreg (SD_, RN2);
1124 State.regs[dstreg] = load_half (State.regs[srcreg]);
1125 State.regs[srcreg] += 2;
1128 // 1111 1001 1111 1010 Rm Rn; movhu Rm,(Rn+)
1129 8.0xf9+8.0xfa+4.RM2,4.RN0!RM2:D1z:::movhu
1136 srcreg = translate_rreg (SD_, RM2);
1137 dstreg = translate_rreg (SD_, RN0);
1138 store_half (State.regs[dstreg], State.regs[srcreg]);
1139 State.regs[dstreg] += 2;
1143 // 1111 1001 0000 1011 Rm Rn; mac Rm,Rn
1144 8.0xf9+8.0x0b+4.RM2,4.RN0:D1:::mac
1148 int srcreg1, srcreg2;
1149 long long temp, sum;
1153 srcreg1 = translate_rreg (SD_, RM2);
1154 srcreg2 = translate_rreg (SD_, RN0);
1156 temp = ((signed64)(signed32)State.regs[srcreg2]
1157 * (signed64)(signed32)State.regs[srcreg1]);
1158 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1159 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1160 State.regs[REG_MCRL] = sum;
1163 sum = State.regs[REG_MCRH] + temp + c;
1164 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1165 && (temp & 0x80000000) != (sum & 0x80000000));
1166 State.regs[REG_MCRH] = sum;
1168 State.regs[REG_MCVF] = 1;
1171 // 1111 1001 0001 1011 Rm Rn; macu Rm,Rn
1172 8.0xf9+8.0x1b+4.RM2,4.RN0:D1:::macu
1176 int srcreg1, srcreg2;
1177 unsigned long long temp, sum;
1181 srcreg1 = translate_rreg (SD_, RM2);
1182 srcreg2 = translate_rreg (SD_, RN0);
1184 temp = ((unsigned64)State.regs[srcreg2]
1185 * (unsigned64)State.regs[srcreg1]);
1186 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1187 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1188 State.regs[REG_MCRL] = sum;
1191 sum = State.regs[REG_MCRH] + temp + c;
1192 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1193 && (temp & 0x80000000) != (sum & 0x80000000));
1194 State.regs[REG_MCRH] = sum;
1196 State.regs[REG_MCVF] = 1;
1199 // 1111 1001 0010 1011 Rm Rn; macb Rm,Rn
1200 8.0xf9+8.0x2b+4.RM2,4.RN0:D1:::macb
1204 int srcreg1, srcreg2;
1209 srcreg1 = translate_rreg (SD_, RM2);
1210 srcreg2 = translate_rreg (SD_, RN0);
1212 temp = ((signed32)(signed8)(State.regs[srcreg2] & 0xff)
1213 * (signed32)(signed8)(State.regs[srcreg1] & 0xff));
1214 sum = State.regs[REG_MCRL] + temp;
1215 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1216 && (temp & 0x80000000) != (sum & 0x80000000));
1217 State.regs[REG_MCRL] = sum;
1219 State.regs[REG_MCVF] = 1;
1222 // 1111 1001 0011 1011 Rm Rn; macbu Rm,Rn
1223 8.0xf9+8.0x3b+4.RM2,4.RN0:D1:::macbu
1227 int srcreg1, srcreg2;
1228 long long temp, sum;
1232 srcreg1 = translate_rreg (SD_, RM2);
1233 srcreg2 = translate_rreg (SD_, RN0);
1235 temp = ((unsigned32)(State.regs[srcreg2] & 0xff)
1236 * (unsigned32)(State.regs[srcreg1] & 0xff));
1237 sum = State.regs[REG_MCRL] + temp;
1238 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1239 && (temp & 0x80000000) != (sum & 0x80000000));
1240 State.regs[REG_MCRL] = sum;
1242 State.regs[REG_MCVF] = 1;
1245 // 1111 1001 0100 1011 Rm Rn; mach Rm,Rn
1246 8.0xf9+8.0x4b+4.RM2,4.RN0:D1:::mach
1250 int srcreg1, srcreg2;
1251 long long temp, sum;
1255 srcreg1 = translate_rreg (SD_, RM2);
1256 srcreg2 = translate_rreg (SD_, RN0);
1258 temp = ((unsigned64)(signed16)(State.regs[srcreg2] & 0xffff)
1259 * (unsigned64)(signed16)(State.regs[srcreg1] & 0xffff));
1260 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1261 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1262 State.regs[REG_MCRL] = sum;
1265 sum = State.regs[REG_MCRH] + temp + c;
1266 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1267 && (temp & 0x80000000) != (sum & 0x80000000));
1268 State.regs[REG_MCRH] = sum;
1270 State.regs[REG_MCVF] = 1;
1273 // 1111 1001 0101 1011 Rm Rn; machu Rm,Rn
1274 8.0xf9+8.0x5b+4.RM2,4.RN0:D1:::machu
1278 int srcreg1, srcreg2;
1279 long long temp, sum;
1283 srcreg1 = translate_rreg (SD_, RM2);
1284 srcreg2 = translate_rreg (SD_, RN0);
1286 temp = ((unsigned64)(State.regs[srcreg2] & 0xffff)
1287 * (unsigned64)(State.regs[srcreg1] & 0xffff));
1288 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1289 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1290 State.regs[REG_MCRL] = sum;
1293 sum = State.regs[REG_MCRH] + temp + c;
1294 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1295 && (temp & 0x80000000) != (sum & 0x80000000));
1296 State.regs[REG_MCRH] = sum;
1298 State.regs[REG_MCVF] = 1;
1301 // 1111 1001 0110 1011 Rm Rn; dmach Rm,Rn
1302 8.0xf9+8.0x6b+4.RM2,4.RN0:D1:::dmach
1306 int srcreg1, srcreg2;
1307 long temp, temp2, sum;
1311 srcreg1 = translate_rreg (SD_, RM2);
1312 srcreg2 = translate_rreg (SD_, RN0);
1314 temp = ((signed32)(signed16)(State.regs[srcreg2] & 0xffff)
1315 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
1316 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
1317 * (signed32)(signed16)((State.regs[srcreg2] >> 16) & 0xffff));
1318 sum = temp + temp2 + State.regs[REG_MCRL];
1319 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1320 && (temp & 0x80000000) != (sum & 0x80000000));
1321 State.regs[REG_MCRL] = sum;
1323 State.regs[REG_MCVF] = 1;
1326 // 1111 1001 0111 1011 Rm Rn; dmachu Rm,Rn
1327 8.0xf9+8.0x7b+4.RM2,4.RN0:D1:::dmachu
1331 int srcreg1, srcreg2;
1332 unsigned long temp, temp2, sum;
1336 srcreg1 = translate_rreg (SD_, RM2);
1337 srcreg2 = translate_rreg (SD_, RN0);
1339 temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
1340 * (unsigned32)(State.regs[srcreg1] & 0xffff));
1341 temp2 = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
1342 * (unsigned32)((State.regs[srcreg2] >> 16) & 0xffff));
1343 sum = temp + temp2 + State.regs[REG_MCRL];
1344 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1345 && (temp & 0x80000000) != (sum & 0x80000000));
1346 State.regs[REG_MCRL] = sum;
1348 State.regs[REG_MCVF] = 1;
1351 // 1111 1001 1000 1011 Rm Rn; dmulh Rm,Rn
1352 8.0xf9+8.0x8b+4.RM2,4.RN0:D1:::dmulh
1360 srcreg = translate_rreg (SD_, RM2);
1361 dstreg = translate_rreg (SD_, RN0);
1363 temp = ((signed32)(signed16)(State.regs[dstreg] & 0xffff)
1364 * (signed32)(signed16)(State.regs[srcreg] & 0xffff));
1365 State.regs[REG_MDRQ] = temp;
1366 temp = ((signed32)(signed16)((State.regs[dstreg] >> 16) & 0xffff)
1367 * (signed32)(signed16)((State.regs[srcreg] >>16) & 0xffff));
1368 State.regs[dstreg] = temp;
1371 // 1111 1001 1001 1011 Rm Rn; dmulhu Rm,Rn
1372 8.0xf9+8.0x9b+4.RM2,4.RN0:D1:::dumachu
1380 srcreg = translate_rreg (SD_, RM2);
1381 dstreg = translate_rreg (SD_, RN0);
1383 temp = ((unsigned32)(State.regs[dstreg] & 0xffff)
1384 * (unsigned32)(State.regs[srcreg] & 0xffff));
1385 State.regs[REG_MDRQ] = temp;
1386 temp = ((unsigned32)((State.regs[dstreg] >> 16) & 0xffff)
1387 * (unsigned32)((State.regs[srcreg] >>16) & 0xffff));
1388 State.regs[dstreg] = temp;
1391 // 1111 1001 1010 1011 Rm Rn; sat16 Rm,Rn
1392 8.0xf9+8.0xab+4.RM2,4.RN0:D1:::sat16
1400 srcreg = translate_rreg (SD_, RM2);
1401 dstreg = translate_rreg (SD_, RN0);
1403 value = State.regs[srcreg];
1405 if (value >= 0x7fff)
1406 State.regs[dstreg] = 0x7fff;
1407 else if (value <= 0xffff8000)
1408 State.regs[dstreg] = 0xffff8000;
1410 State.regs[dstreg] = value;
1412 n = (State.regs[dstreg] & 0x8000) != 0;
1413 z = (State.regs[dstreg] == 0);
1414 PSW &= ~(PSW_Z | PSW_N);
1415 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1418 // 1111 1001 1011 1011 Rm Rn; mcste Rm,Rn
1419 8.0xf9+8.0xbb+4.RM2,4.RN0:D1:::mcste
1426 srcreg = translate_rreg (SD_, RM2);
1427 dstreg = translate_rreg (SD_, RN0);
1429 PSW &= ~(PSW_V | PSW_C);
1430 PSW |= (State.regs[REG_MCVF] ? PSW_V : 0);
1432 /* 32bit saturation. */
1433 if (State.regs[srcreg] == 0x20)
1437 tmp = State.regs[REG_MCRH];
1439 tmp += State.regs[REG_MCRL];
1441 if (tmp > 0x7fffffff)
1442 State.regs[dstreg] = 0x7fffffff;
1443 else if (tmp < 0xffffffff80000000LL)
1444 State.regs[dstreg] = 0x80000000;
1446 State.regs[dstreg] = tmp;
1448 /* 16bit saturation */
1449 else if (State.regs[srcreg] == 0x10)
1453 tmp = State.regs[REG_MCRH];
1455 tmp += State.regs[REG_MCRL];
1458 State.regs[dstreg] = 0x7fff;
1459 else if (tmp < 0xffffffffffff8000LL)
1460 State.regs[dstreg] = 0x8000;
1462 State.regs[dstreg] = tmp;
1464 /* 8 bit saturation */
1465 else if (State.regs[srcreg] == 0x8)
1469 tmp = State.regs[REG_MCRH];
1471 tmp += State.regs[REG_MCRL];
1474 State.regs[dstreg] = 0x7f;
1475 else if (tmp < 0xffffffffffffff80LL)
1476 State.regs[dstreg] = 0x80;
1478 State.regs[dstreg] = tmp;
1480 /* 9 bit saturation */
1481 else if (State.regs[srcreg] == 0x9)
1485 tmp = State.regs[REG_MCRH];
1487 tmp += State.regs[REG_MCRL];
1490 State.regs[dstreg] = 0x80;
1491 else if (tmp < 0xffffffffffffff81LL)
1492 State.regs[dstreg] = 0x81;
1494 State.regs[dstreg] = tmp;
1496 /* 9 bit saturation */
1497 else if (State.regs[srcreg] == 0x30)
1501 tmp = State.regs[REG_MCRH];
1503 tmp += State.regs[REG_MCRL];
1505 if (tmp > 0x7fffffffffffLL)
1506 tmp = 0x7fffffffffffLL;
1507 else if (tmp < 0xffff800000000000LL)
1508 tmp = 0xffff800000000000LL;
1511 State.regs[dstreg] = tmp;
1515 // 1111 1001 1100 1011 Rm Rn; swap Rm,Rn
1516 8.0xf9+8.0xcb+4.RM2,4.RN0:D1:::swap
1523 srcreg = translate_rreg (SD_, RM2);
1524 dstreg = translate_rreg (SD_, RN0);
1526 State.regs[dstreg] = (((State.regs[srcreg] & 0xff) << 24)
1527 | (((State.regs[srcreg] >> 8) & 0xff) << 16)
1528 | (((State.regs[srcreg] >> 16) & 0xff) << 8)
1529 | ((State.regs[srcreg] >> 24) & 0xff));
1532 // 1111 1101 1101 1011 Rm Rn; swaph Rm,Rn
1533 8.0xf9+8.0xdb+4.RM2,4.RN0:D1:::swaph
1540 srcreg = translate_rreg (SD_, RM2);
1541 dstreg = translate_rreg (SD_, RN0);
1543 State.regs[dstreg] = (((State.regs[srcreg] & 0xff) << 8)
1544 | ((State.regs[srcreg] >> 8) & 0xff)
1545 | (((State.regs[srcreg] >> 16) & 0xff) << 24)
1546 | (((State.regs[srcreg] >> 24) & 0xff) << 16));
1549 // 1111 1001 1110 1011 Rm Rn; swhw Rm,Rn
1550 8.0xf9+8.0xeb+4.RM2,4.RN0:D1:::swhw
1557 srcreg = translate_rreg (SD_, RM2);
1558 dstreg = translate_rreg (SD_, RN0);
1560 State.regs[dstreg] = (((State.regs[srcreg] & 0xffff) << 16)
1561 | ((State.regs[srcreg] >> 16) & 0xffff));
1564 // 1111 1001 1111 1011 Rm Rn; bsch Rm,Rn
1565 8.0xf9+8.0xfb+4.RM2,4.RN0:D1:::bsch
1574 srcreg = translate_rreg (SD_, RM2);
1575 dstreg = translate_rreg (SD_, RN0);
1577 temp = State.regs[srcreg];
1578 start = (State.regs[dstreg] & 0x1f) - 1;
1582 for (i = start; i >= 0; i--)
1584 if (temp & (1 << i))
1587 State.regs[dstreg] = i;
1595 State.regs[dstreg] = 0;
1598 PSW |= (c ? PSW_C : 0);
1602 // 1111 1011 0000 1000 Rn Rn IMM8; mov IMM8,Rn
1603 8.0xfb+8.0x08+4.RM2,4.RN0=RM2+8.IMM8:D2j:::mov
1610 dstreg = translate_rreg (SD_, RN0);
1611 State.regs[dstreg] = EXTEND8 (IMM8);
1614 // 1111 1011 0001 1000 Rn Rn IMM8; movu IMM8,Rn
1615 8.0xfb+8.0x18+4.RM2,4.RN0=RM2+8.IMM8:D2:::movu
1622 dstreg = translate_rreg (SD_, RN0);
1623 State.regs[dstreg] = IMM8 & 0xff;
1626 // 1111 1011 0111 1000 Rn Rn IMM8; add IMM8,Rn
1627 8.0xfb+8.0x78+4.RM2,4.RN0=RM2+8.IMM8:D2d:::add
1634 dstreg = translate_rreg (SD_, RN0);
1635 genericAdd (EXTEND8 (IMM8), dstreg);
1638 // 1111 1011 1000 1000 Rn Rn IMM8; addc IMM8,Rn
1639 8.0xfb+8.0x88+4.RM2,4.RN0=RM2+8.IMM8:D2d:::addc
1645 unsigned long reg1, reg2, sum;
1648 dstreg = translate_rreg (SD_, RN0);
1650 imm = EXTEND8 (IMM8);
1651 reg2 = State.regs[dstreg];
1652 sum = imm + reg2 + ((PSW & PSW_C) != 0);
1653 State.regs[dstreg] = sum;
1655 z = ((PSW & PSW_Z) != 0) && (sum == 0);
1656 n = (sum & 0x80000000);
1657 c = (sum < imm) || (sum < reg2);
1658 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
1659 && (reg2 & 0x80000000) != (sum & 0x80000000));
1661 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1662 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1663 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1666 // 1111 1011 1001 1000 Rn Rn IMM8; sub IMM8,Rn
1667 8.0xfb+8.0x98+4.RM2,4.RN0=RM2+8.IMM8:D2d:::sub
1674 dstreg = translate_rreg (SD_, RN0);
1676 genericSub (EXTEND8 (IMM8), dstreg);
1679 // 1111 1011 1010 1000 Rn Rn IMM8; subc IMM8,Rn
1680 8.0xfb+8.0xa8+4.RM2,4.RN0=RM2+8.IMM8:D2d:::subc
1686 unsigned long reg1, reg2, difference;
1689 dstreg = translate_rreg (SD_, RN0);
1691 imm = EXTEND8 (IMM8);
1692 reg2 = State.regs[dstreg];
1693 difference = reg2 - imm - ((PSW & PSW_C) != 0);
1694 State.regs[dstreg] = difference;
1696 z = ((PSW & PSW_Z) != 0) && (difference == 0);
1697 n = (difference & 0x80000000);
1699 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
1700 && (reg2 & 0x80000000) != (difference & 0x80000000));
1702 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1703 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1704 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1707 // 1111 1011 1101 1000 Rn Rn IMM8; cmp IMM8,Rn
1708 8.0xfb+8.0xd8+4.RM2,4.RN0=RM2+8.IMM8:D2b:::cmp
1715 srcreg = translate_rreg (SD_, RN0);
1716 genericCmp (EXTEND8 (IMM8), State.regs[srcreg]);
1719 // 1111 1011 1111 1000 XRn XRn IMM8; mov IMM8,XRn
1720 8.0xfb+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM8:D2k:::mov
1727 dstreg = translate_xreg (SD_, XRN0);
1729 State.regs[dstreg] = IMM8;
1732 // 1111 1011 0000 1001 Rn Rn IMM8; and IMM8,Rn
1733 8.0xfb+8.0x09+4.RM2,4.RN0=RM2+8.IMM8:D2d:::and
1741 dstreg = translate_rreg (SD_, RN0);
1743 State.regs[dstreg] &= (IMM8 & 0xff);
1744 z = (State.regs[dstreg] == 0);
1745 n = (State.regs[dstreg] & 0x80000000) != 0;
1746 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1747 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1750 // 1111 1011 0001 1001 Rn Rn IMM8; or IMM8,Rn
1751 8.0xfb+8.0x19+4.RM2,4.RN0=RM2+8.IMM8:D2d:::or
1759 dstreg = translate_rreg (SD_, RN0);
1761 State.regs[dstreg] |= (IMM8 & 0xff);
1762 z = (State.regs[dstreg] == 0);
1763 n = (State.regs[dstreg] & 0x80000000) != 0;
1764 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1765 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1768 // 1111 1011 0010 1001 Rn Rn IMM8; xor IMM8,Rn
1769 8.0xfb+8.0x29+4.RM2,4.RN0=RM2+8.IMM8:D2d:::xor
1777 dstreg = translate_rreg (SD_, RN0);
1779 State.regs[dstreg] ^= (IMM8 & 0xff);
1780 z = (State.regs[dstreg] == 0);
1781 n = (State.regs[dstreg] & 0x80000000) != 0;
1782 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1783 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1786 // 1111 1011 0100 1001 Rn Rn IMM8; asr IMM8,Rn
1787 8.0xfb+8.0x49+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asr
1796 dstreg = translate_rreg (SD_, RN0);
1798 temp = State.regs[dstreg];
1800 temp >>= (IMM8 & 0xff);
1801 State.regs[dstreg] = temp;
1802 z = (State.regs[dstreg] == 0);
1803 n = (State.regs[dstreg] & 0x80000000) != 0;
1804 PSW &= ~(PSW_Z | PSW_N | PSW_C);
1805 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1808 // 1111 1011 0101 1001 Rn Rn IMM8; lsr IMM8,Rn
1809 8.0xfb+8.0x59+4.RM2,4.RN0=RM2+8.IMM8:D2a:::lsr
1817 dstreg = translate_rreg (SD_, RN0);
1819 c = State.regs[dstreg] & 1;
1820 State.regs[dstreg] >>= (IMM8 & 0xff);
1821 z = (State.regs[dstreg] == 0);
1822 n = (State.regs[dstreg] & 0x80000000) != 0;
1823 PSW &= ~(PSW_Z | PSW_N | PSW_C);
1824 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1827 // 1111 1011 0110 1001 Rn Rn IMM8; asl IMM8,Rn
1828 8.0xfb+8.0x69+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asl
1836 dstreg = translate_rreg (SD_, RN0);
1838 State.regs[dstreg] <<= (IMM8 & 0xff);
1839 z = (State.regs[dstreg] == 0);
1840 n = (State.regs[dstreg] & 0x80000000) != 0;
1841 PSW &= ~(PSW_Z | PSW_N);
1842 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1845 // 1111 1011 1010 1001 Rn Rn IMM8; mul IMM8,Rn
1846 8.0xfb+8.0xa9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mul
1851 unsigned long long temp;
1855 dstreg = translate_rreg (SD_, RN0);
1857 temp = ((signed64)(signed32)State.regs[dstreg]
1858 * (signed64)(signed32)EXTEND8 (IMM8));
1859 State.regs[dstreg] = temp & 0xffffffff;
1860 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
1861 z = (State.regs[dstreg] == 0);
1862 n = (State.regs[dstreg] & 0x80000000) != 0;
1863 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1864 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1867 // 1111 1011 1011 1001 Rn Rn IMM8; mulu IMM8,Rn
1868 8.0xfb+8.0xb9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mulu
1873 unsigned long long temp;
1877 dstreg = translate_rreg (SD_, RN0);
1879 temp = ((unsigned64)State.regs[dstreg]
1880 * (unsigned64)(IMM8 & 0xff));
1881 State.regs[dstreg] = temp & 0xffffffff;
1882 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
1883 z = (State.regs[dstreg] == 0);
1884 n = (State.regs[dstreg] & 0x80000000) != 0;
1885 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1886 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1889 // 1111 1011 1110 1001 Rn Rn IMM8; btst imm8,Rn
1890 8.0xfb+8.0xe9+4.RN2,4.RM0=RN2+8.IMM8:D2l:::btst
1897 srcreg = translate_rreg (SD_, RM0);
1898 genericBtst(IMM8, State.regs[srcreg]);
1901 // 1111 1011 0000 1010 Rn Rm IMM8; mov (d8,Rm),Rn
1902 8.0xfb+8.0x0a+4.RN2,4.RM0+8.IMM8:D2l:::mov
1909 srcreg = translate_rreg (SD_, RM0);
1910 dstreg = translate_rreg (SD_, RN2);
1911 State.regs[dstreg] = load_word (State.regs[srcreg] + EXTEND8 (IMM8));
1914 // 1111 1011 0001 1010 Rn Rm IMM8; mov Rm,(d8,Rn)
1915 8.0xfb+8.0x1a+4.RM2,4.RN0+8.IMM8:D2m:::mov
1921 srcreg = translate_rreg (SD_, RM2);
1922 dstreg = translate_rreg (SD_, RN0);
1923 store_word (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1926 // 1111 1011 0010 1010 Rn Rm IMM8; movbu (d8,Rm),Rn
1927 8.0xfb+8.0x2a+4.RN2,4.RM0+8.IMM8:D2l:::movbu
1933 srcreg = translate_rreg (SD_, RM0);
1934 dstreg = translate_rreg (SD_, RN2);
1935 State.regs[dstreg] = load_byte (State.regs[srcreg] + EXTEND8 (IMM8));
1938 // 1111 1011 0011 1010 Rn Rm IMM8; movbu Rm,(d8,Rn)
1939 8.0xfb+8.0x3a+4.RM2,4.RN0+8.IMM8:D2m:::movbu
1945 srcreg = translate_rreg (SD_, RM2);
1946 dstreg = translate_rreg (SD_, RN0);
1947 store_byte (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1950 // 1111 1011 0100 1010 Rn Rm IMM8; movhu (d8,Rm),Rn
1951 8.0xfb+8.0x4a+4.RN2,4.RM0+8.IMM8:D2l:::movhu
1957 srcreg = translate_rreg (SD_, RM0);
1958 dstreg = translate_rreg (SD_, RN2);
1959 State.regs[dstreg] = load_half (State.regs[srcreg] + EXTEND8 (IMM8));
1962 // 1111 1011 0101 1010 Rn Rm IMM8; movhu Rm,(d8,Rn)
1963 8.0xfb+8.0x5a+4.RM2,4.RN0+8.IMM8:D2m:::movhu
1969 srcreg = translate_rreg (SD_, RM2);
1970 dstreg = translate_rreg (SD_, RN0);
1971 store_half (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1974 // 1111 1011 0110 1010 Rn Rm IMM8; mov (d8,Rm+),Rn
1975 8.0xfb+8.0x6a+4.RN2,4.RM0!RN2+8.IMM8:D2y:::mov
1982 srcreg = translate_rreg (SD_, RM0);
1983 dstreg = translate_rreg (SD_, RN2);
1984 State.regs[dstreg] = load_word (State.regs[srcreg]);
1985 State.regs[srcreg] += EXTEND8 (IMM8);
1988 // 1111 1011 0111 1010 Rn Rm IMM8; mov Rm,(d8,Rn+)
1989 8.0xfb+8.0x7a+4.RM2,4.RN0!RM2+8.IMM8:D2z:::mov
1995 srcreg = translate_rreg (SD_, RM2);
1996 dstreg = translate_rreg (SD_, RN0);
1997 store_word (State.regs[dstreg], State.regs[srcreg]);
1998 State.regs[dstreg] += EXTEND8 (IMM8);
2002 // 1111 1011 1000 1010 Rn 0000 IMM8; mov (d8,sp),Rn
2003 8.0xfb+8.0x8a+4.RN2,4.0x0+8.IMM8:D2n:::mov
2009 dstreg = translate_rreg (SD_, RN2);
2010 State.regs[dstreg] = load_word (State.regs[REG_SP] + EXTEND8 (IMM8));
2013 // 1111 1011 1001 1010 Rm 0000 IMM8; mov Rm,(d8,Rn)
2014 8.0xfb+8.0x9a+4.RM2,4.0x0+8.IMM8:D2o:::mov
2020 srcreg = translate_rreg (SD_, RM2);
2021 store_word (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
2024 // 1111 1011 1010 1010 Rn Rm IMM8; movbu (d8,sp),Rn
2025 8.0xfb+8.0xaa+4.RN2,4.0x0+8.IMM8:D2n:::movbu
2031 dstreg = translate_rreg (SD_, RN2);
2032 State.regs[dstreg] = load_byte (State.regs[REG_SP] + EXTEND8 (IMM8));
2035 // 1111 1011 1011 1010 Rn Rm IMM8; movbu Rm,(sp,Rn)
2036 8.0xfb+8.0xba+4.RM2,4.0x0+8.IMM8:D2o:::movbu
2042 srcreg = translate_rreg (SD_, RM2);
2043 store_byte (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
2046 // 1111 1011 1100 1010 Rn Rm IMM8; movhu (d8,sp),Rn
2047 8.0xfb+8.0xca+4.RN2,4.0x0+8.IMM8:D2n:::movhu
2053 dstreg = translate_rreg (SD_, RN2);
2054 State.regs[dstreg] = load_half (State.regs[REG_SP] + EXTEND8 (IMM8));
2057 // 1111 1011 1101 1010 Rn Rm IMM8; movhu Rm,(d8,sp)
2058 8.0xfb+8.0xda+4.RM2,4.0x0+8.IMM8:D2o:::movhu
2064 srcreg = translate_rreg (SD_, RM2);
2065 store_half (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
2068 // 1111 1011 1110 1010 Rn Rm IMM8; movhu (d8,Rm+),Rn
2069 8.0xfb+8.0xea+4.RN2,4.RM0!RN2+8.IMM8:D2y:::movhu
2076 srcreg = translate_rreg (SD_, RM0);
2077 dstreg = translate_rreg (SD_, RN2);
2078 State.regs[dstreg] = load_half (State.regs[srcreg]);
2079 State.regs[srcreg] += EXTEND8 (IMM8);
2082 // 1111 1011 1111 1010 Rn Rm IMM8; movhu Rm,(d8,Rn+)
2083 8.0xfb+8.0xfa+4.RM2,4.RN0!RM2+8.IMM8:D2z:::movhu
2089 srcreg = translate_rreg (SD_, RM2);
2090 dstreg = translate_rreg (SD_, RN0);
2091 store_half (State.regs[dstreg], State.regs[srcreg]);
2092 State.regs[dstreg] += EXTEND8 (IMM8);
2096 // 1111 1011 0000 1011 Rn Rn IMM8; mac imm8,Rn
2097 8.0xfb+8.0x0b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mac
2101 long long temp, sum;
2105 srcreg = translate_rreg (SD_, RN2);
2107 temp = ((signed64)(signed32)EXTEND8 (IMM8)
2108 * (signed64)(signed32)State.regs[srcreg]);
2109 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2110 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2111 State.regs[REG_MCRL] = sum;
2114 sum = State.regs[REG_MCRH] + temp + c;
2115 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2116 && (temp & 0x80000000) != (sum & 0x80000000));
2117 State.regs[REG_MCRH] = sum;
2119 State.regs[REG_MCVF] = 1;
2122 // 1111 1011 0001 1011 Rn Rn IMM8; macu imm8,Rn
2123 8.0xfb+8.0x1b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macu
2127 long long temp, sum;
2131 srcreg = translate_rreg (SD_, RN2);
2133 temp = ((unsigned64) (IMM8)
2134 * (unsigned64)State.regs[srcreg]);
2135 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2136 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2137 State.regs[REG_MCRL] = sum;
2140 sum = State.regs[REG_MCRH] + temp + c;
2141 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2142 && (temp & 0x80000000) != (sum & 0x80000000));
2143 State.regs[REG_MCRH] = sum;
2145 State.regs[REG_MCVF] = 1;
2148 // 1111 1011 0010 1011 Rn Rn IMM8; macb imm8,Rn
2149 8.0xfb+8.0x2b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macb
2153 long long temp, sum;
2157 srcreg = translate_rreg (SD_, RN2);
2159 temp = ((signed64)(signed8)EXTEND8 (IMM8)
2160 * (signed64)(signed8)State.regs[srcreg] & 0xff);
2161 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2162 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2163 State.regs[REG_MCRL] = sum;
2166 sum = State.regs[REG_MCRH] + temp + c;
2167 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2168 && (temp & 0x80000000) != (sum & 0x80000000));
2169 State.regs[REG_MCRH] = sum;
2171 State.regs[REG_MCVF] = 1;
2174 // 1111 1011 0011 1011 Rn Rn IMM8; macbu imm8,Rn
2175 8.0xfb+8.0x3b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macbu
2179 long long temp, sum;
2183 srcreg = translate_rreg (SD_, RN2);
2185 temp = ((unsigned64) (IMM8)
2186 * (unsigned64)State.regs[srcreg] & 0xff);
2187 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2188 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2189 State.regs[REG_MCRL] = sum;
2192 sum = State.regs[REG_MCRH] + temp + c;
2193 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2194 && (temp & 0x80000000) != (sum & 0x80000000));
2195 State.regs[REG_MCRH] = sum;
2197 State.regs[REG_MCVF] = 1;
2200 // 1111 1011 0100 1011 Rn Rn IMM8; mach imm8,Rn
2201 8.0xfb+8.0x4b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mach
2205 long long temp, sum;
2209 srcreg = translate_rreg (SD_, RN2);
2211 temp = ((signed64)(signed16)EXTEND8 (IMM8)
2212 * (signed64)(signed16)State.regs[srcreg] & 0xffff);
2213 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2214 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2215 State.regs[REG_MCRL] = sum;
2218 sum = State.regs[REG_MCRH] + temp + c;
2219 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2220 && (temp & 0x80000000) != (sum & 0x80000000));
2221 State.regs[REG_MCRH] = sum;
2223 State.regs[REG_MCVF] = 1;
2226 // 1111 1011 0101 1011 Rn Rn IMM8; machu imm8,Rn
2227 8.0xfb+8.0x5b+4.RN2,4.RN0=RN2+8.IMM8:D2:::machu
2231 long long temp, sum;
2235 srcreg = translate_rreg (SD_, RN2);
2237 temp = ((unsigned64) (IMM8)
2238 * (unsigned64)State.regs[srcreg] & 0xffff);
2239 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2240 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2241 State.regs[REG_MCRL] = sum;
2244 sum = State.regs[REG_MCRH] + temp + c;
2245 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2246 && (temp & 0x80000000) != (sum & 0x80000000));
2247 State.regs[REG_MCRH] = sum;
2249 State.regs[REG_MCVF] = 1;
2252 // 1111 1011 1011 1011 Rn Rn IMM8; mcste imm8,Rn
2253 8.0xfb+8.0xbb+4.RN2,4.RN0=RN2+8.IMM8:D2:::mcste
2259 dstreg = translate_rreg (SD_, RN0);
2261 PSW &= ~(PSW_V | PSW_C);
2262 PSW |= (State.regs[REG_MCVF] ? PSW_V : 0);
2264 /* 32bit saturation. */
2269 tmp = State.regs[REG_MCRH];
2271 tmp += State.regs[REG_MCRL];
2273 if (tmp > 0x7fffffff)
2274 State.regs[dstreg] = 0x7fffffff;
2275 else if (tmp < 0xffffffff80000000LL)
2276 State.regs[dstreg] = 0x80000000;
2278 State.regs[dstreg] = tmp;
2280 /* 16bit saturation */
2281 else if (IMM8 == 0x10)
2285 tmp = State.regs[REG_MCRH];
2287 tmp += State.regs[REG_MCRL];
2290 State.regs[dstreg] = 0x7fff;
2291 else if (tmp < 0xffffffffffff8000LL)
2292 State.regs[dstreg] = 0x8000;
2294 State.regs[dstreg] = tmp;
2296 /* 8 bit saturation */
2297 else if (IMM8 == 0x8)
2301 tmp = State.regs[REG_MCRH];
2303 tmp += State.regs[REG_MCRL];
2306 State.regs[dstreg] = 0x7f;
2307 else if (tmp < 0xffffffffffffff80LL)
2308 State.regs[dstreg] = 0x80;
2310 State.regs[dstreg] = tmp;
2312 /* 9 bit saturation */
2313 else if (IMM8 == 0x9)
2317 tmp = State.regs[REG_MCRH];
2319 tmp += State.regs[REG_MCRL];
2322 State.regs[dstreg] = 0x80;
2323 else if (tmp < 0xffffffffffffff81LL)
2324 State.regs[dstreg] = 0x81;
2326 State.regs[dstreg] = tmp;
2328 /* 9 bit saturation */
2329 else if (IMM8 == 0x30)
2333 tmp = State.regs[REG_MCRH];
2335 tmp += State.regs[REG_MCRL];
2337 if (tmp > 0x7fffffffffffLL)
2338 tmp = 0x7fffffffffffLL;
2339 else if (tmp < 0xffff800000000000LL)
2340 tmp = 0xffff800000000000LL;
2343 State.regs[dstreg] = tmp;
2347 // 1111 1011 0111 1100 Rm Rn Rd; add Rm,Rn,Rd
2348 8.0xfb+8.0x7c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::add
2353 unsigned long sum, source1, source2;
2354 int srcreg1, srcreg2, dstreg;
2357 srcreg1 = translate_rreg (SD_, RM2);
2358 srcreg2 = translate_rreg (SD_, RN0);
2359 dstreg = translate_rreg (SD_, RD0);
2361 source1 = State.regs[srcreg1];
2362 source2 = State.regs[srcreg2];
2363 sum = source1 + source2;
2364 State.regs[dstreg] = sum;
2367 n = (sum & 0x80000000);
2368 c = (sum < source1) || (sum < source2);
2369 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2370 && (source1 & 0x80000000) != (sum & 0x80000000));
2372 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2373 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2374 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2377 // 1111 1011 1000 1100 Rm Rn Rd; addc Rm,Rn,Rd
2378 8.0xfb+8.0x8c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::addc
2383 unsigned long sum, source1, source2;
2384 int srcreg1, srcreg2, dstreg;
2387 srcreg1 = translate_rreg (SD_, RM2);
2388 srcreg2 = translate_rreg (SD_, RN0);
2389 dstreg = translate_rreg (SD_, RD0);
2391 source1 = State.regs[srcreg1];
2392 source2 = State.regs[srcreg2];
2393 sum = source1 + source2 + ((PSW & PSW_C) != 0);
2394 State.regs[dstreg] = sum;
2396 z = ((PSW & PSW_Z) != 0) && (sum == 0);
2397 n = (sum & 0x80000000);
2398 c = (sum < source1) || (sum < source2);
2399 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2400 && (source1 & 0x80000000) != (sum & 0x80000000));
2402 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2403 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2404 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2407 // 1111 1011 1001 1100 Rm Rn Rd; sub Rm,Rn,Rd
2408 8.0xfb+8.0x9c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::sub
2413 unsigned long difference, source1, source2;
2414 int srcreg1, srcreg2, dstreg;
2417 srcreg1 = translate_rreg (SD_, RM2);
2418 srcreg2 = translate_rreg (SD_, RN0);
2419 dstreg = translate_rreg (SD_, RD0);
2421 source1 = State.regs[srcreg1];
2422 source2 = State.regs[srcreg2];
2423 difference = source2 - source1;
2424 State.regs[dstreg] = difference;
2426 z = (difference == 0);
2427 n = (difference & 0x80000000);
2428 c = (source1 > source1);
2429 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2430 && (source1 & 0x80000000) != (difference & 0x80000000));
2432 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2433 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2434 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2437 // 1111 1011 1010 1100 Rm Rn Rd; subc Rm,Rn,Rd
2438 8.0xfb+8.0xac+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::subc
2443 unsigned long difference, source1, source2;
2444 int srcreg1, srcreg2, dstreg;
2447 srcreg1 = translate_rreg (SD_, RM2);
2448 srcreg2 = translate_rreg (SD_, RN0);
2449 dstreg = translate_rreg (SD_, RD0);
2451 source1 = State.regs[srcreg1];
2452 source2 = State.regs[srcreg2];
2453 difference = source2 - source1 - ((PSW & PSW_C) != 0);
2454 State.regs[dstreg] = difference;
2456 z = ((PSW & PSW_Z) != 0) && (difference == 0);
2457 n = (difference & 0x80000000);
2458 c = (source1 > source2);
2459 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2460 && (source1 & 0x80000000) != (difference & 0x80000000));
2462 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2463 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2464 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2467 // 1111 1011 0000 1101 Rm Rn Rd; and Rm,Rn,Rd
2468 8.0xfb+8.0x0d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::and
2473 int srcreg1, srcreg2, dstreg;
2476 srcreg1 = translate_rreg (SD_, RM2);
2477 srcreg2 = translate_rreg (SD_, RN0);
2478 dstreg = translate_rreg (SD_, RD0);
2480 State.regs[dstreg] = State.regs[srcreg1] & State.regs[srcreg2];
2482 z = (State.regs[dstreg] == 0);
2483 n = (State.regs[dstreg] & 0x80000000);
2485 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2486 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2489 // 1111 1011 0001 1101 Rm Rn Rd; or Rm,Rn,Rd
2490 8.0xfb+8.0x1d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::or
2495 int srcreg1, srcreg2, dstreg;
2498 srcreg1 = translate_rreg (SD_, RM2);
2499 srcreg2 = translate_rreg (SD_, RN0);
2500 dstreg = translate_rreg (SD_, RD0);
2502 State.regs[dstreg] = State.regs[srcreg1] | State.regs[srcreg2];
2504 z = (State.regs[dstreg] == 0);
2505 n = (State.regs[dstreg] & 0x80000000);
2507 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2508 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2511 // 1111 1011 0010 1101 Rm Rn Rd; xor Rm,Rn,Rd
2512 8.0xfb+8.0x2d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::xor
2517 int srcreg1, srcreg2, dstreg;
2520 srcreg1 = translate_rreg (SD_, RM2);
2521 srcreg2 = translate_rreg (SD_, RN0);
2522 dstreg = translate_rreg (SD_, RD0);
2524 State.regs[dstreg] = State.regs[srcreg1] ^ State.regs[srcreg2];
2526 z = (State.regs[dstreg] == 0);
2527 n = (State.regs[dstreg] & 0x80000000);
2529 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2530 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2533 // 1111 1011 0100 1101 Rm Rn Rd; asr Rm,Rn,Rd
2534 8.0xfb+8.0x4d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asr
2540 int srcreg1, srcreg2, dstreg;
2543 srcreg1 = translate_rreg (SD_, RM2);
2544 srcreg2 = translate_rreg (SD_, RN0);
2545 dstreg = translate_rreg (SD_, RD0);
2547 temp = State.regs[srcreg2];
2549 temp >>= State.regs[srcreg1];
2550 State.regs[dstreg] = temp;
2552 z = (State.regs[dstreg] == 0);
2553 n = (State.regs[dstreg] & 0x80000000);
2555 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2556 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2559 // 1111 1011 0101 1101 Rm Rn Rd; lsr Rm,Rn,Rd
2560 8.0xfb+8.0x5d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::lsr
2565 int srcreg1, srcreg2, dstreg;
2568 srcreg1 = translate_rreg (SD_, RM2);
2569 srcreg2 = translate_rreg (SD_, RN0);
2570 dstreg = translate_rreg (SD_, RD0);
2572 c = State.regs[srcreg2] & 1;
2573 State.regs[dstreg] = State.regs[srcreg2] >> State.regs[srcreg1];
2575 z = (State.regs[dstreg] == 0);
2576 n = (State.regs[dstreg] & 0x80000000);
2578 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2579 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2582 // 1111 1011 0110 1101 Rm Rn Rd; asl Rm,Rn,Rd
2583 8.0xfb+8.0x6d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asl
2588 int srcreg1, srcreg2, dstreg;
2591 srcreg1 = translate_rreg (SD_, RM2);
2592 srcreg2 = translate_rreg (SD_, RN0);
2593 dstreg = translate_rreg (SD_, RD0);
2595 State.regs[dstreg] = State.regs[srcreg2] << State.regs[srcreg1];;
2597 z = (State.regs[dstreg] == 0);
2598 n = (State.regs[dstreg] & 0x80000000);
2600 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2601 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2604 // 1111 1011 1010 1101 Rm Rn Rd1 Rd2; mul Rm,Rn,Rd1,Rd2
2605 8.0xfb+8.0xad+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mul
2609 int srcreg1, srcreg2, dstreg1, dstreg2;
2610 signed long long temp;
2614 srcreg1 = translate_rreg (SD_, RM2);
2615 srcreg2 = translate_rreg (SD_, RN0);
2616 dstreg1 = translate_rreg (SD_, RD0);
2617 dstreg2 = translate_rreg (SD_, RD2);
2619 temp = ((signed64)(signed32)State.regs[srcreg1]
2620 * (signed64)(signed32)State.regs[srcreg2]);
2621 State.regs[dstreg1] = temp & 0xffffffff;
2622 State.regs[dstreg2] = (temp & 0xffffffff00000000LL) >> 32;;
2624 z = (State.regs[dstreg1] == 0) && (State.regs[dstreg2] == 0);
2625 n = (State.regs[dstreg2] & 0x80000000);
2627 PSW &= ~(PSW_Z | PSW_N);
2628 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2631 // 1111 1011 1011 1101 Rm Rn Rd1 Rd2; mulu Rm,Rn,Rd1,Rd2
2632 8.0xfb+8.0xbd+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mulu
2636 int srcreg1, srcreg2, dstreg1, dstreg2;
2637 signed long long temp;
2641 srcreg1 = translate_rreg (SD_, RM2);
2642 srcreg2 = translate_rreg (SD_, RN0);
2643 dstreg1 = translate_rreg (SD_, RD0);
2644 dstreg2 = translate_rreg (SD_, RD2);
2646 temp = ((unsigned64)State.regs[srcreg1]
2647 * (unsigned64)State.regs[srcreg2]);
2648 State.regs[dstreg1] = temp & 0xffffffff;
2649 State.regs[dstreg2] = (temp & 0xffffffff00000000LL) >> 32;;
2651 z = (State.regs[dstreg1] == 0) && (State.regs[dstreg2] == 0);
2652 n = (State.regs[dstreg2] & 0x80000000);
2654 PSW &= ~(PSW_Z | PSW_N);
2655 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2658 // 1111 1011 0000 1110 Rn 0000 abs8 ; mov (abs8),Rn
2659 8.0xfb+8.0x0e+4.RN2,4.0x0+8.IMM8:D2p:::mov
2666 dstreg = translate_rreg (SD_, RN2);
2667 State.regs[dstreg] = load_word (IMM8);
2670 // 1111 1011 0001 1110 Rm 0000 abs8 ; mov Rn,(abs8)
2671 8.0xfb+8.0x1e+4.RM2,4.0x0+8.IMM8:D2q:::mov
2678 srcreg = translate_rreg (SD_, RM2);
2679 store_word (IMM8, State.regs[srcreg]);
2682 // 1111 1011 0010 1110 Rn 0000 abs8 ; movbu (abs8),Rn
2683 8.0xfb+8.0x2e+4.RN2,4.0x0+8.IMM8:D2p:::movbu
2690 dstreg = translate_rreg (SD_, RN2);
2691 State.regs[dstreg] = load_byte (IMM8);
2694 // 1111 1011 0011 1110 Rm 0000 abs8 ; movbu Rn,(abs8)
2695 8.0xfb+8.0x3e+4.RM2,4.0x0+8.IMM8:D2q:::movbu
2702 srcreg = translate_rreg (SD_, RM2);
2703 store_byte (IMM8, State.regs[srcreg]);
2706 // 1111 1011 0100 1110 Rn 0000 abs8 ; movhu (abs8),Rn
2707 8.0xfb+8.0x4e+4.RN2,4.0x0+8.IMM8:D2p:::movhu
2714 dstreg = translate_rreg (SD_, RN2);
2715 State.regs[dstreg] = load_half (IMM8);
2718 // 1111 1011 0101 1110 Rm 0000 abs8 ; movhu Rn,(abs8)
2719 8.0xfb+8.0x5e+4.RM2,4.0x0+8.IMM8:D2q:::movhu
2726 srcreg = translate_rreg (SD_, RM2);
2727 store_half (IMM8, State.regs[srcreg]);
2730 // 1111 1011 1000 1110 Ri Rm Rn; mov (Ri,Rm),Rn
2731 8.0xfb+8.0x8e+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::mov
2735 int srcreg1, srcreg2, dstreg;
2738 srcreg1 = translate_rreg (SD_, RM0);
2739 srcreg1 = translate_rreg (SD_, RI0);
2740 dstreg = translate_rreg (SD_, RN0);
2741 State.regs[dstreg] = load_word (State.regs[srcreg1] + State.regs[srcreg2]);
2744 // 1111 1011 1001 1110 Ri Rm Rn; mov Rn,(Ri,Rm)
2745 8.0xfb+8.0x9e+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::mov
2749 int srcreg, dstreg1, dstreg2;
2752 srcreg = translate_rreg (SD_, RM0);
2753 dstreg1 = translate_rreg (SD_, RI0);
2754 dstreg2 = translate_rreg (SD_, RN0);
2755 store_word (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
2758 // 1111 1011 1010 1110 Ri Rm Rn; movbu (Ri,Rm),Rn
2759 8.0xfb+8.0xae+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movbu
2763 int srcreg1, srcreg2, dstreg;
2766 srcreg1 = translate_rreg (SD_, RM0);
2767 srcreg1 = translate_rreg (SD_, RI0);
2768 dstreg = translate_rreg (SD_, RN0);
2769 State.regs[dstreg] = load_byte (State.regs[srcreg1] + State.regs[srcreg2]);
2772 // 1111 1011 1011 1110 Ri Rm Rn; movbu Rn,(Ri,Rm)
2773 8.0xfb+8.0xbe+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movbu
2777 int srcreg, dstreg1, dstreg2;
2780 srcreg = translate_rreg (SD_, RM0);
2781 dstreg1 = translate_rreg (SD_, RI0);
2782 dstreg2 = translate_rreg (SD_, RN0);
2783 store_byte (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
2786 // 1111 1011 1100 1110 Ri Rm Rn; movhu (Ri,Rm),Rn
2787 8.0xfb+8.0xce+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movhu
2791 int srcreg1, srcreg2, dstreg;
2794 srcreg1 = translate_rreg (SD_, RM0);
2795 srcreg1 = translate_rreg (SD_, RI0);
2796 dstreg = translate_rreg (SD_, RN0);
2797 State.regs[dstreg] = load_half (State.regs[srcreg1] + State.regs[srcreg2]);
2800 // 1111 1011 1101 1110 Ri Rm Rn; movhu Rn,(Ri,Rm)
2801 8.0xfb+8.0xde+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movhu
2805 int srcreg, dstreg1, dstreg2;
2808 srcreg = translate_rreg (SD_, RM0);
2809 dstreg1 = translate_rreg (SD_, RI0);
2810 dstreg2 = translate_rreg (SD_, RN0);
2811 store_half (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
2814 // 1111 1011 0000 1111 Rm Rn Rd1 Rd2; mac Rm,Rn,Rd1,Rd2
2815 8.0xfb+8.0x0f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mac
2819 int srcreg1, srcreg2, dstreg1, dstreg2;
2820 signed long long temp;
2825 srcreg1 = translate_rreg (SD_, RM2);
2826 srcreg2 = translate_rreg (SD_, RN0);
2827 dstreg1 = translate_rreg (SD_, RD0);
2828 dstreg2 = translate_rreg (SD_, RD2);
2830 temp = ((signed64)(signed32)State.regs[srcreg1]
2831 * (signed64)(signed32)State.regs[srcreg2]);
2833 sum = State.regs[dstreg2] + (temp & 0xffffffff);
2834 c = (sum < State.regs[dstreg2]) || (sum < (temp & 0xffffffff));
2835 State.regs[dstreg2] = sum;
2838 sum = State.regs[dstreg1] + temp + c;
2839 v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
2840 && (temp & 0x80000000) != (sum & 0x80000000));
2841 State.regs[dstreg1] = sum;
2844 State.regs[REG_MCVF] = 1;
2846 PSW |= (( v ? PSW_V : 0));
2850 // 1111 1011 0001 1111 Rm Rn Rd1 Rd2; macu Rm,Rn,Rd1,Rd2
2851 8.0xfb+8.0x1f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::macu
2855 int srcreg1, srcreg2, dstreg1, dstreg2;
2856 signed long long temp;
2861 srcreg1 = translate_rreg (SD_, RM2);
2862 srcreg2 = translate_rreg (SD_, RN0);
2863 dstreg1 = translate_rreg (SD_, RD0);
2864 dstreg2 = translate_rreg (SD_, RD2);
2866 temp = ((unsigned64)State.regs[srcreg1]
2867 * (unsigned64)State.regs[srcreg2]);
2869 sum = State.regs[dstreg2] + (temp & 0xffffffff);
2870 c = (sum < State.regs[dstreg2]) || (sum < (temp & 0xffffffff));
2871 State.regs[dstreg2] = sum;
2874 sum = State.regs[dstreg1] + temp + c;
2875 v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
2876 && (temp & 0x80000000) != (sum & 0x80000000));
2877 State.regs[dstreg1] = sum;
2880 State.regs[REG_MCVF] = 1;
2882 PSW |= (( v ? PSW_V : 0));
2886 // 1111 1011 0010 1111 Rm Rn Rd1; macb Rm,Rn,Rd1
2887 8.0xfb+8.0x2f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macb
2891 int srcreg1, srcreg2, dstreg;
2896 srcreg1 = translate_rreg (SD_, RM2);
2897 srcreg2 = translate_rreg (SD_, RN0);
2898 dstreg = translate_rreg (SD_, RD0);
2900 temp = ((signed32)(State.regs[srcreg2] & 0xff)
2901 * (signed32)(State.regs[srcreg1] & 0xff));
2902 sum = State.regs[dstreg] + temp;
2903 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2904 && (temp & 0x80000000) != (sum & 0x80000000));
2905 State.regs[dstreg] = sum;
2908 State.regs[REG_MCVF] = 1;
2910 PSW |= ((v ? PSW_V : 0));
2914 // 1111 1011 0011 1111 Rm Rn Rd1; macbu Rm,Rn,Rd1
2915 8.0xfb+8.0x3f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macbu
2919 int srcreg1, srcreg2, dstreg;
2924 srcreg1 = translate_rreg (SD_, RM2);
2925 srcreg2 = translate_rreg (SD_, RN0);
2926 dstreg = translate_rreg (SD_, RD0);
2928 temp = ((unsigned32)(State.regs[srcreg2] & 0xff)
2929 * (unsigned32)(State.regs[srcreg1] & 0xff));
2930 sum = State.regs[dstreg] + temp;
2931 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2932 && (temp & 0x80000000) != (sum & 0x80000000));
2933 State.regs[dstreg] = sum;
2936 State.regs[REG_MCVF] = 1;
2938 PSW |= ((v ? PSW_V : 0));
2942 // 1111 1011 0100 1111 Rm Rn Rd1; mach Rm,Rn,Rd1,Rd2
2943 8.0xfb+8.0x4f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mach
2947 int srcreg1, srcreg2, dstreg1, dstreg2;
2948 long long temp, sum;
2952 srcreg1 = translate_rreg (SD_, RM2);
2953 srcreg2 = translate_rreg (SD_, RN0);
2954 dstreg1 = translate_rreg (SD_, RD0);
2955 dstreg2 = translate_rreg (SD_, RD0);
2957 temp = ((signed32)(State.regs[srcreg2] & 0xffff)
2958 * (signed32)(State.regs[srcreg1] & 0xffff));
2959 State.regs[dstreg2] += (temp & 0xffffffff);
2960 sum = State.regs[dstreg1] + ((temp >> 32) & 0xffffffff);
2961 v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
2962 && (temp & 0x80000000) != (sum & 0x80000000));
2963 State.regs[dstreg1] = sum;
2966 State.regs[REG_MCVF] = 1;
2968 PSW |= ((v ? PSW_V : 0));
2972 // 1111 1011 0101 1111 Rm Rn Rd1; machu Rm,Rn,Rd1,Rd2
2973 8.0xfb+8.0x5f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::machu
2977 int srcreg1, srcreg2, dstreg1, dstreg2;
2978 long long temp, sum;
2982 srcreg1 = translate_rreg (SD_, RM2);
2983 srcreg2 = translate_rreg (SD_, RN0);
2984 dstreg1 = translate_rreg (SD_, RD0);
2985 dstreg2 = translate_rreg (SD_, RD0);
2987 temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
2988 * (unsigned32)(State.regs[srcreg1] & 0xffff));
2989 State.regs[dstreg2] += (temp & 0xffffffff);
2990 sum = State.regs[dstreg1] + ((temp >> 32) & 0xffffffff);
2991 v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
2992 && (temp & 0x80000000) != (sum & 0x80000000));
2993 State.regs[dstreg1] = sum;
2996 State.regs[REG_MCVF] = 1;
2998 PSW |= ((v ? PSW_V : 0));
3002 // 1111 1011 0110 1111 Rm Rn Rd1; dmach Rm,Rn,Rd1
3003 8.0xfb+8.0x6f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmach
3007 int srcreg1, srcreg2, dstreg;
3008 long temp, temp2, sum;
3012 srcreg1 = translate_rreg (SD_, RM2);
3013 srcreg2 = translate_rreg (SD_, RN0);
3014 dstreg = translate_rreg (SD_, RD0);
3016 temp = ((signed32)(State.regs[srcreg2] & 0xffff)
3017 * (signed32)(State.regs[srcreg1] & 0xffff));
3018 temp2 = ((signed32)((State.regs[srcreg1] >> 16) & 0xffff)
3019 * (signed32)((State.regs[srcreg2] >> 16) & 0xffff));
3020 sum = temp + temp2 + State.regs[dstreg];
3021 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
3022 && (temp & 0x80000000) != (sum & 0x80000000));
3023 State.regs[dstreg] = sum;
3026 State.regs[REG_MCVF] = 1;
3028 PSW |= ((v ? PSW_V : 0));
3032 // 1111 1011 0111 1111 Rm Rn Rd1; dmachu Rm,Rn,Rd1
3033 8.0xfb+8.0x7f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmachu
3037 int srcreg1, srcreg2, dstreg;
3038 long temp, temp2, sum;
3042 srcreg1 = translate_rreg (SD_, RM2);
3043 srcreg2 = translate_rreg (SD_, RN0);
3044 dstreg = translate_rreg (SD_, RD0);
3046 temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
3047 * (unsigned32)(State.regs[srcreg1] & 0xffff));
3048 temp2 = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
3049 * (unsigned32)((State.regs[srcreg2] >> 16) & 0xffff));
3050 sum = temp + temp2 + State.regs[dstreg];
3051 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
3052 && (temp & 0x80000000) != (sum & 0x80000000));
3053 State.regs[dstreg] = sum;
3056 State.regs[REG_MCVF] = 1;
3058 PSW |= ((v ? PSW_V : 0));
3062 // 1111 1011 1000 1111 Rm Rn Rd1 Rd2; dmulh Rm,Rn,Rd1,Rd2
3063 8.0xfb+8.0x8f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::dmulh
3067 int srcreg1, srcreg2, dstreg1, dstreg2;
3068 signed long long temp;
3071 srcreg1 = translate_rreg (SD_, RM2);
3072 srcreg2 = translate_rreg (SD_, RN0);
3073 dstreg1 = translate_rreg (SD_, RD0);
3074 dstreg2 = translate_rreg (SD_, RD2);
3076 temp = ((signed32)(State.regs[srcreg1] & 0xffff)
3077 * (signed32)(State.regs[srcreg1] & 0xffff));
3078 State.regs[dstreg2] = temp;
3079 temp = ((signed32)((State.regs[srcreg1] >> 16) & 0xffff)
3080 * (signed32)((State.regs[srcreg1] >>16) & 0xffff));
3081 State.regs[dstreg1] = temp;
3084 // 1111 1011 1001 1111 Rm Rn Rd1 Rd2; dmulhu Rm,Rn,Rd1,Rd2
3085 8.0xfb+8.0x9f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::dmulhu
3089 int srcreg1, srcreg2, dstreg1, dstreg2;
3090 signed long long temp;
3093 srcreg1 = translate_rreg (SD_, RM2);
3094 srcreg2 = translate_rreg (SD_, RN0);
3095 dstreg1 = translate_rreg (SD_, RD0);
3096 dstreg2 = translate_rreg (SD_, RD2);
3098 temp = ((unsigned32)(State.regs[srcreg1] & 0xffff)
3099 * (unsigned32)(State.regs[srcreg1] & 0xffff));
3100 State.regs[dstreg2] = temp;
3101 temp = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
3102 * (unsigned32)((State.regs[srcreg1] >>16) & 0xffff));
3103 State.regs[dstreg1] = temp;
3106 // 1111 1011 1010 1111 Rm Rn; sat24 Rm,Rn
3107 8.0xfb+8.0xaf+4.RM2,4.RN0+8.0x0:D2:::sat24
3115 srcreg = translate_rreg (SD_, RM2);
3116 dstreg = translate_rreg (SD_, RN0);
3118 value = State.regs[srcreg];
3120 if (value >= 0x7fffff)
3121 State.regs[dstreg] = 0x7fffff;
3122 else if (value <= 0xff800000)
3123 State.regs[dstreg] = 0xff800000;
3125 State.regs[dstreg] = value;
3127 n = (State.regs[dstreg] & 0x800000) != 0;
3128 z = (State.regs[dstreg] == 0);
3129 PSW &= ~(PSW_Z | PSW_N);
3130 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3133 // 1111 1011 1111 1111 Rm Rn Rd1; bsch Rm,Rn,Rd1
3134 8.0xfb+8.0xff+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::bsch
3139 int srcreg1, srcreg2, dstreg;
3143 srcreg1 = translate_rreg (SD_, RM2);
3144 srcreg2 = translate_rreg (SD_, RN0);
3145 dstreg = translate_rreg (SD_, RD0);
3147 temp = State.regs[srcreg1];
3148 start = (State.regs[srcreg2] & 0x1f) - 1;
3152 for (i = start; i >= 0; i--)
3154 if (temp & (1 << i))
3157 State.regs[dstreg] = i;
3165 State.regs[dstreg] = 0;
3168 PSW |= (c ? PSW_C : 0);
3171 // 1111 1101 0000 1000 Rn Rn IMM32; mov imm24,Rn
3172 8.0xfd+8.0x08+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::mov
3179 dstreg = translate_rreg (SD_, RN0);
3180 State.regs[dstreg] = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3183 // 1111 1101 0001 1000 Rn Rn IMM32; movu imm24,Rn
3184 8.0xfd+8.0x18+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4k:::movu
3191 dstreg = translate_rreg (SD_, RN0);
3192 State.regs[dstreg] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff;
3195 // 1111 1101 0111 1000 Rn Rn IMM32; add imm24,Rn
3196 8.0xfd+8.0x78+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4c:::add
3203 dstreg = translate_rreg (SD_, RN0);
3204 genericAdd (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), dstreg);
3207 // 1111 1101 1000 1000 Rn Rn IMM32; addc imm24,Rn
3208 8.0xfd+8.0x88+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::addc
3212 int dstreg, z, n, c, v;
3213 unsigned long sum, imm, reg2;
3216 dstreg = translate_rreg (SD_, RN0);
3218 imm = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3219 reg2 = State.regs[dstreg];
3220 sum = imm + reg2 + ((PSW & PSW_C) != 0);
3221 State.regs[dstreg] = sum;
3223 z = ((PSW & PSW_Z) != 0) && (sum == 0);
3224 n = (sum & 0x80000000);
3225 c = (sum < imm) || (sum < reg2);
3226 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
3227 && (reg2 & 0x80000000) != (sum & 0x80000000));
3229 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3230 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3231 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3234 // 1111 1101 1001 1000 Rn Rn IMM32; sub imm24,Rn
3235 8.0xfd+8.0x98+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::sub
3242 dstreg = translate_rreg (SD_, RN0);
3243 genericSub (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), dstreg);
3246 // 1111 1101 1010 1000 Rn Rn IMM32; subc imm24,Rn
3247 8.0xfd+8.0xa8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::subc
3251 int dstreg, z, n, c, v;
3252 unsigned long difference, imm, reg2;
3255 dstreg = translate_rreg (SD_, RN0);
3257 imm = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3258 reg2 = State.regs[dstreg];
3259 difference = reg2 - imm - ((PSW & PSW_C) != 0);
3260 State.regs[dstreg] = difference;
3262 z = ((PSW & PSW_Z) != 0) && (difference == 0);
3263 n = (difference & 0x80000000);
3265 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
3266 && (reg2 & 0x80000000) != (difference & 0x80000000));
3268 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3269 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3270 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3273 // 1111 1101 1101 1000 Rn Rn IMM32; cmp imm24,Rn
3274 8.0xfd+8.0xd8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::cmp
3281 srcreg = translate_rreg (SD_, RN0);
3282 genericCmp (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), State.regs[srcreg]);
3285 // 1111 1101 1111 1000 XRn XRn IMM32; mov imm24,XRn
3286 8.0xfd+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM24A+8.IMM24B+8.IMM24C:D4o:::mov
3293 dstreg = translate_xreg (SD_, XRN0);
3295 State.regs[dstreg] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff;
3298 // 1111 1101 0000 1001 Rn Rn IMM24; and imm24,Rn
3299 8.0xfd+8.0x09+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::and
3307 dstreg = translate_rreg (SD_, RN0);
3309 State.regs[dstreg] &= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
3310 z = (State.regs[dstreg] == 0);
3311 n = (State.regs[dstreg] & 0x80000000) != 0;
3312 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3313 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3316 // 1111 1101 0001 1001 Rn Rn IMM24; or imm24,Rn
3317 8.0xfd+8.0x19+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::or
3325 dstreg = translate_rreg (SD_, RN0);
3327 State.regs[dstreg] |= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
3328 z = (State.regs[dstreg] == 0);
3329 n = (State.regs[dstreg] & 0x80000000) != 0;
3330 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3331 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3334 // 1111 1101 0010 1001 Rn Rn IMM24; xor imm24,Rn
3335 8.0xfd+8.0x29+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::xor
3343 dstreg = translate_rreg (SD_, RN0);
3345 State.regs[dstreg] ^= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
3346 z = (State.regs[dstreg] == 0);
3347 n = (State.regs[dstreg] & 0x80000000) != 0;
3348 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3349 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3352 // 1111 1101 0100 1001 Rn Rn IMM24; asr imm24,Rn
3353 8.0xfd+8.0x49+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asr
3362 dstreg = translate_rreg (SD_, RN0);
3364 temp = State.regs[dstreg];
3366 temp >>= (FETCH24 (IMM24A, IMM24B, IMM24C));
3367 State.regs[dstreg] = temp;
3368 z = (State.regs[dstreg] == 0);
3369 n = (State.regs[dstreg] & 0x80000000) != 0;
3370 PSW &= ~(PSW_Z | PSW_N | PSW_C);
3371 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
3375 // 1111 1101 0101 1001 Rn Rn IMM24; lsr imm24,Rn
3376 8.0xfd+8.0x59+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::lsr
3384 dstreg = translate_rreg (SD_, RN0);
3386 c = State.regs[dstreg] & 1;
3387 State.regs[dstreg] >>= (FETCH24 (IMM24A, IMM24B, IMM24C));
3388 z = (State.regs[dstreg] == 0);
3389 n = (State.regs[dstreg] & 0x80000000) != 0;
3390 PSW &= ~(PSW_Z | PSW_N | PSW_C);
3391 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
3394 // 1111 1101 0110 1001 Rn Rn IMM24; asl imm24,Rn
3395 8.0xfd+8.0x69+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asl
3403 dstreg = translate_rreg (SD_, RN0);
3405 State.regs[dstreg] <<= (FETCH24 (IMM24A, IMM24B, IMM24C));
3406 z = (State.regs[dstreg] == 0);
3407 n = (State.regs[dstreg] & 0x80000000) != 0;
3408 PSW &= ~(PSW_Z | PSW_N);
3409 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3412 // 1111 1101 1010 1001 Rn Rn IMM24; mul imm24,Rn
3413 8.0xfd+8.0xa9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mul
3418 unsigned long long temp;
3422 dstreg = translate_rreg (SD_, RN0);
3424 temp = ((signed64)(signed32)State.regs[dstreg]
3425 * (signed64)(signed32)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)));
3426 State.regs[dstreg] = temp & 0xffffffff;
3427 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
3428 z = (State.regs[dstreg] == 0);
3429 n = (State.regs[dstreg] & 0x80000000) != 0;
3430 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3431 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3434 // 1111 1101 1011 1001 Rn Rn IMM24; mulu imm24,Rn
3435 8.0xfd+8.0xb9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mulu
3440 unsigned long long temp;
3444 dstreg = translate_rreg (SD_, RN0);
3446 temp = ((unsigned64)State.regs[dstreg]
3447 * (unsigned64)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)));
3448 State.regs[dstreg] = temp & 0xffffffff;
3449 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
3450 z = (State.regs[dstreg] == 0);
3451 n = (State.regs[dstreg] & 0x80000000) != 0;
3452 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3453 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3456 // 1111 1101 1110 1001 Rn Rn IMM24; btst imm24,,Rn
3457 8.0xfd+8.0xe9+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::btst
3464 srcreg = translate_rreg (SD_, RN0);
3465 genericBtst (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3468 // 1111 1101 0000 1010 Rn Rm IMM24; mov (d24,Rm),Rn
3469 8.0xfd+8.0x0a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::mov
3476 srcreg = translate_rreg (SD_, RM0);
3477 dstreg = translate_rreg (SD_, RN2);
3478 State.regs[dstreg] = load_word (State.regs[srcreg]
3479 + EXTEND24 (FETCH24 (IMM24A,
3483 // 1111 1101 0001 1010 Rm Rn IMM24; mov Rm,(d24,Rn)
3484 8.0xfd+8.0x1a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::mov
3491 srcreg = translate_rreg (SD_, RM2);
3492 dstreg = translate_rreg (SD_, RN0);
3493 store_word (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3494 State.regs[srcreg]);
3497 // 1111 1101 0010 1010 Rn Rm IMM24; movbu (d24,Rm),Rn
3498 8.0xfd+8.0x2a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movbu
3505 srcreg = translate_rreg (SD_, RM0);
3506 dstreg = translate_rreg (SD_, RN2);
3507 State.regs[dstreg] = load_byte (State.regs[srcreg]
3508 + EXTEND24 (FETCH24 (IMM24A,
3512 // 1111 1101 0011 1010 Rm Rn IMM24; movbu Rm,(d24,Rn)
3513 8.0xfd+8.0x3a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movbu
3520 srcreg = translate_rreg (SD_, RM2);
3521 dstreg = translate_rreg (SD_, RN0);
3522 store_byte (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3523 State.regs[srcreg]);
3526 // 1111 1101 0100 1010 Rn Rm IMM24; movhu (d24,Rm),Rn
3527 8.0xfd+8.0x4a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movhu
3534 srcreg = translate_rreg (SD_, RM0);
3535 dstreg = translate_rreg (SD_, RN2);
3536 State.regs[dstreg] = load_half (State.regs[srcreg]
3537 + EXTEND24 (FETCH24 (IMM24A,
3541 // 1111 1101 0101 1010 Rm Rn IMM24; movhu Rm,(d24,Rn)
3542 8.0xfd+8.0x5a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movhu
3549 srcreg = translate_rreg (SD_, RM2);
3550 dstreg = translate_rreg (SD_, RN0);
3551 store_half (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3552 State.regs[srcreg]);
3555 // 1111 1101 0110 1010 Rn Rm IMM24; mov (d24,Rm+),Rn
3556 8.0xfd+8.0x6a+4.RN2,4.RM0!RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::mov
3563 srcreg = translate_rreg (SD_, RM0);
3564 dstreg = translate_rreg (SD_, RN2);
3565 State.regs[dstreg] = load_word (State.regs[srcreg]);
3566 State.regs[srcreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3569 // 1111 1101 0111 1010 Rm Rn IMM24; mov Rm,(d24,Rn+)
3570 8.0xfd+8.0x7a+4.RM2,4.RN0!RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mov
3577 srcreg = translate_rreg (SD_, RM2);
3578 dstreg = translate_rreg (SD_, RN0);
3579 store_word (State.regs[dstreg], State.regs[srcreg]);
3580 State.regs[dstreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3584 // 1111 1101 1000 1010 Rn 0000 IMM24; mov (d24,sp),Rn
3585 8.0xfd+8.0x8a+4.RN2,4.0x0+IMM24A+8.IMM24B+8.IMM24C:D4r:::mov
3592 dstreg = translate_rreg (SD_, RN2);
3593 State.regs[dstreg] = load_word (State.regs[REG_SP]
3594 + EXTEND24 (FETCH24 (IMM24A,
3598 // 1111 1101 1001 1010 Rm 0000 IMM24; mov Rm,(d24,sp)
3599 8.0xfd+8.0x9a+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::mov
3606 srcreg = translate_rreg (SD_, RM2);
3607 store_word (State.regs[REG_SP] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3608 State.regs[srcreg]);
3611 // 1111 1101 1010 1010 Rn 0000 IMM24; movbu (d24,Rm),Rn
3612 8.0xfd+8.0xaa+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movbu
3619 dstreg = translate_rreg (SD_, RN2);
3620 State.regs[dstreg] = load_byte (State.regs[REG_SP]
3621 + EXTEND24 (FETCH24 (IMM24A,
3625 // 1111 1101 1011 1010 Rm 0000 IMM24; movbu Rm,(d24,sp)
3626 8.0xfd+8.0xba+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movbu
3633 srcreg = translate_rreg (SD_, RM2);
3634 store_byte (State.regs[REG_SP] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3635 State.regs[srcreg]);
3638 // 1111 1101 1100 1010 Rn 0000 IMM24; movhu (d24,sp),Rn
3639 8.0xfd+8.0xca+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movhu
3646 dstreg = translate_rreg (SD_, RN2);
3647 State.regs[dstreg] = load_half (State.regs[REG_SP]
3648 + EXTEND24 (FETCH24 (IMM24A,
3652 // 1111 1101 1101 1010 Rm Rn IMM24; movhu Rm,(d24,sp)
3653 8.0xfd+8.0xda+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movhu
3660 srcreg = translate_rreg (SD_, RM2);
3661 store_half (State.regs[REG_SP] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3662 State.regs[srcreg]);
3665 // 1111 1101 1110 1010 Rn Rm IMM24; movhu (d24,Rm+),Rn
3666 8.0xfd+8.0xea+4.RN2,4.RM0!RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::movhu
3673 srcreg = translate_rreg (SD_, RM0);
3674 dstreg = translate_rreg (SD_, RN2);
3675 State.regs[dstreg] = load_half (State.regs[srcreg]);
3676 State.regs[dstreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3679 // 1111 1101 1111 1010 Rm Rn IMM24; movhu Rm,(d24,Rn+)
3680 8.0xfd+8.0xfa+4.RM2,4.RN0!RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::movhu
3687 srcreg = translate_rreg (SD_, RM2);
3688 dstreg = translate_rreg (SD_, RN0);
3689 store_half (State.regs[dstreg], State.regs[srcreg]);
3690 State.regs[srcreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3693 // 1111 1101 0000 1011 Rn IMM24; mac imm24,Rn
3694 8.0xfd+8.0x0b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mac
3699 long long temp, sum;
3703 srcreg = translate_rreg (SD_, RN2);
3705 temp = ((signed64)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C))
3706 * (signed64)State.regs[srcreg]);
3707 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3708 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3709 State.regs[REG_MCRL] = sum;
3712 sum = State.regs[REG_MCRH] + temp + c;
3713 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3714 && (temp & 0x80000000) != (sum & 0x80000000));
3715 State.regs[REG_MCRH] = sum;
3717 State.regs[REG_MCVF] = 1;
3720 // 1111 1101 0001 1011 Rn IMM24; macu imm24,Rn
3721 8.0xfd+8.0x1b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macu
3726 long long temp, sum;
3730 srcreg = translate_rreg (SD_, RN2);
3732 temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C))
3733 * (unsigned64)State.regs[srcreg]);
3734 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3735 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3736 State.regs[REG_MCRL] = sum;
3739 sum = State.regs[REG_MCRH] + temp + c;
3740 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3741 && (temp & 0x80000000) != (sum & 0x80000000));
3742 State.regs[REG_MCRH] = sum;
3744 State.regs[REG_MCVF] = 1;
3747 // 1111 1101 0010 1011 Rn IMM24; macb imm24,Rn
3748 8.0xfd+8.0x2b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macb
3753 long long temp, sum;
3757 srcreg = translate_rreg (SD_, RN2);
3759 temp = ((signed64)EXTEND8 (FETCH24 (IMM24A, IMM24B, IMM24C))
3760 * (signed64)State.regs[srcreg] & 0xff);
3761 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3762 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3763 State.regs[REG_MCRL] = sum;
3766 sum = State.regs[REG_MCRH] + temp + c;
3767 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3768 && (temp & 0x80000000) != (sum & 0x80000000));
3769 State.regs[REG_MCRH] = sum;
3771 State.regs[REG_MCVF] = 1;
3774 // 1111 1101 0011 1011 Rn IMM24; macbu imm24,Rn
3775 8.0xfd+8.0x3b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macbu
3780 long long temp, sum;
3784 srcreg = translate_rreg (SD_, RN2);
3786 temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C))
3787 * (unsigned64)State.regs[srcreg] & 0xff);
3788 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3789 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3790 State.regs[REG_MCRL] = sum;
3793 sum = State.regs[REG_MCRH] + temp + c;
3794 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3795 && (temp & 0x80000000) != (sum & 0x80000000));
3796 State.regs[REG_MCRH] = sum;
3798 State.regs[REG_MCVF] = 1;
3801 // 1111 1101 0100 1011 Rn IMM24; mach imm24,Rn
3802 8.0xfd+8.0x4b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mach
3807 long long temp, sum;
3811 srcreg = translate_rreg (SD_, RN2);
3813 temp = ((signed64)EXTEND16 (FETCH24 (IMM24A, IMM24B, IMM24C))
3814 * (signed64)State.regs[srcreg] & 0xffff);
3815 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3816 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3817 State.regs[REG_MCRL] = sum;
3820 sum = State.regs[REG_MCRH] + temp + c;
3821 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3822 && (temp & 0x80000000) != (sum & 0x80000000));
3823 State.regs[REG_MCRH] = sum;
3825 State.regs[REG_MCVF] = 1;
3828 // 1111 1101 0101 1011 Rn IMM24; machu imm24,Rn
3829 8.0xfd+8.0x5b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::machu
3834 long long temp, sum;
3838 srcreg = translate_rreg (SD_, RN2);
3840 temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffff)
3841 * (unsigned64)State.regs[srcreg] & 0xffff);
3842 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3843 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3844 State.regs[REG_MCRL] = sum;
3847 sum = State.regs[REG_MCRH] + temp + c;
3848 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3849 && (temp & 0x80000000) != (sum & 0x80000000));
3850 State.regs[REG_MCRH] = sum;
3852 State.regs[REG_MCVF] = 1;
3855 // 1111 1101 0000 1110 Rn 0000 ABS24; mov (abs24),Rn
3856 8.0xfd+8.0x0e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::mov
3863 dstreg = translate_rreg (SD_, RN2);
3864 State.regs[dstreg] = load_word (FETCH24 (IMM24A, IMM24B, IMM24C));
3867 // 1111 1101 0001 1110 Rm 0000 ABS24; mov Rm,(abs24)
3868 8.0xfd+8.0x1e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4v:::mov
3875 srcreg = translate_rreg (SD_, RM2);
3876 store_word (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3880 // 1111 1101 0010 1110 Rn 0000 ABS24; movbu (abs24),Rn
3881 8.0xfd+8.0x2e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movbu
3888 dstreg = translate_rreg (SD_, RN2);
3889 State.regs[dstreg] = load_byte (FETCH24 (IMM24A, IMM24B, IMM24C));
3892 // 1111 1101 0011 1110 Rm 0000 ABS24; movbu Rm,(abs24)
3893 8.0xfd+8.0x3e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movbu
3900 srcreg = translate_rreg (SD_, RM2);
3901 store_byte (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3905 // 1111 1101 0100 1110 Rn 0000 ABS24; movhu (abs24),Rn
3906 8.0xfd+8.0x4e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movhu
3913 dstreg = translate_rreg (SD_, RN2);
3914 State.regs[dstreg] = load_half (FETCH24 (IMM24A, IMM24B, IMM24C));
3917 // 1111 1101 0101 1110 Rm 0000 ABS24; movhu Rm,(abs24)
3918 8.0xfd+8.0x5e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movhu
3925 srcreg = translate_rreg (SD_, RM2);
3926 store_half (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3930 // 1111 1110 0000 1000 Rn Rn IMM32; mov imm32,Rn
3931 8.0xfe+8.0x08+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mov
3938 dstreg = translate_rreg (SD_, RN0);
3939 State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
3942 // 1111 1110 0001 1000 Rn Rn IMM32; movu imm32,Rn
3943 8.0xfe+8.0x18+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movu
3950 dstreg = translate_rreg (SD_, RN0);
3951 State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
3954 // 1111 1110 0111 1000 Rn Rn IMM32; add imm32,Rn
3955 8.0xfe+8.0x78+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::add
3962 dstreg = translate_rreg (SD_, RN0);
3963 genericAdd (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), dstreg);
3966 // 1111 1110 1000 1000 Rn Rn IMM32; addc imm32,Rn
3967 8.0xfe+8.0x88+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::addc
3972 unsigned int imm, reg2, sum;
3976 dstreg = translate_rreg (SD_, RN0);
3978 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
3979 reg2 = State.regs[dstreg];
3980 sum = imm + reg2 + ((PSW & PSW_C) != 0);
3981 State.regs[dstreg] = sum;
3983 z = ((PSW & PSW_Z) != 0) && (sum == 0);
3984 n = (sum & 0x80000000);
3985 c = (sum < imm) || (sum < reg2);
3986 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
3987 && (reg2 & 0x80000000) != (sum & 0x80000000));
3989 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3990 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3991 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3994 // 1111 1110 1001 1000 Rn Rn IMM32; sub imm32,Rn
3995 8.0xfe+8.0x98+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::sub
4002 dstreg = translate_rreg (SD_, RN0);
4003 genericSub (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), dstreg);
4006 // 1111 1110 1010 1000 Rn Rn IMM32; subc imm32,Rn
4007 8.0xfe+8.0xa8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::subc
4012 unsigned int imm, reg2, difference;
4016 dstreg = translate_rreg (SD_, RN0);
4018 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4019 reg2 = State.regs[dstreg];
4020 difference = reg2 - imm - ((PSW & PSW_C) != 0);
4021 State.regs[dstreg] = difference;
4023 z = ((PSW & PSW_Z) != 0) && (difference == 0);
4024 n = (difference & 0x80000000);
4026 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
4027 && (reg2 & 0x80000000) != (difference & 0x80000000));
4029 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4030 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
4031 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
4034 // 1111 1110 0111 1000 Rn Rn IMM32; cmp imm32,Rn
4035 8.0xfe+8.0xd8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::cmp
4042 srcreg = translate_rreg (SD_, RN0);
4043 genericCmp (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4046 // 1111 1110 1111 1000 XRn XRn IMM32; mov imm32,XRn
4047 8.0xfe+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::mov
4054 dstreg = translate_xreg (SD_, XRN0);
4056 State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
4059 // 1111 1110 0000 1001 Rn Rn IMM32; and imm32,Rn
4060 8.0xfe+8.0x09+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::and
4068 dstreg = translate_rreg (SD_, RN0);
4070 State.regs[dstreg] &= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4071 z = (State.regs[dstreg] == 0);
4072 n = (State.regs[dstreg] & 0x80000000) != 0;
4073 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4074 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4077 // 1111 1110 0001 1001 Rn Rn IMM32; or imm32,Rn
4078 8.0xfe+8.0x19+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::or
4086 dstreg = translate_rreg (SD_, RN0);
4088 State.regs[dstreg] |= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4089 z = (State.regs[dstreg] == 0);
4090 n = (State.regs[dstreg] & 0x80000000) != 0;
4091 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4092 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4095 // 1111 1110 0010 1001 Rn Rn IMM32; xor imm32,Rn
4096 8.0xfe+8.0x29+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::xor
4104 dstreg = translate_rreg (SD_, RN0);
4106 State.regs[dstreg] ^= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4107 z = (State.regs[dstreg] == 0);
4108 n = (State.regs[dstreg] & 0x80000000) != 0;
4109 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4110 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4113 // 1111 1110 0100 1001 Rn Rn IMM32; asr imm32,Rn
4114 8.0xfe+8.0x49+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asr
4123 dstreg = translate_rreg (SD_, RN0);
4125 temp = State.regs[dstreg];
4127 temp >>= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4128 State.regs[dstreg] = temp;
4129 z = (State.regs[dstreg] == 0);
4130 n = (State.regs[dstreg] & 0x80000000) != 0;
4131 PSW &= ~(PSW_Z | PSW_N | PSW_C);
4132 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
4135 // 1111 1110 0101 1001 Rn Rn IMM32; lsr imm32,Rn
4136 8.0xfe+8.0x59+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::lsr
4144 dstreg = translate_rreg (SD_, RN0);
4146 c = State.regs[dstreg] & 1;
4147 State.regs[dstreg] >>= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4148 z = (State.regs[dstreg] == 0);
4149 n = (State.regs[dstreg] & 0x80000000) != 0;
4150 PSW &= ~(PSW_Z | PSW_N | PSW_C);
4151 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
4154 // 1111 1110 0110 1001 Rn Rn IMM32; asl imm32,Rn
4155 8.0xfe+8.0x69+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asl
4163 dstreg = translate_rreg (SD_, RN0);
4165 State.regs[dstreg] <<= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4166 z = (State.regs[dstreg] == 0);
4167 n = (State.regs[dstreg] & 0x80000000) != 0;
4168 PSW &= ~(PSW_Z | PSW_N);
4169 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4172 // 1111 1110 1010 1001 Rn Rn IMM32; mul imm32,Rn
4173 8.0xfe+8.0xa9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mul
4178 unsigned long long temp;
4182 dstreg = translate_rreg (SD_, RN0);
4184 temp = ((signed64)(signed32)State.regs[dstreg]
4185 * (signed64)(signed32)(FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)));
4186 State.regs[dstreg] = temp & 0xffffffff;
4187 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
4188 z = (State.regs[dstreg] == 0);
4189 n = (State.regs[dstreg] & 0x80000000) != 0;
4190 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4191 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4194 // 1111 1110 1011 1001 Rn Rn IMM32; mulu imm32,Rn
4195 8.0xfe+8.0xb9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mulu
4200 unsigned long long temp;
4204 dstreg = translate_rreg (SD_, RN0);
4206 temp = ((unsigned64)State.regs[dstreg]
4207 * (unsigned64) (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)));
4208 State.regs[dstreg] = temp & 0xffffffff;
4209 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
4210 z = (State.regs[dstreg] == 0);
4211 n = (State.regs[dstreg] & 0x80000000) != 0;
4212 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4213 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4216 // 1111 1110 1110 1001 Rn Rn IMM32; btst imm32,Rn
4217 8.0xfe+8.0xe9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5a:::btst
4224 srcreg = translate_rreg (SD_, RN0);
4225 genericBtst (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4228 // 1111 1110 0000 1010 Rn Rm IMM32; mov (d32,Rm),Rn
4229 8.0xfe+8.0x0a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::mov
4236 srcreg = translate_rreg (SD_, RM0);
4237 dstreg = translate_rreg (SD_, RN2);
4238 State.regs[dstreg] = load_word (State.regs[srcreg]
4239 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4242 // 1111 1110 0001 1010 Rm Rn IMM32; mov Rm,(d32,Rn)
4243 8.0xfe+8.0x1a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5g:::mov
4250 srcreg = translate_rreg (SD_, RM2);
4251 dstreg = translate_rreg (SD_, RN0);
4252 store_word (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4253 State.regs[srcreg]);
4256 // 1111 1110 0010 1010 Rn Rm IMM32; movbu (d32,Rm),Rn
4257 8.0xfe+8.0x2a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movbu
4264 srcreg = translate_rreg (SD_, RM0);
4265 dstreg = translate_rreg (SD_, RN2);
4266 State.regs[dstreg] = load_byte (State.regs[srcreg]
4267 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4270 // 1111 1110 0011 1010 Rm Rn IMM32; movbu Rm,(d32,Rn)
4271 8.0xfe+8.0x3a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movbu
4278 srcreg = translate_rreg (SD_, RM2);
4279 dstreg = translate_rreg (SD_, RN0);
4280 store_byte (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4281 State.regs[srcreg]);
4284 // 1111 1110 0100 1010 Rn Rm IMM32; movhu (d32,Rm),Rn
4285 8.0xfe+8.0x4a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movhu
4292 srcreg = translate_rreg (SD_, RM0);
4293 dstreg = translate_rreg (SD_, RN2);
4294 State.regs[dstreg] = load_half (State.regs[srcreg]
4295 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4298 // 1111 1110 0101 1010 Rm Rn IMM32; movhu Rm,(d32,Rn)
4299 8.0xfe+8.0x5a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movhu
4306 srcreg = translate_rreg (SD_, RM2);
4307 dstreg = translate_rreg (SD_, RN0);
4308 store_half (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4309 State.regs[srcreg]);
4312 // 1111 1110 0110 1010 Rn Rm IMM32; mov (d32,Rm+),Rn
4313 8.0xfe+8.0x6a+4.RN2,4.RM0!RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::mov
4320 srcreg = translate_rreg (SD_, RM0);
4321 dstreg = translate_rreg (SD_, RN2);
4322 State.regs[dstreg] = load_word (State.regs[srcreg]);
4323 State.regs[srcreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4326 // 1111 1110 0111 1010 Rm Rn IMM32; mov Rm,(d32,Rn+)
4327 8.0xfe+8.0x7a+4.RM2,4.RN0!RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5z:::mov
4334 srcreg = translate_rreg (SD_, RM2);
4335 dstreg = translate_rreg (SD_, RN0);
4336 store_word (State.regs[dstreg], State.regs[srcreg]);
4337 State.regs[dstreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4341 // 1111 1110 1000 1010 Rn 0000 IMM32; mov (d32,sp),Rn
4342 8.0xfe+8.0x8a+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::mov
4349 dstreg = translate_rreg (SD_, RN2);
4350 State.regs[dstreg] = load_word (State.regs[REG_SP]
4351 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4354 // 1111 1110 1001 1010 Rm 0000 IMM32; mov Rm,(d32,sp)
4355 8.0xfe+8.0x9a+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::mov
4362 srcreg = translate_rreg (SD_, RM2);
4363 store_word (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4364 State.regs[srcreg]);
4367 // 1111 1110 1010 1010 Rn 0000 IMM32; movbu (d32,sp),Rn
4368 8.0xfe+8.0xaa+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movbu
4375 dstreg = translate_rreg (SD_, RN2);
4376 State.regs[dstreg] = load_byte (State.regs[REG_SP]
4377 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4380 // 1111 1110 1011 1010 Rm 0000 IMM32; movbu Rm,(d32,sp)
4381 8.0xfe+8.0xba+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movbu
4388 srcreg = translate_rreg (SD_, RM2);
4389 store_byte (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4390 State.regs[srcreg]);
4393 // 1111 1110 1100 1010 Rn 0000 IMM32; movhu (d32,sp),Rn
4394 8.0xfe+8.0xca+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movhu
4401 dstreg = translate_rreg (SD_, RN2);
4402 State.regs[dstreg] = load_half (State.regs[REG_SP]
4403 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4406 // 1111 1110 1101 1010 Rm 0000 IMM32; movhu Rm,(d32,sp)
4407 8.0xfe+8.0xda+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movhu
4414 srcreg = translate_rreg (SD_, RM2);
4415 store_half (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4416 State.regs[srcreg]);
4420 // 1111 1110 1110 1010 Rn Rm IMM32; movhu (d32,Rm+),Rn
4421 8.0xfe+8.0xea+4.RN2,4.RM0!RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::movhu
4428 srcreg = translate_rreg (SD_, RM0);
4429 dstreg = translate_rreg (SD_, RN2);
4430 State.regs[dstreg] = load_half (State.regs[srcreg]);
4431 State.regs[srcreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4434 // 1111 1110 1111 1010 Rm Rn IMM32; movhu Rm,(d32,Rn+)
4435 8.0xfe+8.0xfa+4.RM2,4.RN0!RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::movhu
4442 srcreg = translate_rreg (SD_, RM2);
4443 dstreg = translate_rreg (SD_, RN0);
4444 store_half (State.regs[dstreg], State.regs[srcreg]);
4445 State.regs[dstreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4449 // 1111 1110 0000 1011 Rn Rn IMM32; mac imm32,Rn
4450 8.0xfe+8.0x0b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mac
4455 long long temp, sum;
4459 srcreg = translate_rreg (SD_, RN0);
4460 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4462 temp = ((signed64)(signed32)State.regs[srcreg]
4463 * (signed64)(signed32)imm);
4464 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
4465 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
4466 State.regs[REG_MCRL] = sum;
4469 sum = State.regs[REG_MCRH] + temp + c;
4470 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
4471 && (temp & 0x80000000) != (sum & 0x80000000));
4472 State.regs[REG_MCRH] = sum;
4474 State.regs[REG_MCVF] = 1;
4477 // 1111 1110 0001 1011 Rn Rn IMM32; macu imm32,Rn
4478 8.0xfe+8.0x1b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macu
4483 long long temp, sum;
4487 srcreg = translate_rreg (SD_, RN0);
4488 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4490 temp = ((unsigned64)State.regs[srcreg]
4492 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
4493 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
4494 State.regs[REG_MCRL] = sum;
4497 sum = State.regs[REG_MCRH] + temp + c;
4498 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
4499 && (temp & 0x80000000) != (sum & 0x80000000));
4500 State.regs[REG_MCRH] = sum;
4502 State.regs[REG_MCVF] = 1;
4505 // 1111 1110 0010 1011 Rn Rn IMM32; macb imm32,Rn
4506 8.0xfe+8.0x2b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macb
4515 srcreg = translate_rreg (SD_, RN0);
4516 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4518 temp = ((signed32)(signed8)(State.regs[srcreg] & 0xff)
4519 * (signed32)(signed8)(imm & 0xff));
4520 sum = State.regs[REG_MCRL] + temp;
4521 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
4522 && (temp & 0x80000000) != (sum & 0x80000000));
4523 State.regs[REG_MCRL] = sum;
4525 State.regs[REG_MCVF] = 1;
4528 // 1111 1110 0011 1011 Rn Rn IMM32; macbu imm32,Rn
4529 8.0xfe+8.0x3b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macbu
4538 srcreg = translate_rreg (SD_, RN0);
4539 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4541 temp = ((unsigned32)(State.regs[srcreg] & 0xff)
4542 * (unsigned32)(imm & 0xff));
4543 sum = State.regs[REG_MCRL] + temp;
4544 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
4545 && (temp & 0x80000000) != (sum & 0x80000000));
4546 State.regs[REG_MCRL] = sum;
4548 State.regs[REG_MCVF] = 1;
4551 // 1111 1110 0100 1011 Rn Rn IMM32; mach imm32,Rn
4552 8.0xfe+8.0x4b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mach
4561 srcreg = translate_rreg (SD_, RN0);
4562 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4564 temp = ((signed32)(signed16)(State.regs[srcreg] & 0xffff)
4565 * (signed32)(signed16)(imm & 0xffff));
4566 sum = State.regs[REG_MCRL] + temp;
4567 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
4568 && (temp & 0x80000000) != (sum & 0x80000000));
4569 State.regs[REG_MCRL] = sum;
4571 State.regs[REG_MCVF] = 1;
4574 // 1111 1110 0101 1011 Rn Rn IMM32; machu imm32,Rn
4575 8.0xfe+8.0x5b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::machu
4584 srcreg = translate_rreg (SD_, RN0);
4585 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4587 temp = ((unsigned32)(State.regs[srcreg] & 0xffff)
4588 * (unsigned32)(imm & 0xffff));
4589 sum = State.regs[REG_MCRL] + temp;
4590 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
4591 && (temp & 0x80000000) != (sum & 0x80000000));
4592 State.regs[REG_MCRL] = sum;
4594 State.regs[REG_MCVF] = 1;
4597 // 1111 1110 0110 1011 Rn Rn IMM32; dmach imm32,Rn
4598 8.0xfe+8.0x6b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmach
4603 long temp, temp2, sum;
4607 srcreg = translate_rreg (SD_, RN0);
4608 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4610 temp = ((signed32)(signed16)(State.regs[srcreg] & 0xffff)
4611 * (signed32)(signed16)(imm & 0xffff));
4612 temp2 = ((signed32)(signed16)((State.regs[srcreg] >> 16) & 0xffff)
4613 * (signed32)(signed16)((imm >> 16) & 0xffff));
4614 sum = temp + temp2 + State.regs[REG_MCRL];
4615 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
4616 && (temp & 0x80000000) != (sum & 0x80000000));
4617 State.regs[REG_MCRL] = sum;
4619 State.regs[REG_MCVF] = 1;
4622 // 1111 1110 0111 1011 Rn Rn IMM32; dmachu imm32,Rn
4623 8.0xfe+8.0x7b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmachu
4628 long temp, temp2, sum;
4632 srcreg = translate_rreg (SD_, RN0);
4633 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4635 temp = ((unsigned32)(State.regs[srcreg] & 0xffff)
4636 * (unsigned32)(imm & 0xffff));
4637 temp2 = ((unsigned32)((State.regs[srcreg] >> 16) & 0xffff)
4638 * (unsigned32)((imm >> 16) & 0xffff));
4639 sum = temp + temp2 + State.regs[REG_MCRL];
4640 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
4641 && (temp & 0x80000000) != (sum & 0x80000000));
4642 State.regs[REG_MCRL] = sum;
4644 State.regs[REG_MCVF] = 1;
4647 // 1111 1110 1000 1011 Rn Rn IMM32; dmulh imm32,Rn
4648 8.0xfe+8.0x8b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmulh
4656 dstreg = translate_rreg (SD_, RN0);
4657 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4659 temp = ((signed32)(signed16)(State.regs[dstreg] & 0xffff)
4660 * (signed32)(signed16)(imm & 0xffff));
4661 State.regs[REG_MDRQ] = temp;
4662 temp = ((signed32)(signed16)((State.regs[dstreg] >> 16) & 0xffff)
4663 * (signed32)(signed16)((imm>>16) & 0xffff));
4664 State.regs[dstreg] = temp;
4667 // 1111 1110 1001 1011 Rn Rn IMM32; dmulhu imm32,Rn
4668 8.0xfe+8.0x9b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmulhu
4676 dstreg = translate_rreg (SD_, RN0);
4677 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4679 temp = ((unsigned32)(State.regs[dstreg] & 0xffff)
4680 * (unsigned32)(imm & 0xffff));
4681 State.regs[REG_MDRQ] = temp;
4682 temp = ((unsigned32)((State.regs[dstreg] >> 16) & 0xffff)
4683 * (unsigned32)((imm >>16) & 0xffff));
4684 State.regs[dstreg] = temp;
4687 // 1111 1110 0000 1110 Rn 0000 IMM32; mov (abs32),Rn
4688 8.0xfe+8.0x0e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5h:::mov
4695 dstreg = translate_rreg (SD_, RN2);
4696 State.regs[dstreg] = load_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4699 // 1111 1110 0001 1110 Rm 0000 IMM32; mov Rn,(abs32)
4700 8.0xfe+8.0x1e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::mov
4707 srcreg = translate_rreg (SD_, RM2);
4708 store_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4711 // 1111 1110 0020 1110 Rn 0000 IMM32; movbu (abs32),Rn
4712 8.0xfe+8.0x2e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5i:::movbu
4719 dstreg = translate_rreg (SD_, RN2);
4720 State.regs[dstreg] = load_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4723 // 1111 1110 0011 1110 Rm 0000 IMM32; movbu Rn,(abs32)
4724 8.0xfe+8.0x3e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movbu
4731 srcreg = translate_rreg (SD_, RM2);
4732 store_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4735 // 1111 1110 0100 1110 Rn 0000 IMM32; movhu (abs32),Rn
4736 8.0xfe+8.0x4e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5j:::movhu
4743 dstreg = translate_rreg (SD_, RN2);
4744 State.regs[dstreg] = load_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4747 // 1111 1110 0101 1110 Rm 0000 IMM32; movhu Rn,(abs32)
4748 8.0xfe+8.0x5e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movhu
4755 srcreg = translate_rreg (SD_, RM2);
4756 store_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4759 // 1111 0111 0000 0000 Rm1 Rn1 Rm2 Rn2; add_add Rm1, Rn1, Rm2, Rn2
4760 8.0xf7+8.0x00+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_add
4764 int srcreg1, srcreg2, dstreg1, dstreg2;
4767 srcreg1 = translate_rreg (SD_, RM1);
4768 srcreg2 = translate_rreg (SD_, RM2);
4769 dstreg1 = translate_rreg (SD_, RN1);
4770 dstreg2 = translate_rreg (SD_, RN2);
4772 State.regs[dstreg1] += State.regs[srcreg1];
4773 State.regs[dstreg2] += State.regs[srcreg2];
4776 // 1111 0111 0001 0000 Rm1 Rn1 imm4 Rn2; add_add Rm1, Rn1, imm4, Rn2
4777 8.0xf7+8.0x10+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_add
4781 int srcreg1, dstreg1, dstreg2;
4784 srcreg1 = translate_rreg (SD_, RM1);
4785 dstreg1 = translate_rreg (SD_, RN1);
4786 dstreg2 = translate_rreg (SD_, RN2);
4788 State.regs[dstreg1] += State.regs[srcreg1];
4789 State.regs[dstreg2] += EXTEND4 (IMM4);
4792 // 1111 0111 0010 0000 Rm1 Rn1 Rm2 Rn2; add_sub Rm1, Rn1, Rm2, Rn2
4793 8.0xf7+8.0x20+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_sub
4797 int srcreg1, srcreg2, dstreg1, dstreg2;
4800 srcreg1 = translate_rreg (SD_, RM1);
4801 srcreg2 = translate_rreg (SD_, RM2);
4802 dstreg1 = translate_rreg (SD_, RN1);
4803 dstreg2 = translate_rreg (SD_, RN2);
4805 State.regs[dstreg1] += State.regs[srcreg1];
4806 State.regs[dstreg2] -= State.regs[srcreg2];
4809 // 1111 0111 0011 0000 Rm1 Rn1 imm4 Rn2; add_sub Rm1, Rn1, imm4, Rn2
4810 8.0xf7+8.0x30+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_sub
4814 int srcreg1, dstreg1, dstreg2;
4817 srcreg1 = translate_rreg (SD_, RM1);
4818 dstreg1 = translate_rreg (SD_, RN1);
4819 dstreg2 = translate_rreg (SD_, RN2);
4821 State.regs[dstreg1] += State.regs[srcreg1];
4822 State.regs[dstreg2] -= EXTEND4 (IMM4);
4825 // 1111 0111 0100 0000 Rm1 Rn1 Rm2 Rn2; add_cmp Rm1, Rn1, Rm2, Rn2
4826 8.0xf7+8.0x40+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_cmp
4830 int srcreg1, srcreg2, dstreg1, dstreg2;
4833 srcreg1 = translate_rreg (SD_, RM1);
4834 srcreg2 = translate_rreg (SD_, RM2);
4835 dstreg1 = translate_rreg (SD_, RN1);
4836 dstreg2 = translate_rreg (SD_, RN2);
4838 State.regs[dstreg1] += State.regs[srcreg1];
4839 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
4842 // 1111 0111 0101 0000 Rm1 Rn1 imm4 Rn2; add_cmp Rm1, Rn1, imm4, Rn2
4843 8.0xf7+8.0x50+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_cmp
4847 int srcreg1, dstreg1, dstreg2;
4850 srcreg1 = translate_rreg (SD_, RM1);
4851 dstreg1 = translate_rreg (SD_, RN1);
4852 dstreg2 = translate_rreg (SD_, RN2);
4854 State.regs[dstreg1] += State.regs[srcreg1];
4855 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
4858 // 1111 0111 0110 0000 Rm1 Rn1 Rm2 Rn2; add_mov Rm1, Rn1, Rm2, Rn2
4859 8.0xf7+8.0x60+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_mov
4863 int srcreg1, srcreg2, dstreg1, dstreg2;
4866 srcreg1 = translate_rreg (SD_, RM1);
4867 srcreg2 = translate_rreg (SD_, RM2);
4868 dstreg1 = translate_rreg (SD_, RN1);
4869 dstreg2 = translate_rreg (SD_, RN2);
4871 State.regs[dstreg1] += State.regs[srcreg1];
4872 State.regs[dstreg2] = State.regs[srcreg2];
4875 // 1111 0111 0111 0000 Rm1 Rn1 imm4 Rn2; add_mov Rm1, Rn1, imm4, Rn2
4876 8.0xf7+8.0x70+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_mov
4880 int srcreg1, dstreg1, dstreg2;
4883 srcreg1 = translate_rreg (SD_, RM1);
4884 dstreg1 = translate_rreg (SD_, RN1);
4885 dstreg2 = translate_rreg (SD_, RN2);
4887 State.regs[dstreg1] += State.regs[srcreg1];
4888 State.regs[dstreg2] = EXTEND4 (IMM4);
4891 // 1111 0111 1000 0000 Rm1 Rn1 Rm2 Rn2; add_asr Rm1, Rn1, Rm2, Rn2
4892 8.0xf7+8.0x80+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_asr
4896 int srcreg1, srcreg2, dstreg1, dstreg2;
4900 srcreg1 = translate_rreg (SD_, RM1);
4901 srcreg2 = translate_rreg (SD_, RM2);
4902 dstreg1 = translate_rreg (SD_, RN1);
4903 dstreg2 = translate_rreg (SD_, RN2);
4905 State.regs[dstreg1] += State.regs[srcreg1];
4906 temp = State.regs[dstreg2];
4907 temp >>= State.regs[srcreg2];
4908 State.regs[dstreg2] = temp;
4911 // 1111 0111 1001 0000 Rm1 Rn1 imm4 Rn2; add_asr Rm1, Rn1, imm4, Rn2
4912 8.0xf7+8.0x90+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_asr
4916 int srcreg1, dstreg1, dstreg2;
4920 srcreg1 = translate_rreg (SD_, RM1);
4921 dstreg1 = translate_rreg (SD_, RN1);
4922 dstreg2 = translate_rreg (SD_, RN2);
4924 State.regs[dstreg1] += State.regs[srcreg1];
4925 temp = State.regs[dstreg2];
4927 State.regs[dstreg2] = temp;
4930 // 1111 0111 1010 0000 Rm1 Rn1 Rm2 Rn2; add_lsr Rm1, Rn1, Rm2, Rn2
4931 8.0xf7+8.0xa0+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_lsr
4935 int srcreg1, srcreg2, dstreg1, dstreg2;
4938 srcreg1 = translate_rreg (SD_, RM1);
4939 srcreg2 = translate_rreg (SD_, RM2);
4940 dstreg1 = translate_rreg (SD_, RN1);
4941 dstreg2 = translate_rreg (SD_, RN2);
4943 State.regs[dstreg1] += State.regs[srcreg1];
4944 State.regs[dstreg2] >>= State.regs[srcreg2];
4947 // 1111 0111 1011 0000 Rm1 Rn1 imm4 Rn2; add_lsr Rm1, Rn1, imm4, Rn2
4948 8.0xf7+8.0xb0+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_lsr
4952 int srcreg1, dstreg1, dstreg2;
4956 srcreg1 = translate_rreg (SD_, RM1);
4957 dstreg1 = translate_rreg (SD_, RN1);
4958 dstreg2 = translate_rreg (SD_, RN2);
4960 State.regs[dstreg1] += State.regs[srcreg1];
4961 State.regs[dstreg2] >>= IMM4;
4965 // 1111 0111 1100 0000 Rm1 Rn1 Rm2 Rn2; add_asl Rm1, Rn1, Rm2, Rn2
4966 8.0xf7+8.0xc0+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_asl
4970 int srcreg1, srcreg2, dstreg1, dstreg2;
4973 srcreg1 = translate_rreg (SD_, RM1);
4974 srcreg2 = translate_rreg (SD_, RM2);
4975 dstreg1 = translate_rreg (SD_, RN1);
4976 dstreg2 = translate_rreg (SD_, RN2);
4978 State.regs[dstreg1] += State.regs[srcreg1];
4979 State.regs[dstreg2] <<= State.regs[srcreg2];
4982 // 1111 0111 1101 0000 Rm1 Rn1 imm4 Rn2; add_asl Rm1, Rn1, imm4, Rn2
4983 8.0xf7+8.0xd0+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_asl
4987 int srcreg1, dstreg1, dstreg2;
4991 srcreg1 = translate_rreg (SD_, RM1);
4992 dstreg1 = translate_rreg (SD_, RN1);
4993 dstreg2 = translate_rreg (SD_, RN2);
4995 State.regs[dstreg1] += State.regs[srcreg1];
4996 State.regs[dstreg2] <<= IMM4;
4999 // 1111 0111 0000 0001 Rm1 Rn1 Rm2 Rn2; cmp_add Rm1, Rn1, Rm2, Rn2
5000 8.0xf7+8.0x01+4.RM1,4.RN1+4.RM2,4.RN2:D2:::cmp_add
5004 int srcreg1, srcreg2, dstreg1, dstreg2;
5007 srcreg1 = translate_rreg (SD_, RM1);
5008 srcreg2 = translate_rreg (SD_, RM2);
5009 dstreg1 = translate_rreg (SD_, RN1);
5010 dstreg2 = translate_rreg (SD_, RN2);
5012 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5013 State.regs[dstreg2] += State.regs[srcreg2];
5016 // 1111 0111 0001 0001 Rm1 Rn1 imm4 Rn2; cmp_add Rm1, Rn1, imm4, Rn2
5017 8.0xf7+8.0x11+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::cmp_add
5021 int srcreg1, dstreg1, dstreg2;
5024 srcreg1 = translate_rreg (SD_, RM1);
5025 dstreg1 = translate_rreg (SD_, RN1);
5026 dstreg2 = translate_rreg (SD_, RN2);
5028 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5029 State.regs[dstreg2] += EXTEND4 (IMM4);
5032 // 1111 0111 0010 0001 Rm1 Rn1 Rm2 Rn2; cmp_sub Rm1, Rn1, Rm2, Rn2
5033 8.0xf7+8.0x21+4.RM1,4.RN1+4.RM2,4.RN2:D2:::cmp_sub
5037 int srcreg1, srcreg2, dstreg1, dstreg2;
5040 srcreg1 = translate_rreg (SD_, RM1);
5041 srcreg2 = translate_rreg (SD_, RM2);
5042 dstreg1 = translate_rreg (SD_, RN1);
5043 dstreg2 = translate_rreg (SD_, RN2);
5045 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5046 State.regs[dstreg2] -= State.regs[srcreg2];
5049 // 1111 0111 0011 0001 Rm1 Rn1 imm4 Rn2; cmp_sub Rm1, Rn1, imm4, Rn2
5050 8.0xf7+8.0x31+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::cmp_sub
5054 int srcreg1, dstreg1, dstreg2;
5057 srcreg1 = translate_rreg (SD_, RM1);
5058 dstreg1 = translate_rreg (SD_, RN1);
5059 dstreg2 = translate_rreg (SD_, RN2);
5061 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5062 State.regs[dstreg2] -= EXTEND4 (IMM4);
5065 // 1111 0111 0110 0001 Rm1 Rn1 Rm2 Rn2; cmp_mov Rm1, Rn1, Rm2, Rn2
5066 8.0xf7+8.0x61+4.RM1,4.RN1+4.RM2,4.RN2:D2:::cmp_mov
5070 int srcreg1, srcreg2, dstreg1, dstreg2;
5073 srcreg1 = translate_rreg (SD_, RM1);
5074 srcreg2 = translate_rreg (SD_, RM2);
5075 dstreg1 = translate_rreg (SD_, RN1);
5076 dstreg2 = translate_rreg (SD_, RN2);
5078 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5079 State.regs[dstreg2] = State.regs[srcreg2];
5082 // 1111 0111 0111 0001 Rm1 Rn1 imm4 Rn2; cmp_mov Rm1, Rn1, imm4, Rn2
5083 8.0xf7+8.0x71+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::cmp_mov
5087 int srcreg1, dstreg1, dstreg2;
5090 srcreg1 = translate_rreg (SD_, RM1);
5091 dstreg1 = translate_rreg (SD_, RN1);
5092 dstreg2 = translate_rreg (SD_, RN2);
5094 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5095 State.regs[dstreg2] = EXTEND4 (IMM4);
5098 // 1111 0111 1000 0001 Rm1 Rn1 Rm2 Rn2; cmp_asr Rm1, Rn1, Rm2, Rn2
5099 8.0xf7+8.0x81+4.RM1,4.RN1+4.RM2,4.RN2:D2:::cmp_asr
5103 int srcreg1, srcreg2, dstreg1, dstreg2;
5107 srcreg1 = translate_rreg (SD_, RM1);
5108 srcreg2 = translate_rreg (SD_, RM2);
5109 dstreg1 = translate_rreg (SD_, RN1);
5110 dstreg2 = translate_rreg (SD_, RN2);
5112 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5113 temp = State.regs[dstreg2];
5114 temp >>= State.regs[srcreg2];
5115 State.regs[dstreg2] = temp;
5118 // 1111 0111 1001 0001 Rm1 Rn1 imm4 Rn2; cmp_asr Rm1, Rn1, imm4, Rn2
5119 8.0xf7+8.0x91+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::cmp_asr
5123 int srcreg1, dstreg1, dstreg2;
5127 srcreg1 = translate_rreg (SD_, RM1);
5128 dstreg1 = translate_rreg (SD_, RN1);
5129 dstreg2 = translate_rreg (SD_, RN2);
5131 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5132 temp = State.regs[dstreg2];
5134 State.regs[dstreg2] = temp;
5137 // 1111 0111 1010 0001 Rm1 Rn1 Rm2 Rn2; cmp_lsr Rm1, Rn1, Rm2, Rn2
5138 8.0xf7+8.0xa1+4.RM1,4.RN1+4.RM2,4.RN2:D2:::cmp_lsr
5142 int srcreg1, srcreg2, dstreg1, dstreg2;
5145 srcreg1 = translate_rreg (SD_, RM1);
5146 srcreg2 = translate_rreg (SD_, RM2);
5147 dstreg1 = translate_rreg (SD_, RN1);
5148 dstreg2 = translate_rreg (SD_, RN2);
5150 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5151 State.regs[dstreg2] >>= State.regs[srcreg2];
5154 // 1111 0111 1011 0001 Rm1 Rn1 imm4 Rn2; cmp_lsr Rm1, Rn1, imm4, Rn2
5155 8.0xf7+8.0xb1+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::cmp_lsr
5159 int srcreg1, dstreg1, dstreg2;
5163 srcreg1 = translate_rreg (SD_, RM1);
5164 dstreg1 = translate_rreg (SD_, RN1);
5165 dstreg2 = translate_rreg (SD_, RN2);
5167 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5168 State.regs[dstreg2] >>= IMM4;
5172 // 1111 0111 1100 0001 Rm1 Rn1 Rm2 Rn2; cmp_asl Rm1, Rn1, Rm2, Rn2
5173 8.0xf7+8.0xc1+4.RM1,4.RN1+4.RM2,4.RN2:D2:::cmp_asl
5177 int srcreg1, srcreg2, dstreg1, dstreg2;
5180 srcreg1 = translate_rreg (SD_, RM1);
5181 srcreg2 = translate_rreg (SD_, RM2);
5182 dstreg1 = translate_rreg (SD_, RN1);
5183 dstreg2 = translate_rreg (SD_, RN2);
5185 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5186 State.regs[dstreg2] <<= State.regs[srcreg2];
5189 // 1111 0111 1101 0001 Rm1 Rn1 imm4 Rn2; cmp_asl Rm1, Rn1, imm4, Rn2
5190 8.0xf7+8.0xd1+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::cmp_asl
5194 int srcreg1, dstreg1, dstreg2;
5198 srcreg1 = translate_rreg (SD_, RM1);
5199 dstreg1 = translate_rreg (SD_, RN1);
5200 dstreg2 = translate_rreg (SD_, RN2);
5202 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5203 State.regs[dstreg2] <<= IMM4;
5206 // 1111 0111 0000 0010 Rm1 Rn1 Rm2 Rn2; sub_add Rm1, Rn1, Rm2, Rn2
5207 8.0xf7+8.0x02+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_add
5211 int srcreg1, srcreg2, dstreg1, dstreg2;
5214 srcreg1 = translate_rreg (SD_, RM1);
5215 srcreg2 = translate_rreg (SD_, RM2);
5216 dstreg1 = translate_rreg (SD_, RN1);
5217 dstreg2 = translate_rreg (SD_, RN2);
5219 State.regs[dstreg1] -= State.regs[srcreg1];
5220 State.regs[dstreg2] += State.regs[srcreg2];
5223 // 1111 0111 0001 0010 Rm1 Rn1 imm4 Rn2; sub_add Rm1, Rn1, imm4, Rn2
5224 8.0xf7+8.0x12+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_add
5228 int srcreg1, dstreg1, dstreg2;
5231 srcreg1 = translate_rreg (SD_, RM1);
5232 dstreg1 = translate_rreg (SD_, RN1);
5233 dstreg2 = translate_rreg (SD_, RN2);
5235 State.regs[dstreg1] -= State.regs[srcreg1];
5236 State.regs[dstreg2] += EXTEND4 (IMM4);
5239 // 1111 0111 0010 0010 Rm1 Rn1 Rm2 Rn2; sub_sub Rm1, Rn1, Rm2, Rn2
5240 8.0xf7+8.0x22+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_sub
5244 int srcreg1, srcreg2, dstreg1, dstreg2;
5247 srcreg1 = translate_rreg (SD_, RM1);
5248 srcreg2 = translate_rreg (SD_, RM2);
5249 dstreg1 = translate_rreg (SD_, RN1);
5250 dstreg2 = translate_rreg (SD_, RN2);
5252 State.regs[dstreg1] -= State.regs[srcreg1];
5253 State.regs[dstreg2] -= State.regs[srcreg2];
5256 // 1111 0111 0011 0010 Rm1 Rn1 imm4 Rn2; sub_sub Rm1, Rn1, imm4, Rn2
5257 8.0xf7+8.0x32+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_sub
5261 int srcreg1, dstreg1, dstreg2;
5264 srcreg1 = translate_rreg (SD_, RM1);
5265 dstreg1 = translate_rreg (SD_, RN1);
5266 dstreg2 = translate_rreg (SD_, RN2);
5268 State.regs[dstreg1] -= State.regs[srcreg1];
5269 State.regs[dstreg2] -= EXTEND4 (IMM4);
5272 // 1111 0111 0100 0010 Rm1 Rn1 Rm2 Rn2; sub_cmp Rm1, Rn1, Rm2, Rn2
5273 8.0xf7+8.0x42+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_cmp
5277 int srcreg1, srcreg2, dstreg1, dstreg2;
5280 srcreg1 = translate_rreg (SD_, RM1);
5281 srcreg2 = translate_rreg (SD_, RM2);
5282 dstreg1 = translate_rreg (SD_, RN1);
5283 dstreg2 = translate_rreg (SD_, RN2);
5285 State.regs[dstreg1] -= State.regs[srcreg1];
5286 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
5289 // 1111 0111 0101 0010 Rm1 Rn1 imm4 Rn2; sub_cmp Rm1, Rn1, imm4, Rn2
5290 8.0xf7+8.0x52+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_cmp
5294 int srcreg1, dstreg1, dstreg2;
5297 srcreg1 = translate_rreg (SD_, RM1);
5298 dstreg1 = translate_rreg (SD_, RN1);
5299 dstreg2 = translate_rreg (SD_, RN2);
5301 State.regs[dstreg1] -= State.regs[srcreg1];
5302 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
5305 // 1111 0111 0110 0010 Rm1 Rn1 Rm2 Rn2; sub_mov Rm1, Rn1, Rm2, Rn2
5306 8.0xf7+8.0x62+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_mov
5310 int srcreg1, srcreg2, dstreg1, dstreg2;
5313 srcreg1 = translate_rreg (SD_, RM1);
5314 srcreg2 = translate_rreg (SD_, RM2);
5315 dstreg1 = translate_rreg (SD_, RN1);
5316 dstreg2 = translate_rreg (SD_, RN2);
5318 State.regs[dstreg1] -= State.regs[srcreg1];
5319 State.regs[dstreg2] = State.regs[srcreg2];
5322 // 1111 0111 0111 0010 Rm1 Rn1 imm4 Rn2; sub_mov Rm1, Rn1, imm4, Rn2
5323 8.0xf7+8.0x72+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_mov
5327 int srcreg1, dstreg1, dstreg2;
5330 srcreg1 = translate_rreg (SD_, RM1);
5331 dstreg1 = translate_rreg (SD_, RN1);
5332 dstreg2 = translate_rreg (SD_, RN2);
5334 State.regs[dstreg1] -= State.regs[srcreg1];
5335 State.regs[dstreg2] = EXTEND4 (IMM4);
5338 // 1111 0111 1000 0010 Rm1 Rn1 Rm2 Rn2; sub_asr Rm1, Rn1, Rm2, Rn2
5339 8.0xf7+8.0x82+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_asr
5343 int srcreg1, srcreg2, dstreg1, dstreg2;
5347 srcreg1 = translate_rreg (SD_, RM1);
5348 srcreg2 = translate_rreg (SD_, RM2);
5349 dstreg1 = translate_rreg (SD_, RN1);
5350 dstreg2 = translate_rreg (SD_, RN2);
5352 State.regs[dstreg1] -= State.regs[srcreg1];
5353 temp = State.regs[dstreg2];
5354 temp >>= State.regs[srcreg2];
5355 State.regs[dstreg2] = temp;
5358 // 1111 0111 1001 0010 Rm1 Rn1 imm4 Rn2; sub_asr Rm1, Rn1, imm4, Rn2
5359 8.0xf7+8.0x92+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_asr
5363 int srcreg1, dstreg1, dstreg2;
5367 srcreg1 = translate_rreg (SD_, RM1);
5368 dstreg1 = translate_rreg (SD_, RN1);
5369 dstreg2 = translate_rreg (SD_, RN2);
5371 State.regs[dstreg1] -= State.regs[srcreg1];
5372 temp = State.regs[dstreg2];
5374 State.regs[dstreg2] = temp;
5377 // 1111 0111 1010 0010 Rm1 Rn1 Rm2 Rn2; sub_lsr Rm1, Rn1, Rm2, Rn2
5378 8.0xf7+8.0xa2+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_lsr
5382 int srcreg1, srcreg2, dstreg1, dstreg2;
5385 srcreg1 = translate_rreg (SD_, RM1);
5386 srcreg2 = translate_rreg (SD_, RM2);
5387 dstreg1 = translate_rreg (SD_, RN1);
5388 dstreg2 = translate_rreg (SD_, RN2);
5390 State.regs[dstreg1] -= State.regs[srcreg1];
5391 State.regs[dstreg2] >>= State.regs[srcreg2];
5394 // 1111 0111 1011 0010 Rm1 Rn1 imm4 Rn2; sub_lsr Rm1, Rn1, imm4, Rn2
5395 8.0xf7+8.0xb2+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_lsr
5399 int srcreg1, dstreg1, dstreg2;
5403 srcreg1 = translate_rreg (SD_, RM1);
5404 dstreg1 = translate_rreg (SD_, RN1);
5405 dstreg2 = translate_rreg (SD_, RN2);
5407 State.regs[dstreg1] -= State.regs[srcreg1];
5408 State.regs[dstreg2] >>= IMM4;
5412 // 1111 0111 1100 0010 Rm1 Rn1 Rm2 Rn2; sub_asl Rm1, Rn1, Rm2, Rn2
5413 8.0xf7+8.0xc2+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_asl
5417 int srcreg1, srcreg2, dstreg1, dstreg2;
5420 srcreg1 = translate_rreg (SD_, RM1);
5421 srcreg2 = translate_rreg (SD_, RM2);
5422 dstreg1 = translate_rreg (SD_, RN1);
5423 dstreg2 = translate_rreg (SD_, RN2);
5425 State.regs[dstreg1] -= State.regs[srcreg1];
5426 State.regs[dstreg2] <<= State.regs[srcreg2];
5429 // 1111 0111 1101 0010 Rm1 Rn1 imm4 Rn2; sub_asl Rm1, Rn1, imm4, Rn2
5430 8.0xf7+8.0xd2+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_asl
5434 int srcreg1, dstreg1, dstreg2;
5438 srcreg1 = translate_rreg (SD_, RM1);
5439 dstreg1 = translate_rreg (SD_, RN1);
5440 dstreg2 = translate_rreg (SD_, RN2);
5442 State.regs[dstreg1] -= State.regs[srcreg1];
5443 State.regs[dstreg2] <<= IMM4;
5446 // 1111 0111 0000 0011 Rm1 Rn1 Rm2 Rn2; mov_add Rm1, Rn1, Rm2, Rn2
5447 8.0xf7+8.0x03+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_add
5451 int srcreg1, srcreg2, dstreg1, dstreg2;
5454 srcreg1 = translate_rreg (SD_, RM1);
5455 srcreg2 = translate_rreg (SD_, RM2);
5456 dstreg1 = translate_rreg (SD_, RN1);
5457 dstreg2 = translate_rreg (SD_, RN2);
5459 State.regs[dstreg1] = State.regs[srcreg1];
5460 State.regs[dstreg2] += State.regs[srcreg2];
5463 // 1111 0111 0001 0011 Rm1 Rn1 imm4 Rn2; mov_add Rm1, Rn1, imm4, Rn2
5464 8.0xf7+8.0x13+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_add
5468 int srcreg1, dstreg1, dstreg2;
5471 srcreg1 = translate_rreg (SD_, RM1);
5472 dstreg1 = translate_rreg (SD_, RN1);
5473 dstreg2 = translate_rreg (SD_, RN2);
5475 State.regs[dstreg1] = State.regs[srcreg1];
5476 State.regs[dstreg2] += EXTEND4 (IMM4);
5479 // 1111 0111 0010 0011 Rm1 Rn1 Rm2 Rn2; mov_sub Rm1, Rn1, Rm2, Rn2
5480 8.0xf7+8.0x23+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_sub
5484 int srcreg1, srcreg2, dstreg1, dstreg2;
5487 srcreg1 = translate_rreg (SD_, RM1);
5488 srcreg2 = translate_rreg (SD_, RM2);
5489 dstreg1 = translate_rreg (SD_, RN1);
5490 dstreg2 = translate_rreg (SD_, RN2);
5492 State.regs[dstreg1] = State.regs[srcreg1];
5493 State.regs[dstreg2] -= State.regs[srcreg2];
5496 // 1111 0111 0011 0011 Rm1 Rn1 imm4 Rn2; mov_sub Rm1, Rn1, imm4, Rn2
5497 8.0xf7+8.0x33+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_sub
5501 int srcreg1, dstreg1, dstreg2;
5504 srcreg1 = translate_rreg (SD_, RM1);
5505 dstreg1 = translate_rreg (SD_, RN1);
5506 dstreg2 = translate_rreg (SD_, RN2);
5508 State.regs[dstreg1] = State.regs[srcreg1];
5509 State.regs[dstreg2] -= EXTEND4 (IMM4);
5512 // 1111 0111 0100 0011 Rm1 Rn1 Rm2 Rn2; mov_cmp Rm1, Rn1, Rm2, Rn2
5513 8.0xf7+8.0x43+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_cmp
5517 int srcreg1, srcreg2, dstreg1, dstreg2;
5520 srcreg1 = translate_rreg (SD_, RM1);
5521 srcreg2 = translate_rreg (SD_, RM2);
5522 dstreg1 = translate_rreg (SD_, RN1);
5523 dstreg2 = translate_rreg (SD_, RN2);
5525 State.regs[dstreg1] = State.regs[srcreg1];
5526 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
5529 // 1111 0111 0101 0011 Rm1 Rn1 imm4 Rn2; mov_cmp Rm1, Rn1, imm4, Rn2
5530 8.0xf7+8.0x53+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_cmp
5534 int srcreg1, dstreg1, dstreg2;
5537 srcreg1 = translate_rreg (SD_, RM1);
5538 dstreg1 = translate_rreg (SD_, RN1);
5539 dstreg2 = translate_rreg (SD_, RN2);
5541 State.regs[dstreg1] = State.regs[srcreg1];
5542 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
5545 // 1111 0111 0110 0011 Rm1 Rn1 Rm2 Rn2; mov_mov Rm1, Rn1, Rm2, Rn2
5546 8.0xf7+8.0x63+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_mov
5550 int srcreg1, srcreg2, dstreg1, dstreg2;
5553 srcreg1 = translate_rreg (SD_, RM1);
5554 srcreg2 = translate_rreg (SD_, RM2);
5555 dstreg1 = translate_rreg (SD_, RN1);
5556 dstreg2 = translate_rreg (SD_, RN2);
5558 State.regs[dstreg1] = State.regs[srcreg1];
5559 State.regs[dstreg2] = State.regs[srcreg2];
5562 // 1111 0111 0111 0011 Rm1 Rn1 imm4 Rn2; mov_mov Rm1, Rn1, imm4, Rn2
5563 8.0xf7+8.0x73+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_mov
5567 int srcreg1, dstreg1, dstreg2;
5570 srcreg1 = translate_rreg (SD_, RM1);
5571 dstreg1 = translate_rreg (SD_, RN1);
5572 dstreg2 = translate_rreg (SD_, RN2);
5574 State.regs[dstreg1] = State.regs[srcreg1];
5575 State.regs[dstreg2] = EXTEND4 (IMM4);
5578 // 1111 0111 1000 0011 Rm1 Rn1 Rm2 Rn2; mov_asr Rm1, Rn1, Rm2, Rn2
5579 8.0xf7+8.0x83+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_asr
5583 int srcreg1, srcreg2, dstreg1, dstreg2;
5587 srcreg1 = translate_rreg (SD_, RM1);
5588 srcreg2 = translate_rreg (SD_, RM2);
5589 dstreg1 = translate_rreg (SD_, RN1);
5590 dstreg2 = translate_rreg (SD_, RN2);
5592 State.regs[dstreg1] = State.regs[srcreg1];
5593 temp = State.regs[dstreg2];
5594 temp >>= State.regs[srcreg2];
5595 State.regs[dstreg2] = temp;
5598 // 1111 0111 1001 0011 Rm1 Rn1 imm4 Rn2; mov_asr Rm1, Rn1, imm4, Rn2
5599 8.0xf7+8.0x93+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_asr
5603 int srcreg1, dstreg1, dstreg2;
5607 srcreg1 = translate_rreg (SD_, RM1);
5608 dstreg1 = translate_rreg (SD_, RN1);
5609 dstreg2 = translate_rreg (SD_, RN2);
5611 State.regs[dstreg1] = State.regs[srcreg1];
5612 temp = State.regs[dstreg2];
5614 State.regs[dstreg2] = temp;
5617 // 1111 0111 1010 0011 Rm1 Rn1 Rm2 Rn2; mov_lsr Rm1, Rn1, Rm2, Rn2
5618 8.0xf7+8.0xa3+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_lsr
5622 int srcreg1, srcreg2, dstreg1, dstreg2;
5625 srcreg1 = translate_rreg (SD_, RM1);
5626 srcreg2 = translate_rreg (SD_, RM2);
5627 dstreg1 = translate_rreg (SD_, RN1);
5628 dstreg2 = translate_rreg (SD_, RN2);
5630 State.regs[dstreg1] = State.regs[srcreg1];
5631 State.regs[dstreg2] >>= State.regs[srcreg2];
5634 // 1111 0111 1011 0011 Rm1 Rn1 imm4 Rn2; mov_lsr Rm1, Rn1, imm4, Rn2
5635 8.0xf7+8.0xb3+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_lsr
5639 int srcreg1, dstreg1, dstreg2;
5643 srcreg1 = translate_rreg (SD_, RM1);
5644 dstreg1 = translate_rreg (SD_, RN1);
5645 dstreg2 = translate_rreg (SD_, RN2);
5647 State.regs[dstreg1] = State.regs[srcreg1];
5648 State.regs[dstreg2] >>= IMM4;
5652 // 1111 0111 1100 0011 Rm1 Rn1 Rm2 Rn2; mov_asl Rm1, Rn1, Rm2, Rn2
5653 8.0xf7+8.0xc3+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_asl
5657 int srcreg1, srcreg2, dstreg1, dstreg2;
5660 srcreg1 = translate_rreg (SD_, RM1);
5661 srcreg2 = translate_rreg (SD_, RM2);
5662 dstreg1 = translate_rreg (SD_, RN1);
5663 dstreg2 = translate_rreg (SD_, RN2);
5665 State.regs[dstreg1] = State.regs[srcreg1];
5666 State.regs[dstreg2] <<= State.regs[srcreg2];
5669 // 1111 0111 1101 0011 Rm1 Rn1 imm4 Rn2; mov_asl Rm1, Rn1, imm4, Rn2
5670 8.0xf7+8.0xd3+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_asl
5674 int srcreg1, dstreg1, dstreg2;
5678 srcreg1 = translate_rreg (SD_, RM1);
5679 dstreg1 = translate_rreg (SD_, RN1);
5680 dstreg2 = translate_rreg (SD_, RN2);
5682 State.regs[dstreg1] = State.regs[srcreg1];
5683 State.regs[dstreg2] <<= IMM4;
5686 // 1111 0111 0000 0100 imm4 Rn1 Rm2 Rn2; add_add imm4, Rn1, Rm2, Rn2
5687 8.0xf7+8.0x04+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_add
5691 int srcreg2, dstreg1, dstreg2;
5694 srcreg2 = translate_rreg (SD_, RM2);
5695 dstreg1 = translate_rreg (SD_, RN1);
5696 dstreg2 = translate_rreg (SD_, RN2);
5698 State.regs[dstreg1] += EXTEND4 (IMM4A);
5699 State.regs[dstreg2] += State.regs[srcreg2];
5702 // 1111 0111 0001 0100 imm4 Rn1 imm4 Rn2; add_add imm4, Rn1, imm4, Rn2
5703 8.0xf7+8.0x14+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_add
5707 int dstreg1, dstreg2;
5710 dstreg1 = translate_rreg (SD_, RN1);
5711 dstreg2 = translate_rreg (SD_, RN2);
5713 State.regs[dstreg1] += EXTEND4 (IMM4A);
5714 State.regs[dstreg2] += EXTEND4 (IMM4);
5717 // 1111 0111 0010 0100 imm4 Rn1 Rm2 Rn2; add_sub imm4, Rn1, Rm2, Rn2
5718 8.0xf7+8.0x24+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_sub
5722 int srcreg2, dstreg1, dstreg2;
5725 srcreg2 = translate_rreg (SD_, RM2);
5726 dstreg1 = translate_rreg (SD_, RN1);
5727 dstreg2 = translate_rreg (SD_, RN2);
5729 State.regs[dstreg1] += EXTEND4 (IMM4A);
5730 State.regs[dstreg2] -= State.regs[srcreg2];
5733 // 1111 0111 0011 0100 imm4 Rn1 imm4 Rn2; add_sub imm4, Rn1, imm4, Rn2
5734 8.0xf7+8.0x34+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_sub
5738 int dstreg1, dstreg2;
5741 dstreg1 = translate_rreg (SD_, RN1);
5742 dstreg2 = translate_rreg (SD_, RN2);
5744 State.regs[dstreg1] += EXTEND4 (IMM4A);
5745 State.regs[dstreg2] -= EXTEND4 (IMM4);
5748 // 1111 0111 0100 0100 imm4 Rn1 Rm2 Rn2; add_cmp imm4, Rn1, Rm2, Rn2
5749 8.0xf7+8.0x44+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_cmp
5753 int srcreg2, dstreg1, dstreg2;
5756 srcreg2 = translate_rreg (SD_, RM2);
5757 dstreg1 = translate_rreg (SD_, RN1);
5758 dstreg2 = translate_rreg (SD_, RN2);
5760 State.regs[dstreg1] += EXTEND4 (IMM4A);
5761 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
5764 // 1111 0111 0101 0100 imm4 Rn1 imm4 Rn2; add_cmp imm4, Rn1, imm4, Rn2
5765 8.0xf7+8.0x54+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_cmp
5769 int dstreg1, dstreg2;
5772 dstreg1 = translate_rreg (SD_, RN1);
5773 dstreg2 = translate_rreg (SD_, RN2);
5775 State.regs[dstreg1] += EXTEND4 (IMM4A);
5776 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
5779 // 1111 0111 0110 0100 imm4 Rn1 Rm2 Rn2; add_mov imm4, Rn1, Rm2, Rn2
5780 8.0xf7+8.0x64+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_mov
5784 int srcreg2, dstreg1, dstreg2;
5787 srcreg2 = translate_rreg (SD_, RM2);
5788 dstreg1 = translate_rreg (SD_, RN1);
5789 dstreg2 = translate_rreg (SD_, RN2);
5791 State.regs[dstreg1] += EXTEND4 (IMM4A);
5792 State.regs[dstreg2] = State.regs[srcreg2];
5795 // 1111 0111 0111 0100 imm4 Rn1 imm4 Rn2; add_mov imm4, Rn1, imm4, Rn2
5796 8.0xf7+8.0x74+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_mov
5800 int dstreg1, dstreg2;
5803 dstreg1 = translate_rreg (SD_, RN1);
5804 dstreg2 = translate_rreg (SD_, RN2);
5806 State.regs[dstreg1] += EXTEND4 (IMM4A);
5807 State.regs[dstreg2] = EXTEND4 (IMM4);
5810 // 1111 0111 1000 0100 imm4 Rn1 Rm2 Rn2; add_asr imm4, Rn1, Rm2, Rn2
5811 8.0xf7+8.0x84+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_asr
5815 int srcreg2, dstreg1, dstreg2;
5819 srcreg2 = translate_rreg (SD_, RM2);
5820 dstreg1 = translate_rreg (SD_, RN1);
5821 dstreg2 = translate_rreg (SD_, RN2);
5823 State.regs[dstreg1] += EXTEND4 (IMM4A);
5824 temp = State.regs[dstreg2];
5825 temp >>= State.regs[srcreg2];
5826 State.regs[dstreg2] = temp;
5829 // 1111 0111 1001 0100 imm4 Rn1 imm4 Rn2; add_asr imm4, Rn1, imm4, Rn2
5830 8.0xf7+8.0x94+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_asr
5834 int dstreg1, dstreg2;
5838 dstreg1 = translate_rreg (SD_, RN1);
5839 dstreg2 = translate_rreg (SD_, RN2);
5841 State.regs[dstreg1] += EXTEND4 (IMM4A);
5842 temp = State.regs[dstreg2];
5844 State.regs[dstreg2] = temp;
5847 // 1111 0111 1010 0100 imm4 Rn1 Rm2 Rn2; add_lsr imm4, Rn1, Rm2, Rn2
5848 8.0xf7+8.0xa4+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_lsr
5852 int srcreg2, dstreg1, dstreg2;
5855 srcreg2 = translate_rreg (SD_, RM2);
5856 dstreg1 = translate_rreg (SD_, RN1);
5857 dstreg2 = translate_rreg (SD_, RN2);
5859 State.regs[dstreg1] += EXTEND4 (IMM4A);
5860 State.regs[dstreg2] >>= State.regs[srcreg2];
5863 // 1111 0111 1011 0100 imm4 Rn1 imm4 Rn2; add_lsr imm4, Rn1, imm4, Rn2
5864 8.0xf7+8.0xb4+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_lsr
5868 int dstreg1, dstreg2;
5872 dstreg1 = translate_rreg (SD_, RN1);
5873 dstreg2 = translate_rreg (SD_, RN2);
5875 State.regs[dstreg1] += EXTEND4 (IMM4A);
5876 State.regs[dstreg2] >>= IMM4;
5880 // 1111 0111 1100 0100 imm4 Rn1 Rm2 Rn2; add_asl imm4, Rn1, Rm2, Rn2
5881 8.0xf7+8.0xc4+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_asl
5885 int srcreg2, dstreg1, dstreg2;
5888 srcreg2 = translate_rreg (SD_, RM2);
5889 dstreg1 = translate_rreg (SD_, RN1);
5890 dstreg2 = translate_rreg (SD_, RN2);
5892 State.regs[dstreg1] += EXTEND4 (IMM4A);
5893 State.regs[dstreg2] <<= State.regs[srcreg2];
5896 // 1111 0111 1101 0100 imm4 Rn1 imm4 Rn2; add_asl imm4, Rn1, imm4, Rn2
5897 8.0xf7+8.0xd4+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_asl
5901 int dstreg1, dstreg2;
5905 dstreg1 = translate_rreg (SD_, RN1);
5906 dstreg2 = translate_rreg (SD_, RN2);
5908 State.regs[dstreg1] += EXTEND4 (IMM4A);
5909 State.regs[dstreg2] <<= IMM4;
5912 // 1111 0111 0000 0101 imm4 Rn1 Rm2 Rn2; cmp_add imm4, Rn1, Rm2, Rn2
5913 8.0xf7+8.0x05+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::cmp_add
5917 int srcreg2, dstreg1, dstreg2;
5920 srcreg2 = translate_rreg (SD_, RM2);
5921 dstreg1 = translate_rreg (SD_, RN1);
5922 dstreg2 = translate_rreg (SD_, RN2);
5924 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
5925 State.regs[dstreg2] += State.regs[srcreg2];
5928 // 1111 0111 0001 0101 imm4 Rn1 imm4 Rn2; cmp_add imm4, Rn1, imm4, Rn2
5929 8.0xf7+8.0x15+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::cmp_add
5933 int dstreg1, dstreg2;
5936 dstreg1 = translate_rreg (SD_, RN1);
5937 dstreg2 = translate_rreg (SD_, RN2);
5939 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
5940 State.regs[dstreg2] += EXTEND4 (IMM4);
5943 // 1111 0111 0010 0101 imm4 Rn1 Rm2 Rn2; cmp_sub imm4, Rn1, Rm2, Rn2
5944 8.0xf7+8.0x25+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::cmp_sub
5948 int srcreg2, dstreg1, dstreg2;
5951 srcreg2 = translate_rreg (SD_, RM2);
5952 dstreg1 = translate_rreg (SD_, RN1);
5953 dstreg2 = translate_rreg (SD_, RN2);
5955 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
5956 State.regs[dstreg2] -= State.regs[srcreg2];
5959 // 1111 0111 0011 0101 imm4 Rn1 imm4 Rn2; cmp_sub imm4, Rn1, imm4, Rn2
5960 8.0xf7+8.0x35+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::cmp_sub
5964 int dstreg1, dstreg2;
5967 dstreg1 = translate_rreg (SD_, RN1);
5968 dstreg2 = translate_rreg (SD_, RN2);
5970 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
5971 State.regs[dstreg2] -= EXTEND4 (IMM4);
5974 // 1111 0111 0110 0101 imm4 Rn1 Rm2 Rn2; cmp_mov imm4, Rn1, Rm2, Rn2
5975 8.0xf7+8.0x65+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::cmp_mov
5979 int srcreg2, dstreg1, dstreg2;
5982 srcreg2 = translate_rreg (SD_, RM2);
5983 dstreg1 = translate_rreg (SD_, RN1);
5984 dstreg2 = translate_rreg (SD_, RN2);
5986 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
5987 State.regs[dstreg2] = State.regs[srcreg2];
5990 // 1111 0111 0111 0101 imm4 Rn1 imm4 Rn2; cmp_mov imm4, Rn1, imm4, Rn2
5991 8.0xf7+8.0x75+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::cmp_mov
5995 int dstreg1, dstreg2;
5998 dstreg1 = translate_rreg (SD_, RN1);
5999 dstreg2 = translate_rreg (SD_, RN2);
6001 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6002 State.regs[dstreg2] = EXTEND4 (IMM4);
6005 // 1111 0111 1000 0101 imm4 Rn1 Rm2 Rn2; cmp_asr imm4, Rn1, Rm2, Rn2
6006 8.0xf7+8.0x85+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::cmp_asr
6010 int srcreg2, dstreg1, dstreg2;
6014 srcreg2 = translate_rreg (SD_, RM2);
6015 dstreg1 = translate_rreg (SD_, RN1);
6016 dstreg2 = translate_rreg (SD_, RN2);
6018 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6019 temp = State.regs[dstreg2];
6020 temp >>= State.regs[srcreg2];
6021 State.regs[dstreg2] = temp;
6024 // 1111 0111 1001 0101 imm4 Rn1 imm4 Rn2; cmp_asr imm4, Rn1, imm4, Rn2
6025 8.0xf7+8.0x95+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::cmp_asr
6029 int dstreg1, dstreg2;
6033 dstreg1 = translate_rreg (SD_, RN1);
6034 dstreg2 = translate_rreg (SD_, RN2);
6036 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6037 temp = State.regs[dstreg2];
6039 State.regs[dstreg2] = temp;
6042 // 1111 0111 1010 0101 imm4 Rn1 Rm2 Rn2; cmp_lsr imm4, Rn1, Rm2, Rn2
6043 8.0xf7+8.0xa5+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::cmp_lsr
6047 int srcreg2, dstreg1, dstreg2;
6050 srcreg2 = translate_rreg (SD_, RM2);
6051 dstreg1 = translate_rreg (SD_, RN1);
6052 dstreg2 = translate_rreg (SD_, RN2);
6054 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6055 State.regs[dstreg2] >>= State.regs[srcreg2];
6058 // 1111 0111 1011 0101 imm4 Rn1 imm4 Rn2; cmp_lsr imm4, Rn1, imm4, Rn2
6059 8.0xf7+8.0xb5+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::cmp_lsr
6063 int dstreg1, dstreg2;
6067 dstreg1 = translate_rreg (SD_, RN1);
6068 dstreg2 = translate_rreg (SD_, RN2);
6070 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6071 State.regs[dstreg2] >>= IMM4;
6075 // 1111 0111 1100 0101 imm4 Rn1 Rm2 Rn2; cmp_asl imm4, Rn1, Rm2, Rn2
6076 8.0xf7+8.0xc5+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::cmp_asl
6080 int srcreg2, dstreg1, dstreg2;
6083 srcreg2 = translate_rreg (SD_, RM2);
6084 dstreg1 = translate_rreg (SD_, RN1);
6085 dstreg2 = translate_rreg (SD_, RN2);
6087 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6088 State.regs[dstreg2] <<= State.regs[srcreg2];
6091 // 1111 0111 1101 0101 imm4 Rn1 imm4 Rn2; cmp_asl imm4, Rn1, imm4, Rn2
6092 8.0xf7+8.0xd5+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::cmp_asl
6096 int dstreg1, dstreg2;
6100 dstreg1 = translate_rreg (SD_, RN1);
6101 dstreg2 = translate_rreg (SD_, RN2);
6103 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6104 State.regs[dstreg2] <<= IMM4;
6107 // 1111 0111 0000 0110 imm4 Rn1 Rm2 Rn2; sub_add imm4, Rn1, Rm2, Rn2
6108 8.0xf7+8.0x06+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_add
6112 int srcreg2, dstreg1, dstreg2;
6115 srcreg2 = translate_rreg (SD_, RM2);
6116 dstreg1 = translate_rreg (SD_, RN1);
6117 dstreg2 = translate_rreg (SD_, RN2);
6119 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6120 State.regs[dstreg2] += State.regs[srcreg2];
6123 // 1111 0111 0001 0110 imm4 Rn1 imm4 Rn2; sub_add imm4, Rn1, imm4, Rn2
6124 8.0xf7+8.0x16+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_add
6128 int dstreg1, dstreg2;
6131 dstreg1 = translate_rreg (SD_, RN1);
6132 dstreg2 = translate_rreg (SD_, RN2);
6134 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6135 State.regs[dstreg2] += EXTEND4 (IMM4);
6138 // 1111 0111 0010 0110 imm4 Rn1 Rm2 Rn2; sub_sub imm4, Rn1, Rm2, Rn2
6139 8.0xf7+8.0x26+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_sub
6143 int srcreg2, dstreg1, dstreg2;
6146 srcreg2 = translate_rreg (SD_, RM2);
6147 dstreg1 = translate_rreg (SD_, RN1);
6148 dstreg2 = translate_rreg (SD_, RN2);
6150 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6151 State.regs[dstreg2] -= State.regs[srcreg2];
6154 // 1111 0111 0011 0110 imm4 Rn1 imm4 Rn2; sub_sub imm4, Rn1, imm4, Rn2
6155 8.0xf7+8.0x36+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_sub
6159 int dstreg1, dstreg2;
6162 dstreg1 = translate_rreg (SD_, RN1);
6163 dstreg2 = translate_rreg (SD_, RN2);
6165 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6166 State.regs[dstreg2] -= EXTEND4 (IMM4);
6169 // 1111 0111 0100 0110 imm4 Rn1 Rm2 Rn2; sub_cmp imm4, Rn1, Rm2, Rn2
6170 8.0xf7+8.0x46+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_cmp
6174 int srcreg2, dstreg1, dstreg2;
6177 srcreg2 = translate_rreg (SD_, RM2);
6178 dstreg1 = translate_rreg (SD_, RN1);
6179 dstreg2 = translate_rreg (SD_, RN2);
6181 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6182 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
6185 // 1111 0111 0101 0110 imm4 Rn1 imm4 Rn2; sub_cmp imm4, Rn1, imm4, Rn2
6186 8.0xf7+8.0x56+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_cmp
6190 int dstreg1, dstreg2;
6193 dstreg1 = translate_rreg (SD_, RN1);
6194 dstreg2 = translate_rreg (SD_, RN2);
6196 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6197 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
6200 // 1111 0111 0110 0110 imm4 Rn1 Rm2 Rn2; sub_mov imm4, Rn1, Rm2, Rn2
6201 8.0xf7+8.0x66+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_mov
6205 int srcreg2, dstreg1, dstreg2;
6208 srcreg2 = translate_rreg (SD_, RM2);
6209 dstreg1 = translate_rreg (SD_, RN1);
6210 dstreg2 = translate_rreg (SD_, RN2);
6212 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6213 State.regs[dstreg2] = State.regs[srcreg2];
6216 // 1111 0111 0111 0110 imm4 Rn1 imm4 Rn2; sub_mov imm4, Rn1, imm4, Rn2
6217 8.0xf7+8.0x76+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_mov
6221 int dstreg1, dstreg2;
6224 dstreg1 = translate_rreg (SD_, RN1);
6225 dstreg2 = translate_rreg (SD_, RN2);
6227 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6228 State.regs[dstreg2] = EXTEND4 (IMM4);
6231 // 1111 0111 1000 0110 imm4 Rn1 Rm2 Rn2; sub_asr imm4, Rn1, Rm2, Rn2
6232 8.0xf7+8.0x86+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_asr
6236 int srcreg2, dstreg1, dstreg2;
6240 srcreg2 = translate_rreg (SD_, RM2);
6241 dstreg1 = translate_rreg (SD_, RN1);
6242 dstreg2 = translate_rreg (SD_, RN2);
6244 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6245 temp = State.regs[dstreg2];
6246 temp >>= State.regs[srcreg2];
6247 State.regs[dstreg2] = temp;
6250 // 1111 0111 1001 0110 imm4 Rn1 imm4 Rn2; sub_asr imm4, Rn1, imm4, Rn2
6251 8.0xf7+8.0x96+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_asr
6255 int dstreg1, dstreg2;
6259 dstreg1 = translate_rreg (SD_, RN1);
6260 dstreg2 = translate_rreg (SD_, RN2);
6262 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6263 temp = State.regs[dstreg2];
6265 State.regs[dstreg2] = temp;
6268 // 1111 0111 1010 0110 imm4 Rn1 Rm2 Rn2; sub_lsr imm4, Rn1, Rm2, Rn2
6269 8.0xf7+8.0xa6+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_lsr
6273 int srcreg2, dstreg1, dstreg2;
6276 srcreg2 = translate_rreg (SD_, RM2);
6277 dstreg1 = translate_rreg (SD_, RN1);
6278 dstreg2 = translate_rreg (SD_, RN2);
6280 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6281 State.regs[dstreg2] >>= State.regs[srcreg2];
6284 // 1111 0111 1011 0110 imm4 Rn1 imm4 Rn2; sub_lsr imm4, Rn1, imm4, Rn2
6285 8.0xf7+8.0xb6+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_lsr
6289 int dstreg1, dstreg2;
6293 dstreg1 = translate_rreg (SD_, RN1);
6294 dstreg2 = translate_rreg (SD_, RN2);
6296 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6297 State.regs[dstreg2] >>= IMM4;
6301 // 1111 0111 1100 0110 imm4 Rn1 Rm2 Rn2; sub_asl imm4, Rn1, Rm2, Rn2
6302 8.0xf7+8.0xc6+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_asl
6306 int srcreg2, dstreg1, dstreg2;
6309 srcreg2 = translate_rreg (SD_, RM2);
6310 dstreg1 = translate_rreg (SD_, RN1);
6311 dstreg2 = translate_rreg (SD_, RN2);
6313 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6314 State.regs[dstreg2] <<= State.regs[srcreg2];
6317 // 1111 0111 1101 0110 imm4 Rn1 imm4 Rn2; sub_asl imm4, Rn1, imm4, Rn2
6318 8.0xf7+8.0xd6+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_asl
6322 int dstreg1, dstreg2;
6326 dstreg1 = translate_rreg (SD_, RN1);
6327 dstreg2 = translate_rreg (SD_, RN2);
6329 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6330 State.regs[dstreg2] <<= IMM4;
6333 // 1111 0111 0000 0111 imm4 Rn1 Rm2 Rn2; mov_add imm4, Rn1, Rm2, Rn2
6334 8.0xf7+8.0x07+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_add
6338 int srcreg2, dstreg1, dstreg2;
6341 srcreg2 = translate_rreg (SD_, RM2);
6342 dstreg1 = translate_rreg (SD_, RN1);
6343 dstreg2 = translate_rreg (SD_, RN2);
6345 State.regs[dstreg1] = EXTEND4 (IMM4A);
6346 State.regs[dstreg2] += State.regs[srcreg2];
6349 // 1111 0111 0001 0111 imm4 Rn1 imm4 Rn2; mov_add imm4, Rn1, imm4, Rn2
6350 8.0xf7+8.0x17+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_add
6354 int dstreg1, dstreg2;
6357 dstreg1 = translate_rreg (SD_, RN1);
6358 dstreg2 = translate_rreg (SD_, RN2);
6360 State.regs[dstreg1] = EXTEND4 (IMM4A);
6361 State.regs[dstreg2] += EXTEND4 (IMM4);
6364 // 1111 0111 0010 0111 imm4 Rn1 Rm2 Rn2; mov_sub imm4, Rn1, Rm2, Rn2
6365 8.0xf7+8.0x27+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_sub
6369 int srcreg2, dstreg1, dstreg2;
6372 srcreg2 = translate_rreg (SD_, RM2);
6373 dstreg1 = translate_rreg (SD_, RN1);
6374 dstreg2 = translate_rreg (SD_, RN2);
6376 State.regs[dstreg1] = EXTEND4 (IMM4A);
6377 State.regs[dstreg2] -= State.regs[srcreg2];
6380 // 1111 0111 0011 0111 imm4 Rn1 imm4 Rn2; mov_sub imm4, Rn1, imm4, Rn2
6381 8.0xf7+8.0x37+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_sub
6385 int dstreg1, dstreg2;
6388 dstreg1 = translate_rreg (SD_, RN1);
6389 dstreg2 = translate_rreg (SD_, RN2);
6391 State.regs[dstreg1] = EXTEND4 (IMM4A);
6392 State.regs[dstreg2] -= EXTEND4 (IMM4);
6395 // 1111 0111 0100 0111 imm4 Rn1 Rm2 Rn2; mov_cmp imm4, Rn1, Rm2, Rn2
6396 8.0xf7+8.0x47+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_cmp
6400 int srcreg2, dstreg1, dstreg2;
6403 srcreg2 = translate_rreg (SD_, RM2);
6404 dstreg1 = translate_rreg (SD_, RN1);
6405 dstreg2 = translate_rreg (SD_, RN2);
6407 State.regs[dstreg1] = EXTEND4 (IMM4A);
6408 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
6411 // 1111 0111 0101 0111 imm4 Rn1 imm4 Rn2; mov_cmp imm4, Rn1, imm4, Rn2
6412 8.0xf7+8.0x57+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_cmp
6416 int dstreg1, dstreg2;
6419 dstreg1 = translate_rreg (SD_, RN1);
6420 dstreg2 = translate_rreg (SD_, RN2);
6422 State.regs[dstreg1] = EXTEND4 (IMM4A);
6423 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
6426 // 1111 0111 0110 0111 imm4 Rn1 Rm2 Rn2; mov_mov imm4, Rn1, Rm2, Rn2
6427 8.0xf7+8.0x67+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_mov
6431 int srcreg2, dstreg1, dstreg2;
6434 srcreg2 = translate_rreg (SD_, RM2);
6435 dstreg1 = translate_rreg (SD_, RN1);
6436 dstreg2 = translate_rreg (SD_, RN2);
6438 State.regs[dstreg1] = EXTEND4 (IMM4A);
6439 State.regs[dstreg2] = State.regs[srcreg2];
6442 // 1111 0111 0111 0111 imm4 Rn1 imm4 Rn2; mov_mov imm4, Rn1, imm4, Rn2
6443 8.0xf7+8.0x77+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_mov
6447 int dstreg1, dstreg2;
6450 dstreg1 = translate_rreg (SD_, RN1);
6451 dstreg2 = translate_rreg (SD_, RN2);
6453 State.regs[dstreg1] = EXTEND4 (IMM4A);
6454 State.regs[dstreg2] = EXTEND4 (IMM4);
6457 // 1111 0111 1000 0111 imm4 Rn1 Rm2 Rn2; mov_asr imm4, Rn1, Rm2, Rn2
6458 8.0xf7+8.0x87+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_asr
6462 int srcreg2, dstreg1, dstreg2;
6466 srcreg2 = translate_rreg (SD_, RM2);
6467 dstreg1 = translate_rreg (SD_, RN1);
6468 dstreg2 = translate_rreg (SD_, RN2);
6470 State.regs[dstreg1] = EXTEND4 (IMM4A);
6471 temp = State.regs[dstreg2];
6472 temp >>= State.regs[srcreg2];
6473 State.regs[dstreg2] = temp;
6476 // 1111 0111 1001 0111 imm4 Rn1 imm4 Rn2; mov_asr imm4, Rn1, imm4, Rn2
6477 8.0xf7+8.0x97+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_asr
6481 int dstreg1, dstreg2;
6485 dstreg1 = translate_rreg (SD_, RN1);
6486 dstreg2 = translate_rreg (SD_, RN2);
6488 State.regs[dstreg1] = EXTEND4 (IMM4A);
6489 temp = State.regs[dstreg2];
6491 State.regs[dstreg2] = temp;
6494 // 1111 0111 1010 0111 imm4 Rn1 Rm2 Rn2; mov_lsr imm4, Rn1, Rm2, Rn2
6495 8.0xf7+8.0xa7+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_lsr
6499 int srcreg2, dstreg1, dstreg2;
6502 srcreg2 = translate_rreg (SD_, RM2);
6503 dstreg1 = translate_rreg (SD_, RN1);
6504 dstreg2 = translate_rreg (SD_, RN2);
6506 State.regs[dstreg1] = EXTEND4 (IMM4A);
6507 State.regs[dstreg2] >>= State.regs[srcreg2];
6510 // 1111 0111 1011 0111 imm4 Rn1 imm4 Rn2; mov_lsr imm4, Rn1, imm4, Rn2
6511 8.0xf7+8.0xb7+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_lsr
6515 int dstreg1, dstreg2;
6519 dstreg1 = translate_rreg (SD_, RN1);
6520 dstreg2 = translate_rreg (SD_, RN2);
6522 State.regs[dstreg1] = EXTEND4 (IMM4A);
6523 State.regs[dstreg2] >>= IMM4;
6527 // 1111 0111 1100 0111 imm4 Rn1 Rm2 Rn2; mov_asl imm4, Rn1, Rm2, Rn2
6528 8.0xf7+8.0xc7+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_asl
6532 int srcreg2, dstreg1, dstreg2;
6535 srcreg2 = translate_rreg (SD_, RM2);
6536 dstreg1 = translate_rreg (SD_, RN1);
6537 dstreg2 = translate_rreg (SD_, RN2);
6539 State.regs[dstreg1] = EXTEND4 (IMM4A);
6540 State.regs[dstreg2] <<= State.regs[srcreg2];
6543 // 1111 0111 1101 0111 imm4 Rn1 imm4 Rn2; mov_asl imm4, Rn1, imm4, Rn2
6544 8.0xf7+8.0xd7+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_asl
6548 int dstreg1, dstreg2;
6552 dstreg1 = translate_rreg (SD_, RN1);
6553 dstreg2 = translate_rreg (SD_, RN2);
6555 State.regs[dstreg1] = EXTEND4 (IMM4A);
6556 State.regs[dstreg2] <<= IMM4;
6559 // 1111 0111 0000 1000 Rm1 Rn1 Rm2 Rn2; and_add Rm1, Rn1, Rm2, Rn2
6560 8.0xf7+8.0x08+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_add
6564 int srcreg1, srcreg2, dstreg1, dstreg2;
6567 srcreg1 = translate_rreg (SD_, RM1);
6568 srcreg2 = translate_rreg (SD_, RM2);
6569 dstreg1 = translate_rreg (SD_, RN1);
6570 dstreg2 = translate_rreg (SD_, RN2);
6572 State.regs[dstreg1] &= State.regs[srcreg1];
6573 State.regs[dstreg2] += State.regs[srcreg2];
6576 // 1111 0111 0001 1000 Rm1 Rn1 imm4 Rn2; and_add Rm1, Rn1, imm4, Rn2
6577 8.0xf7+8.0x18+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_add
6581 int srcreg1, dstreg1, dstreg2;
6584 srcreg1 = translate_rreg (SD_, RM1);
6585 dstreg1 = translate_rreg (SD_, RN1);
6586 dstreg2 = translate_rreg (SD_, RN2);
6588 State.regs[dstreg1] &= State.regs[srcreg1];
6589 State.regs[dstreg2] += EXTEND4 (IMM4);
6592 // 1111 0111 0010 1000 Rm1 Rn1 Rm2 Rn2; and_sub Rm1, Rn1, Rm2, Rn2
6593 8.0xf7+8.0x28+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_sub
6597 int srcreg1, srcreg2, dstreg1, dstreg2;
6600 srcreg1 = translate_rreg (SD_, RM1);
6601 srcreg2 = translate_rreg (SD_, RM2);
6602 dstreg1 = translate_rreg (SD_, RN1);
6603 dstreg2 = translate_rreg (SD_, RN2);
6605 State.regs[dstreg1] &= State.regs[srcreg1];
6606 State.regs[dstreg2] -= State.regs[srcreg2];
6609 // 1111 0111 0011 1000 Rm1 Rn1 imm4 Rn2; and_sub Rm1, Rn1, imm4, Rn2
6610 8.0xf7+8.0x38+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_sub
6614 int srcreg1, dstreg1, dstreg2;
6617 srcreg1 = translate_rreg (SD_, RM1);
6618 dstreg1 = translate_rreg (SD_, RN1);
6619 dstreg2 = translate_rreg (SD_, RN2);
6621 State.regs[dstreg1] &= State.regs[srcreg1];
6622 State.regs[dstreg2] -= EXTEND4 (IMM4);
6625 // 1111 0111 0100 1000 Rm1 Rn1 Rm2 Rn2; and_cmp Rm1, Rn1, Rm2, Rn2
6626 8.0xf7+8.0x48+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_cmp
6630 int srcreg1, srcreg2, dstreg1, dstreg2;
6633 srcreg1 = translate_rreg (SD_, RM1);
6634 srcreg2 = translate_rreg (SD_, RM2);
6635 dstreg1 = translate_rreg (SD_, RN1);
6636 dstreg2 = translate_rreg (SD_, RN2);
6638 State.regs[dstreg1] &= State.regs[srcreg1];
6639 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
6642 // 1111 0111 0101 1000 Rm1 Rn1 imm4 Rn2; and_cmp Rm1, Rn1, imm4, Rn2
6643 8.0xf7+8.0x58+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_cmp
6647 int srcreg1, dstreg1, dstreg2;
6650 srcreg1 = translate_rreg (SD_, RM1);
6651 dstreg1 = translate_rreg (SD_, RN1);
6652 dstreg2 = translate_rreg (SD_, RN2);
6654 State.regs[dstreg1] &= State.regs[srcreg1];
6655 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
6658 // 1111 0111 0110 1000 Rm1 Rn1 Rm2 Rn2; and_mov Rm1, Rn1, Rm2, Rn2
6659 8.0xf7+8.0x68+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_mov
6663 int srcreg1, srcreg2, dstreg1, dstreg2;
6666 srcreg1 = translate_rreg (SD_, RM1);
6667 srcreg2 = translate_rreg (SD_, RM2);
6668 dstreg1 = translate_rreg (SD_, RN1);
6669 dstreg2 = translate_rreg (SD_, RN2);
6671 State.regs[dstreg1] &= State.regs[srcreg1];
6672 State.regs[dstreg2] = State.regs[srcreg2];
6675 // 1111 0111 0111 1000 Rm1 Rn1 imm4 Rn2; and_mov Rm1, Rn1, imm4, Rn2
6676 8.0xf7+8.0x78+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_mov
6680 int srcreg1, dstreg1, dstreg2;
6683 srcreg1 = translate_rreg (SD_, RM1);
6684 dstreg1 = translate_rreg (SD_, RN1);
6685 dstreg2 = translate_rreg (SD_, RN2);
6687 State.regs[dstreg1] &= State.regs[srcreg1];
6688 State.regs[dstreg2] = EXTEND4 (IMM4);
6691 // 1111 0111 1000 1000 Rm1 Rn1 Rm2 Rn2; and_asr Rm1, Rn1, Rm2, Rn2
6692 8.0xf7+8.0x88+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_asr
6696 int srcreg1, srcreg2, dstreg1, dstreg2;
6700 srcreg1 = translate_rreg (SD_, RM1);
6701 srcreg2 = translate_rreg (SD_, RM2);
6702 dstreg1 = translate_rreg (SD_, RN1);
6703 dstreg2 = translate_rreg (SD_, RN2);
6705 State.regs[dstreg1] &= State.regs[srcreg1];
6706 temp = State.regs[dstreg2];
6707 temp >>= State.regs[srcreg2];
6708 State.regs[dstreg2] = temp;
6711 // 1111 0111 1001 1000 Rm1 Rn1 imm4 Rn2; and_asr Rm1, Rn1, imm4, Rn2
6712 8.0xf7+8.0x98+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_asr
6716 int srcreg1, dstreg1, dstreg2;
6720 srcreg1 = translate_rreg (SD_, RM1);
6721 dstreg1 = translate_rreg (SD_, RN1);
6722 dstreg2 = translate_rreg (SD_, RN2);
6724 State.regs[dstreg1] &= State.regs[srcreg1];
6725 temp = State.regs[dstreg2];
6727 State.regs[dstreg2] = temp;
6730 // 1111 0111 1010 1000 Rm1 Rn1 Rm2 Rn2; and_lsr Rm1, Rn1, Rm2, Rn2
6731 8.0xf7+8.0xa8+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_lsr
6735 int srcreg1, srcreg2, dstreg1, dstreg2;
6738 srcreg1 = translate_rreg (SD_, RM1);
6739 srcreg2 = translate_rreg (SD_, RM2);
6740 dstreg1 = translate_rreg (SD_, RN1);
6741 dstreg2 = translate_rreg (SD_, RN2);
6743 State.regs[dstreg1] &= State.regs[srcreg1];
6744 State.regs[dstreg2] >>= State.regs[srcreg2];
6747 // 1111 0111 1011 1000 Rm1 Rn1 imm4 Rn2; and_lsr Rm1, Rn1, imm4, Rn2
6748 8.0xf7+8.0xb8+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_lsr
6752 int srcreg1, dstreg1, dstreg2;
6756 srcreg1 = translate_rreg (SD_, RM1);
6757 dstreg1 = translate_rreg (SD_, RN1);
6758 dstreg2 = translate_rreg (SD_, RN2);
6760 State.regs[dstreg1] &= State.regs[srcreg1];
6761 State.regs[dstreg2] >>= IMM4;
6765 // 1111 0111 1100 1000 Rm1 Rn1 Rm2 Rn2; and_asl Rm1, Rn1, Rm2, Rn2
6766 8.0xf7+8.0xc8+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_asl
6770 int srcreg1, srcreg2, dstreg1, dstreg2;
6773 srcreg1 = translate_rreg (SD_, RM1);
6774 srcreg2 = translate_rreg (SD_, RM2);
6775 dstreg1 = translate_rreg (SD_, RN1);
6776 dstreg2 = translate_rreg (SD_, RN2);
6778 State.regs[dstreg1] &= State.regs[srcreg1];
6779 State.regs[dstreg2] <<= State.regs[srcreg2];
6782 // 1111 0111 1101 1000 Rm1 Rn1 imm4 Rn2; and_asl Rm1, Rn1, imm4, Rn2
6783 8.0xf7+8.0xd8+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_asl
6787 int srcreg1, dstreg1, dstreg2;
6791 srcreg1 = translate_rreg (SD_, RM1);
6792 dstreg1 = translate_rreg (SD_, RN1);
6793 dstreg2 = translate_rreg (SD_, RN2);
6795 State.regs[dstreg1] &= State.regs[srcreg1];
6796 State.regs[dstreg2] <<= IMM4;
6799 // 1111 0111 0000 1001 Rm1 Rn1 Rm2 Rn2; dmach_add Rm1, Rn1, Rm2, Rn2
6800 8.0xf7+8.0x09+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_add
6804 int srcreg1, srcreg2, dstreg1, dstreg2;
6805 long temp, temp2, sum;
6808 srcreg1 = translate_rreg (SD_, RM1);
6809 srcreg2 = translate_rreg (SD_, RM2);
6810 dstreg1 = translate_rreg (SD_, RN1);
6811 dstreg2 = translate_rreg (SD_, RN2);
6813 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6814 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6815 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6816 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6817 sum = temp + temp2 + State.regs[REG_MCRL];
6819 State.regs[dstreg1] = sum;
6820 State.regs[dstreg2] += State.regs[srcreg2];
6823 // 1111 0111 0001 1001 Rm1 Rn1 imm4 Rn2; dmach_add Rm1, Rn1, imm4, Rn2
6824 8.0xf7+8.0x19+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_add
6828 int srcreg1, dstreg1, dstreg2;
6829 long temp, temp2, sum;
6832 srcreg1 = translate_rreg (SD_, RM1);
6833 dstreg1 = translate_rreg (SD_, RN1);
6834 dstreg2 = translate_rreg (SD_, RN2);
6836 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6837 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6838 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6839 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6840 sum = temp + temp2 + State.regs[REG_MCRL];
6842 State.regs[dstreg1] = sum;
6843 State.regs[dstreg2] += EXTEND4 (IMM4);
6846 // 1111 0111 0010 1001 Rm1 Rn1 Rm2 Rn2; dmach_sub Rm1, Rn1, Rm2, Rn2
6847 8.0xf7+8.0x29+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_sub
6851 int srcreg1, srcreg2, dstreg1, dstreg2;
6852 long temp, temp2, sum;
6855 srcreg1 = translate_rreg (SD_, RM1);
6856 srcreg2 = translate_rreg (SD_, RM2);
6857 dstreg1 = translate_rreg (SD_, RN1);
6858 dstreg2 = translate_rreg (SD_, RN2);
6860 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6861 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6862 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6863 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6864 sum = temp + temp2 + State.regs[REG_MCRL];
6866 State.regs[dstreg1] = sum;
6867 State.regs[dstreg2] -= State.regs[srcreg2];
6870 // 1111 0111 0011 1001 Rm1 Rn1 imm4 Rn2; dmach_sub Rm1, Rn1, imm4, Rn2
6871 8.0xf7+8.0x39+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_sub
6875 int srcreg1, dstreg1, dstreg2;
6876 long temp, temp2, sum;
6879 srcreg1 = translate_rreg (SD_, RM1);
6880 dstreg1 = translate_rreg (SD_, RN1);
6881 dstreg2 = translate_rreg (SD_, RN2);
6883 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6884 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6885 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6886 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6887 sum = temp + temp2 + State.regs[REG_MCRL];
6889 State.regs[dstreg1] = sum;
6890 State.regs[dstreg2] -= EXTEND4 (IMM4);
6893 // 1111 0111 0100 1001 Rm1 Rn1 Rm2 Rn2; dmach_cmp Rm1, Rn1, Rm2, Rn2
6894 8.0xf7+8.0x49+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_cmp
6898 int srcreg1, srcreg2, dstreg1, dstreg2;
6899 long temp, temp2, sum;
6902 srcreg1 = translate_rreg (SD_, RM1);
6903 srcreg2 = translate_rreg (SD_, RM2);
6904 dstreg1 = translate_rreg (SD_, RN1);
6905 dstreg2 = translate_rreg (SD_, RN2);
6907 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6908 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6909 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6910 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6911 sum = temp + temp2 + State.regs[REG_MCRL];
6913 State.regs[dstreg1] = sum;
6914 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
6917 // 1111 0111 0101 1001 Rm1 Rn1 imm4 Rn2; dmach_cmp Rm1, Rn1, imm4, Rn2
6918 8.0xf7+8.0x59+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_cmp
6922 int srcreg1, dstreg1, dstreg2;
6923 long temp, temp2, sum;
6926 srcreg1 = translate_rreg (SD_, RM1);
6927 dstreg1 = translate_rreg (SD_, RN1);
6928 dstreg2 = translate_rreg (SD_, RN2);
6930 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6931 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6932 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6933 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6934 sum = temp + temp2 + State.regs[REG_MCRL];
6936 State.regs[dstreg1] = sum;
6937 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
6940 // 1111 0111 0110 1001 Rm1 Rn1 Rm2 Rn2; dmach_mov Rm1, Rn1, Rm2, Rn2
6941 8.0xf7+8.0x69+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_mov
6945 int srcreg1, srcreg2, dstreg1, dstreg2;
6946 long temp, temp2, sum;
6949 srcreg1 = translate_rreg (SD_, RM1);
6950 srcreg2 = translate_rreg (SD_, RM2);
6951 dstreg1 = translate_rreg (SD_, RN1);
6952 dstreg2 = translate_rreg (SD_, RN2);
6954 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6955 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6956 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6957 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6958 sum = temp + temp2 + State.regs[REG_MCRL];
6960 State.regs[dstreg1] = sum;
6961 State.regs[dstreg2] = State.regs[srcreg2];
6964 // 1111 0111 0111 1001 Rm1 Rn1 imm4 Rn2; dmach_mov Rm1, Rn1, imm4, Rn2
6965 8.0xf7+8.0x79+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_mov
6969 int srcreg1, dstreg1, dstreg2;
6970 long temp, temp2, sum;
6973 srcreg1 = translate_rreg (SD_, RM1);
6974 dstreg1 = translate_rreg (SD_, RN1);
6975 dstreg2 = translate_rreg (SD_, RN2);
6977 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6978 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6979 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6980 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6981 sum = temp + temp2 + State.regs[REG_MCRL];
6983 State.regs[dstreg1] = sum;
6984 State.regs[dstreg2] = EXTEND4 (IMM4);
6987 // 1111 0111 1000 1001 Rm1 Rn1 Rm2 Rn2; dmach_asr Rm1, Rn1, Rm2, Rn2
6988 8.0xf7+8.0x89+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_asr
6992 int srcreg1, srcreg2, dstreg1, dstreg2;
6993 long temp, temp2, sum;
6996 srcreg1 = translate_rreg (SD_, RM1);
6997 srcreg2 = translate_rreg (SD_, RM2);
6998 dstreg1 = translate_rreg (SD_, RN1);
6999 dstreg2 = translate_rreg (SD_, RN2);
7001 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7002 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7003 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7004 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7005 sum = temp + temp2 + State.regs[REG_MCRL];
7007 State.regs[dstreg1] = sum;
7008 temp = State.regs[dstreg2];
7009 temp >>= State.regs[srcreg2];
7010 State.regs[dstreg2] = temp;
7013 // 1111 0111 1001 1001 Rm1 Rn1 imm4 Rn2; dmach_asr Rm1, Rn1, imm4, Rn2
7014 8.0xf7+8.0x99+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_asr
7018 int srcreg1, dstreg1, dstreg2;
7019 long temp, temp2, sum;
7022 srcreg1 = translate_rreg (SD_, RM1);
7023 dstreg1 = translate_rreg (SD_, RN1);
7024 dstreg2 = translate_rreg (SD_, RN2);
7026 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7027 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7028 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7029 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7030 sum = temp + temp2 + State.regs[REG_MCRL];
7032 State.regs[dstreg1] = sum;
7033 temp = State.regs[dstreg2];
7035 State.regs[dstreg2] = temp;
7038 // 1111 0111 1010 1001 Rm1 Rn1 Rm2 Rn2; dmach_lsr Rm1, Rn1, Rm2, Rn2
7039 8.0xf7+8.0xa9+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_lsr
7043 int srcreg1, srcreg2, dstreg1, dstreg2;
7044 long temp, temp2, sum;
7047 srcreg1 = translate_rreg (SD_, RM1);
7048 srcreg2 = translate_rreg (SD_, RM2);
7049 dstreg1 = translate_rreg (SD_, RN1);
7050 dstreg2 = translate_rreg (SD_, RN2);
7052 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7053 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7054 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7055 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7056 sum = temp + temp2 + State.regs[REG_MCRL];
7058 State.regs[dstreg1] = sum;
7059 State.regs[dstreg2] >>= State.regs[srcreg2];
7062 // 1111 0111 1011 1001 Rm1 Rn1 imm4 Rn2; dmach_lsr Rm1, Rn1, imm4, Rn2
7063 8.0xf7+8.0xb9+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_lsr
7067 int srcreg1, dstreg1, dstreg2;
7068 long temp, temp2, sum;
7071 srcreg1 = translate_rreg (SD_, RM1);
7072 dstreg1 = translate_rreg (SD_, RN1);
7073 dstreg2 = translate_rreg (SD_, RN2);
7075 State.regs[dstreg2] >>= IMM4;
7079 // 1111 0111 1100 1001 Rm1 Rn1 Rm2 Rn2; dmach_asl Rm1, Rn1, Rm2, Rn2
7080 8.0xf7+8.0xc9+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_asl
7084 int srcreg1, srcreg2, dstreg1, dstreg2;
7085 long temp, temp2, sum;
7088 srcreg1 = translate_rreg (SD_, RM1);
7089 srcreg2 = translate_rreg (SD_, RM2);
7090 dstreg1 = translate_rreg (SD_, RN1);
7091 dstreg2 = translate_rreg (SD_, RN2);
7093 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7094 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7095 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7096 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7097 sum = temp + temp2 + State.regs[REG_MCRL];
7099 State.regs[dstreg1] = sum;
7100 State.regs[dstreg2] <<= State.regs[srcreg2];
7103 // 1111 0111 1101 1001 Rm1 Rn1 imm4 Rn2; dmach_asl Rm1, Rn1, imm4, Rn2
7104 8.0xf7+8.0xd9+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_asl
7108 int srcreg1, dstreg1, dstreg2;
7109 long temp, temp2, sum;
7112 srcreg1 = translate_rreg (SD_, RM1);
7113 dstreg1 = translate_rreg (SD_, RN1);
7114 dstreg2 = translate_rreg (SD_, RN2);
7116 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7117 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7118 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7119 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7120 sum = temp + temp2 + State.regs[REG_MCRL];
7122 State.regs[dstreg1] = sum;
7123 State.regs[dstreg2] <<= IMM4;
7126 // 1111 0111 0000 1010 Rm1 Rn1 Rm2 Rn2; xor_add Rm1, Rn1, Rm2, Rn2
7127 8.0xf7+8.0x0a+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_add
7131 int srcreg1, srcreg2, dstreg1, dstreg2;
7134 srcreg1 = translate_rreg (SD_, RM1);
7135 srcreg2 = translate_rreg (SD_, RM2);
7136 dstreg1 = translate_rreg (SD_, RN1);
7137 dstreg2 = translate_rreg (SD_, RN2);
7139 State.regs[dstreg1] ^= State.regs[srcreg1];
7140 State.regs[dstreg2] += State.regs[srcreg2];
7143 // 1111 0111 0001 1010 Rm1 Rn1 imm4 Rn2; xor_add Rm1, Rn1, imm4, Rn2
7144 8.0xf7+8.0x1a+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_add
7148 int srcreg1, dstreg1, dstreg2;
7151 srcreg1 = translate_rreg (SD_, RM1);
7152 dstreg1 = translate_rreg (SD_, RN1);
7153 dstreg2 = translate_rreg (SD_, RN2);
7155 State.regs[dstreg1] ^= State.regs[srcreg1];
7156 State.regs[dstreg2] += EXTEND4 (IMM4);
7159 // 1111 0111 0010 1010 Rm1 Rn1 Rm2 Rn2; xor_sub Rm1, Rn1, Rm2, Rn2
7160 8.0xf7+8.0x2a+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_sub
7164 int srcreg1, srcreg2, dstreg1, dstreg2;
7167 srcreg1 = translate_rreg (SD_, RM1);
7168 srcreg2 = translate_rreg (SD_, RM2);
7169 dstreg1 = translate_rreg (SD_, RN1);
7170 dstreg2 = translate_rreg (SD_, RN2);
7172 State.regs[dstreg1] ^= State.regs[srcreg1];
7173 State.regs[dstreg2] -= State.regs[srcreg2];
7176 // 1111 0111 0011 1010 Rm1 Rn1 imm4 Rn2; xor_sub Rm1, Rn1, imm4, Rn2
7177 8.0xf7+8.0x3a+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_sub
7181 int srcreg1, dstreg1, dstreg2;
7184 srcreg1 = translate_rreg (SD_, RM1);
7185 dstreg1 = translate_rreg (SD_, RN1);
7186 dstreg2 = translate_rreg (SD_, RN2);
7188 State.regs[dstreg1] ^= State.regs[srcreg1];
7189 State.regs[dstreg2] -= EXTEND4 (IMM4);
7192 // 1111 0111 0100 1010 Rm1 Rn1 Rm2 Rn2; xor_cmp Rm1, Rn1, Rm2, Rn2
7193 8.0xf7+8.0x4a+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_cmp
7197 int srcreg1, srcreg2, dstreg1, dstreg2;
7200 srcreg1 = translate_rreg (SD_, RM1);
7201 srcreg2 = translate_rreg (SD_, RM2);
7202 dstreg1 = translate_rreg (SD_, RN1);
7203 dstreg2 = translate_rreg (SD_, RN2);
7205 State.regs[dstreg1] ^= State.regs[srcreg1];
7206 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
7209 // 1111 0111 0101 1010 Rm1 Rn1 imm4 Rn2; xor_cmp Rm1, Rn1, imm4, Rn2
7210 8.0xf7+8.0x5a+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_cmp
7214 int srcreg1, dstreg1, dstreg2;
7217 srcreg1 = translate_rreg (SD_, RM1);
7218 dstreg1 = translate_rreg (SD_, RN1);
7219 dstreg2 = translate_rreg (SD_, RN2);
7221 State.regs[dstreg1] ^= State.regs[srcreg1];
7222 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
7225 // 1111 0111 0110 1010 Rm1 Rn1 Rm2 Rn2; xor_mov Rm1, Rn1, Rm2, Rn2
7226 8.0xf7+8.0x6a+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_mov
7230 int srcreg1, srcreg2, dstreg1, dstreg2;
7233 srcreg1 = translate_rreg (SD_, RM1);
7234 srcreg2 = translate_rreg (SD_, RM2);
7235 dstreg1 = translate_rreg (SD_, RN1);
7236 dstreg2 = translate_rreg (SD_, RN2);
7238 State.regs[dstreg1] ^= State.regs[srcreg1];
7239 State.regs[dstreg2] = State.regs[srcreg2];
7242 // 1111 0111 0111 1010 Rm1 Rn1 imm4 Rn2; xor_mov Rm1, Rn1, imm4, Rn2
7243 8.0xf7+8.0x7a+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_mov
7247 int srcreg1, dstreg1, dstreg2;
7250 srcreg1 = translate_rreg (SD_, RM1);
7251 dstreg1 = translate_rreg (SD_, RN1);
7252 dstreg2 = translate_rreg (SD_, RN2);
7254 State.regs[dstreg1] ^= State.regs[srcreg1];
7255 State.regs[dstreg2] = EXTEND4 (IMM4);
7258 // 1111 0111 1000 1010 Rm1 Rn1 Rm2 Rn2; xor_asr Rm1, Rn1, Rm2, Rn2
7259 8.0xf7+8.0x8a+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_asr
7263 int srcreg1, srcreg2, dstreg1, dstreg2;
7267 srcreg1 = translate_rreg (SD_, RM1);
7268 srcreg2 = translate_rreg (SD_, RM2);
7269 dstreg1 = translate_rreg (SD_, RN1);
7270 dstreg2 = translate_rreg (SD_, RN2);
7272 State.regs[dstreg1] ^= State.regs[srcreg1];
7273 temp = State.regs[dstreg2];
7274 temp >>= State.regs[srcreg2];
7275 State.regs[dstreg2] = temp;
7278 // 1111 0111 1001 1010 Rm1 Rn1 imm4 Rn2; xor_asr Rm1, Rn1, imm4, Rn2
7279 8.0xf7+8.0x9a+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_asr
7283 int srcreg1, dstreg1, dstreg2;
7287 srcreg1 = translate_rreg (SD_, RM1);
7288 dstreg1 = translate_rreg (SD_, RN1);
7289 dstreg2 = translate_rreg (SD_, RN2);
7291 State.regs[dstreg1] ^= State.regs[srcreg1];
7292 temp = State.regs[dstreg2];
7294 State.regs[dstreg2] = temp;
7297 // 1111 0111 1010 1010 Rm1 Rn1 Rm2 Rn2; xor_lsr Rm1, Rn1, Rm2, Rn2
7298 8.0xf7+8.0xaa+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_lsr
7302 int srcreg1, srcreg2, dstreg1, dstreg2;
7305 srcreg1 = translate_rreg (SD_, RM1);
7306 srcreg2 = translate_rreg (SD_, RM2);
7307 dstreg1 = translate_rreg (SD_, RN1);
7308 dstreg2 = translate_rreg (SD_, RN2);
7310 State.regs[dstreg1] ^= State.regs[srcreg1];
7311 State.regs[dstreg2] >>= State.regs[srcreg2];
7314 // 1111 0111 1011 1010 Rm1 Rn1 imm4 Rn2; xor_lsr Rm1, Rn1, imm4, Rn2
7315 8.0xf7+8.0xba+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_lsr
7319 int srcreg1, dstreg1, dstreg2;
7323 srcreg1 = translate_rreg (SD_, RM1);
7324 dstreg1 = translate_rreg (SD_, RN1);
7325 dstreg2 = translate_rreg (SD_, RN2);
7327 State.regs[dstreg1] ^= State.regs[srcreg1];
7328 State.regs[dstreg2] >>= IMM4;
7332 // 1111 0111 1100 1010 Rm1 Rn1 Rm2 Rn2; xor_asl Rm1, Rn1, Rm2, Rn2
7333 8.0xf7+8.0xca+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_asl
7337 int srcreg1, srcreg2, dstreg1, dstreg2;
7340 srcreg1 = translate_rreg (SD_, RM1);
7341 srcreg2 = translate_rreg (SD_, RM2);
7342 dstreg1 = translate_rreg (SD_, RN1);
7343 dstreg2 = translate_rreg (SD_, RN2);
7345 State.regs[dstreg1] ^= State.regs[srcreg1];
7346 State.regs[dstreg2] <<= State.regs[srcreg2];
7349 // 1111 0111 1101 1010 Rm1 Rn1 imm4 Rn2; xor_asl Rm1, Rn1, imm4, Rn2
7350 8.0xf7+8.0xda+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_asl
7354 int srcreg1, dstreg1, dstreg2;
7358 srcreg1 = translate_rreg (SD_, RM1);
7359 dstreg1 = translate_rreg (SD_, RN1);
7360 dstreg2 = translate_rreg (SD_, RN2);
7362 State.regs[dstreg1] ^= State.regs[srcreg1];
7363 State.regs[dstreg2] <<= IMM4;
7366 // 1111 0111 0000 1011 Rm1 Rn1 Rm2 Rn2; swhw_add Rm1, Rn1, Rm2, Rn2
7367 8.0xf7+8.0x0b+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_add
7371 int srcreg1, srcreg2, dstreg1, dstreg2;
7374 srcreg1 = translate_rreg (SD_, RM1);
7375 srcreg2 = translate_rreg (SD_, RM2);
7376 dstreg1 = translate_rreg (SD_, RN1);
7377 dstreg2 = translate_rreg (SD_, RN2);
7379 State.regs[dstreg1] ^= State.regs[srcreg1];
7380 State.regs[dstreg2] += State.regs[srcreg2];
7383 // 1111 0111 0001 1011 Rm1 Rn1 imm4 Rn2; swhw_add Rm1, Rn1, imm4, Rn2
7384 8.0xf7+8.0x1b+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_add
7388 int srcreg1, dstreg1, dstreg2;
7391 srcreg1 = translate_rreg (SD_, RM1);
7392 dstreg1 = translate_rreg (SD_, RN1);
7393 dstreg2 = translate_rreg (SD_, RN2);
7395 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7396 | ((State.regs[srcreg1] >> 16) & 0xffff));
7397 State.regs[dstreg2] += EXTEND4 (IMM4);
7400 // 1111 0111 0010 1011 Rm1 Rn1 Rm2 Rn2; swhw_sub Rm1, Rn1, Rm2, Rn2
7401 8.0xf7+8.0x2b+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_sub
7405 int srcreg1, srcreg2, dstreg1, dstreg2;
7408 srcreg1 = translate_rreg (SD_, RM1);
7409 srcreg2 = translate_rreg (SD_, RM2);
7410 dstreg1 = translate_rreg (SD_, RN1);
7411 dstreg2 = translate_rreg (SD_, RN2);
7413 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7414 | ((State.regs[srcreg1] >> 16) & 0xffff));
7415 State.regs[dstreg2] -= State.regs[srcreg2];
7418 // 1111 0111 0011 1011 Rm1 Rn1 imm4 Rn2; swhw_sub Rm1, Rn1, imm4, Rn2
7419 8.0xf7+8.0x3b+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_sub
7423 int srcreg1, dstreg1, dstreg2;
7426 srcreg1 = translate_rreg (SD_, RM1);
7427 dstreg1 = translate_rreg (SD_, RN1);
7428 dstreg2 = translate_rreg (SD_, RN2);
7430 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7431 | ((State.regs[srcreg1] >> 16) & 0xffff));
7432 State.regs[dstreg2] -= EXTEND4 (IMM4);
7435 // 1111 0111 0100 1011 Rm1 Rn1 Rm2 Rn2; swhw_cmp Rm1, Rn1, Rm2, Rn2
7436 8.0xf7+8.0x4b+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_cmp
7440 int srcreg1, srcreg2, dstreg1, dstreg2;
7443 srcreg1 = translate_rreg (SD_, RM1);
7444 srcreg2 = translate_rreg (SD_, RM2);
7445 dstreg1 = translate_rreg (SD_, RN1);
7446 dstreg2 = translate_rreg (SD_, RN2);
7448 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7449 | ((State.regs[srcreg1] >> 16) & 0xffff));
7450 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
7453 // 1111 0111 0101 1011 Rm1 Rn1 imm4 Rn2; swhw_cmp Rm1, Rn1, imm4, Rn2
7454 8.0xf7+8.0x5b+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_cmp
7458 int srcreg1, dstreg1, dstreg2;
7461 srcreg1 = translate_rreg (SD_, RM1);
7462 dstreg1 = translate_rreg (SD_, RN1);
7463 dstreg2 = translate_rreg (SD_, RN2);
7465 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7466 | ((State.regs[srcreg1] >> 16) & 0xffff));
7467 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
7470 // 1111 0111 0110 1011 Rm1 Rn1 Rm2 Rn2; swhw_mov Rm1, Rn1, Rm2, Rn2
7471 8.0xf7+8.0x6b+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_mov
7475 int srcreg1, srcreg2, dstreg1, dstreg2;
7478 srcreg1 = translate_rreg (SD_, RM1);
7479 srcreg2 = translate_rreg (SD_, RM2);
7480 dstreg1 = translate_rreg (SD_, RN1);
7481 dstreg2 = translate_rreg (SD_, RN2);
7483 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7484 | ((State.regs[srcreg1] >> 16) & 0xffff));
7485 State.regs[dstreg2] = State.regs[srcreg2];
7488 // 1111 0111 0111 1011 Rm1 Rn1 imm4 Rn2; swhw_mov Rm1, Rn1, imm4, Rn2
7489 8.0xf7+8.0x7b+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_mov
7493 int srcreg1, dstreg1, dstreg2;
7496 srcreg1 = translate_rreg (SD_, RM1);
7497 dstreg1 = translate_rreg (SD_, RN1);
7498 dstreg2 = translate_rreg (SD_, RN2);
7500 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7501 | ((State.regs[srcreg1] >> 16) & 0xffff));
7502 State.regs[dstreg2] = EXTEND4 (IMM4);
7505 // 1111 0111 1000 1011 Rm1 Rn1 Rm2 Rn2; swhw_asr Rm1, Rn1, Rm2, Rn2
7506 8.0xf7+8.0x8b+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_asr
7510 int srcreg1, srcreg2, dstreg1, dstreg2;
7514 srcreg1 = translate_rreg (SD_, RM1);
7515 srcreg2 = translate_rreg (SD_, RM2);
7516 dstreg1 = translate_rreg (SD_, RN1);
7517 dstreg2 = translate_rreg (SD_, RN2);
7519 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7520 | ((State.regs[srcreg1] >> 16) & 0xffff));
7521 temp = State.regs[dstreg2];
7522 temp >>= State.regs[srcreg2];
7523 State.regs[dstreg2] = temp;
7526 // 1111 0111 1001 1011 Rm1 Rn1 imm4 Rn2; swhw_asr Rm1, Rn1, imm4, Rn2
7527 8.0xf7+8.0x9b+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_asr
7531 int srcreg1, dstreg1, dstreg2;
7535 srcreg1 = translate_rreg (SD_, RM1);
7536 dstreg1 = translate_rreg (SD_, RN1);
7537 dstreg2 = translate_rreg (SD_, RN2);
7539 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7540 | ((State.regs[srcreg1] >> 16) & 0xffff));
7541 temp = State.regs[dstreg2];
7543 State.regs[dstreg2] = temp;
7546 // 1111 0111 1010 1011 Rm1 Rn1 Rm2 Rn2; swhw_lsr Rm1, Rn1, Rm2, Rn2
7547 8.0xf7+8.0xab+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_lsr
7551 int srcreg1, srcreg2, dstreg1, dstreg2;
7554 srcreg1 = translate_rreg (SD_, RM1);
7555 srcreg2 = translate_rreg (SD_, RM2);
7556 dstreg1 = translate_rreg (SD_, RN1);
7557 dstreg2 = translate_rreg (SD_, RN2);
7559 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7560 | ((State.regs[srcreg1] >> 16) & 0xffff));
7561 State.regs[dstreg2] >>= State.regs[srcreg2];
7564 // 1111 0111 1011 1011 Rm1 Rn1 imm4 Rn2; swhw_lsr Rm1, Rn1, imm4, Rn2
7565 8.0xf7+8.0xbb+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_lsr
7569 int srcreg1, dstreg1, dstreg2;
7573 srcreg1 = translate_rreg (SD_, RM1);
7574 dstreg1 = translate_rreg (SD_, RN1);
7575 dstreg2 = translate_rreg (SD_, RN2);
7577 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7578 | ((State.regs[srcreg1] >> 16) & 0xffff));
7579 State.regs[dstreg2] >>= IMM4;
7583 // 1111 0111 1100 1011 Rm1 Rn1 Rm2 Rn2; swhw_asl Rm1, Rn1, Rm2, Rn2
7584 8.0xf7+8.0xcb+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_asl
7588 int srcreg1, srcreg2, dstreg1, dstreg2;
7591 srcreg1 = translate_rreg (SD_, RM1);
7592 srcreg2 = translate_rreg (SD_, RM2);
7593 dstreg1 = translate_rreg (SD_, RN1);
7594 dstreg2 = translate_rreg (SD_, RN2);
7596 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7597 | ((State.regs[srcreg1] >> 16) & 0xffff));
7598 State.regs[dstreg2] <<= State.regs[srcreg2];
7601 // 1111 0111 1101 1011 Rm1 Rn1 imm4 Rn2; swhw_asl Rm1, Rn1, imm4, Rn2
7602 8.0xf7+8.0xdb+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_asl
7606 int srcreg1, dstreg1, dstreg2;
7610 srcreg1 = translate_rreg (SD_, RM1);
7611 dstreg1 = translate_rreg (SD_, RN1);
7612 dstreg2 = translate_rreg (SD_, RN2);
7614 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7615 | ((State.regs[srcreg1] >> 16) & 0xffff));
7616 State.regs[dstreg2] <<= IMM4;
7619 // 1111 0111 0000 1100 Rm1 Rn1 Rm2 Rn2; or_add Rm1, Rn1, Rm2, Rn2
7620 8.0xf7+8.0x0c+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_add
7624 int srcreg1, srcreg2, dstreg1, dstreg2;
7627 srcreg1 = translate_rreg (SD_, RM1);
7628 srcreg2 = translate_rreg (SD_, RM2);
7629 dstreg1 = translate_rreg (SD_, RN1);
7630 dstreg2 = translate_rreg (SD_, RN2);
7632 State.regs[dstreg1] |= State.regs[srcreg1];
7633 State.regs[dstreg2] += State.regs[srcreg2];
7636 // 1111 0111 0001 1100 Rm1 Rn1 imm4 Rn2; or_add Rm1, Rn1, imm4, Rn2
7637 8.0xf7+8.0x1c+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_add
7641 int srcreg1, dstreg1, dstreg2;
7644 srcreg1 = translate_rreg (SD_, RM1);
7645 dstreg1 = translate_rreg (SD_, RN1);
7646 dstreg2 = translate_rreg (SD_, RN2);
7648 State.regs[dstreg1] |= State.regs[srcreg1];
7649 State.regs[dstreg2] += EXTEND4 (IMM4);
7652 // 1111 0111 0010 1100 Rm1 Rn1 Rm2 Rn2; or_sub Rm1, Rn1, Rm2, Rn2
7653 8.0xf7+8.0x2c+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_sub
7657 int srcreg1, srcreg2, dstreg1, dstreg2;
7660 srcreg1 = translate_rreg (SD_, RM1);
7661 srcreg2 = translate_rreg (SD_, RM2);
7662 dstreg1 = translate_rreg (SD_, RN1);
7663 dstreg2 = translate_rreg (SD_, RN2);
7665 State.regs[dstreg1] |= State.regs[srcreg1];
7666 State.regs[dstreg2] -= State.regs[srcreg2];
7669 // 1111 0111 0011 1100 Rm1 Rn1 imm4 Rn2; or_sub Rm1, Rn1, imm4, Rn2
7670 8.0xf7+8.0x3c+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_sub
7674 int srcreg1, dstreg1, dstreg2;
7677 srcreg1 = translate_rreg (SD_, RM1);
7678 dstreg1 = translate_rreg (SD_, RN1);
7679 dstreg2 = translate_rreg (SD_, RN2);
7681 State.regs[dstreg1] |= State.regs[srcreg1];
7682 State.regs[dstreg2] -= EXTEND4 (IMM4);
7685 // 1111 0111 0100 1100 Rm1 Rn1 Rm2 Rn2; or_cmp Rm1, Rn1, Rm2, Rn2
7686 8.0xf7+8.0x4c+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_cmp
7690 int srcreg1, srcreg2, dstreg1, dstreg2;
7693 srcreg1 = translate_rreg (SD_, RM1);
7694 srcreg2 = translate_rreg (SD_, RM2);
7695 dstreg1 = translate_rreg (SD_, RN1);
7696 dstreg2 = translate_rreg (SD_, RN2);
7698 State.regs[dstreg1] |= State.regs[srcreg1];
7699 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
7702 // 1111 0111 0101 1100 Rm1 Rn1 imm4 Rn2; or_cmp Rm1, Rn1, imm4, Rn2
7703 8.0xf7+8.0x5c+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_cmp
7707 int srcreg1, dstreg1, dstreg2;
7710 srcreg1 = translate_rreg (SD_, RM1);
7711 dstreg1 = translate_rreg (SD_, RN1);
7712 dstreg2 = translate_rreg (SD_, RN2);
7714 State.regs[dstreg1] |= State.regs[srcreg1];
7715 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
7718 // 1111 0111 0110 1100 Rm1 Rn1 Rm2 Rn2; or_mov Rm1, Rn1, Rm2, Rn2
7719 8.0xf7+8.0x6c+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_mov
7723 int srcreg1, srcreg2, dstreg1, dstreg2;
7726 srcreg1 = translate_rreg (SD_, RM1);
7727 srcreg2 = translate_rreg (SD_, RM2);
7728 dstreg1 = translate_rreg (SD_, RN1);
7729 dstreg2 = translate_rreg (SD_, RN2);
7731 State.regs[dstreg1] |= State.regs[srcreg1];
7732 State.regs[dstreg2] = State.regs[srcreg2];
7735 // 1111 0111 0111 1100 Rm1 Rn1 imm4 Rn2; or_mov Rm1, Rn1, imm4, Rn2
7736 8.0xf7+8.0x7c+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_mov
7740 int srcreg1, dstreg1, dstreg2;
7743 srcreg1 = translate_rreg (SD_, RM1);
7744 dstreg1 = translate_rreg (SD_, RN1);
7745 dstreg2 = translate_rreg (SD_, RN2);
7747 State.regs[dstreg1] |= State.regs[srcreg1];
7748 State.regs[dstreg2] = EXTEND4 (IMM4);
7751 // 1111 0111 1000 1100 Rm1 Rn1 Rm2 Rn2; or_asr Rm1, Rn1, Rm2, Rn2
7752 8.0xf7+8.0x8c+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_asr
7756 int srcreg1, srcreg2, dstreg1, dstreg2;
7760 srcreg1 = translate_rreg (SD_, RM1);
7761 srcreg2 = translate_rreg (SD_, RM2);
7762 dstreg1 = translate_rreg (SD_, RN1);
7763 dstreg2 = translate_rreg (SD_, RN2);
7765 State.regs[dstreg1] |= State.regs[srcreg1];
7766 temp = State.regs[dstreg2];
7767 temp >>= State.regs[srcreg2];
7768 State.regs[dstreg2] = temp;
7771 // 1111 0111 1001 1100 Rm1 Rn1 imm4 Rn2; or_asr Rm1, Rn1, imm4, Rn2
7772 8.0xf7+8.0x9c+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_asr
7776 int srcreg1, dstreg1, dstreg2;
7780 srcreg1 = translate_rreg (SD_, RM1);
7781 dstreg1 = translate_rreg (SD_, RN1);
7782 dstreg2 = translate_rreg (SD_, RN2);
7784 State.regs[dstreg1] |= State.regs[srcreg1];
7785 temp = State.regs[dstreg2];
7787 State.regs[dstreg2] = temp;
7790 // 1111 0111 1010 1100 Rm1 Rn1 Rm2 Rn2; or_lsr Rm1, Rn1, Rm2, Rn2
7791 8.0xf7+8.0xac+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_lsr
7795 int srcreg1, srcreg2, dstreg1, dstreg2;
7798 srcreg1 = translate_rreg (SD_, RM1);
7799 srcreg2 = translate_rreg (SD_, RM2);
7800 dstreg1 = translate_rreg (SD_, RN1);
7801 dstreg2 = translate_rreg (SD_, RN2);
7803 State.regs[dstreg1] |= State.regs[srcreg1];
7804 State.regs[dstreg2] >>= State.regs[srcreg2];
7807 // 1111 0111 1011 1100 Rm1 Rn1 imm4 Rn2; or_lsr Rm1, Rn1, imm4, Rn2
7808 8.0xf7+8.0xbc+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_lsr
7812 int srcreg1, dstreg1, dstreg2;
7816 srcreg1 = translate_rreg (SD_, RM1);
7817 dstreg1 = translate_rreg (SD_, RN1);
7818 dstreg2 = translate_rreg (SD_, RN2);
7820 State.regs[dstreg1] |= State.regs[srcreg1];
7821 State.regs[dstreg2] >>= IMM4;
7825 // 1111 0111 1100 1100 Rm1 Rn1 Rm2 Rn2; or_asl Rm1, Rn1, Rm2, Rn2
7826 8.0xf7+8.0xcc+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_asl
7830 int srcreg1, srcreg2, dstreg1, dstreg2;
7833 srcreg1 = translate_rreg (SD_, RM1);
7834 srcreg2 = translate_rreg (SD_, RM2);
7835 dstreg1 = translate_rreg (SD_, RN1);
7836 dstreg2 = translate_rreg (SD_, RN2);
7838 State.regs[dstreg1] |= State.regs[srcreg1];
7839 State.regs[dstreg2] <<= State.regs[srcreg2];
7842 // 1111 0111 1101 1100 Rm1 Rn1 imm4 Rn2; or_asl Rm1, Rn1, imm4, Rn2
7843 8.0xf7+8.0xdc+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_asl
7847 int srcreg1, dstreg1, dstreg2;
7851 srcreg1 = translate_rreg (SD_, RM1);
7852 dstreg1 = translate_rreg (SD_, RN1);
7853 dstreg2 = translate_rreg (SD_, RN2);
7855 State.regs[dstreg1] |= State.regs[srcreg1];
7856 State.regs[dstreg2] <<= IMM4;
7859 // 1111 0111 0000 1101 Rm1 Rn1 Rm2 Rn2; sat16_add Rm1, Rn1, Rm2, Rn2
7860 8.0xf7+8.0x0d+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_add
7864 int srcreg1, srcreg2, dstreg1, dstreg2;
7867 srcreg1 = translate_rreg (SD_, RM1);
7868 srcreg2 = translate_rreg (SD_, RM2);
7869 dstreg1 = translate_rreg (SD_, RN1);
7870 dstreg2 = translate_rreg (SD_, RN2);
7872 if (State.regs[srcreg1] >= 0x7fff)
7873 State.regs[dstreg1] = 0x7fff;
7874 else if (State.regs[srcreg1] <= 0xffff8000)
7875 State.regs[dstreg1] = 0xffff8000;
7877 State.regs[dstreg1] = State.regs[srcreg1];
7879 State.regs[dstreg2] += State.regs[srcreg2];
7882 // 1111 0111 0001 1101 Rm1 Rn1 imm4 Rn2; sat16_add Rm1, Rn1, imm4, Rn2
7883 8.0xf7+8.0x1d+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_add
7887 int srcreg1, dstreg1, dstreg2;
7890 srcreg1 = translate_rreg (SD_, RM1);
7891 dstreg1 = translate_rreg (SD_, RN1);
7892 dstreg2 = translate_rreg (SD_, RN2);
7894 if (State.regs[srcreg1] >= 0x7fff)
7895 State.regs[dstreg1] = 0x7fff;
7896 else if (State.regs[srcreg1] <= 0xffff8000)
7897 State.regs[dstreg1] = 0xffff8000;
7899 State.regs[dstreg1] = State.regs[srcreg1];
7901 State.regs[dstreg2] += EXTEND4 (IMM4);
7904 // 1111 0111 0010 1101 Rm1 Rn1 Rm2 Rn2; sat16_sub Rm1, Rn1, Rm2, Rn2
7905 8.0xf7+8.0x2d+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_sub
7909 int srcreg1, srcreg2, dstreg1, dstreg2;
7912 srcreg1 = translate_rreg (SD_, RM1);
7913 srcreg2 = translate_rreg (SD_, RM2);
7914 dstreg1 = translate_rreg (SD_, RN1);
7915 dstreg2 = translate_rreg (SD_, RN2);
7917 if (State.regs[srcreg1] >= 0x7fff)
7918 State.regs[dstreg1] = 0x7fff;
7919 else if (State.regs[srcreg1] <= 0xffff8000)
7920 State.regs[dstreg1] = 0xffff8000;
7922 State.regs[dstreg1] = State.regs[srcreg1];
7924 State.regs[dstreg2] -= State.regs[srcreg2];
7927 // 1111 0111 0011 1101 Rm1 Rn1 imm4 Rn2; sat16_sub Rm1, Rn1, imm4, Rn2
7928 8.0xf7+8.0x3d+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_sub
7932 int srcreg1, dstreg1, dstreg2;
7935 srcreg1 = translate_rreg (SD_, RM1);
7936 dstreg1 = translate_rreg (SD_, RN1);
7937 dstreg2 = translate_rreg (SD_, RN2);
7939 if (State.regs[srcreg1] >= 0x7fff)
7940 State.regs[dstreg1] = 0x7fff;
7941 else if (State.regs[srcreg1] <= 0xffff8000)
7942 State.regs[dstreg1] = 0xffff8000;
7944 State.regs[dstreg1] = State.regs[srcreg1];
7946 State.regs[dstreg2] -= EXTEND4 (IMM4);
7949 // 1111 0111 0100 1101 Rm1 Rn1 Rm2 Rn2; sat16_cmp Rm1, Rn1, Rm2, Rn2
7950 8.0xf7+8.0x4d+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_cmp
7954 int srcreg1, srcreg2, dstreg1, dstreg2;
7957 srcreg1 = translate_rreg (SD_, RM1);
7958 srcreg2 = translate_rreg (SD_, RM2);
7959 dstreg1 = translate_rreg (SD_, RN1);
7960 dstreg2 = translate_rreg (SD_, RN2);
7962 if (State.regs[srcreg1] >= 0x7fff)
7963 State.regs[dstreg1] = 0x7fff;
7964 else if (State.regs[srcreg1] <= 0xffff8000)
7965 State.regs[dstreg1] = 0xffff8000;
7967 State.regs[dstreg1] = State.regs[srcreg1];
7969 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
7972 // 1111 0111 0101 1101 Rm1 Rn1 imm4 Rn2; sat16_cmp Rm1, Rn1, imm4, Rn2
7973 8.0xf7+8.0x5d+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_cmp
7977 int srcreg1, dstreg1, dstreg2;
7980 srcreg1 = translate_rreg (SD_, RM1);
7981 dstreg1 = translate_rreg (SD_, RN1);
7982 dstreg2 = translate_rreg (SD_, RN2);
7984 if (State.regs[srcreg1] >= 0x7fff)
7985 State.regs[dstreg1] = 0x7fff;
7986 else if (State.regs[srcreg1] <= 0xffff8000)
7987 State.regs[dstreg1] = 0xffff8000;
7989 State.regs[dstreg1] = State.regs[srcreg1];
7991 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
7994 // 1111 0111 0110 1101 Rm1 Rn1 Rm2 Rn2; sat16_mov Rm1, Rn1, Rm2, Rn2
7995 8.0xf7+8.0x6d+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_mov
7999 int srcreg1, srcreg2, dstreg1, dstreg2;
8002 srcreg1 = translate_rreg (SD_, RM1);
8003 srcreg2 = translate_rreg (SD_, RM2);
8004 dstreg1 = translate_rreg (SD_, RN1);
8005 dstreg2 = translate_rreg (SD_, RN2);
8007 if (State.regs[srcreg1] >= 0x7fff)
8008 State.regs[dstreg1] = 0x7fff;
8009 else if (State.regs[srcreg1] <= 0xffff8000)
8010 State.regs[dstreg1] = 0xffff8000;
8012 State.regs[dstreg1] = State.regs[srcreg1];
8014 State.regs[dstreg2] = State.regs[srcreg2];
8017 // 1111 0111 0111 1101 Rm1 Rn1 imm4 Rn2; sat16_mov Rm1, Rn1, imm4, Rn2
8018 8.0xf7+8.0x7d+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_mov
8022 int srcreg1, dstreg1, dstreg2;
8025 srcreg1 = translate_rreg (SD_, RM1);
8026 dstreg1 = translate_rreg (SD_, RN1);
8027 dstreg2 = translate_rreg (SD_, RN2);
8029 if (State.regs[srcreg1] >= 0x7fff)
8030 State.regs[dstreg1] = 0x7fff;
8031 else if (State.regs[srcreg1] <= 0xffff8000)
8032 State.regs[dstreg1] = 0xffff8000;
8034 State.regs[dstreg1] = State.regs[srcreg1];
8036 State.regs[dstreg2] = EXTEND4 (IMM4);
8039 // 1111 0111 1000 1101 Rm1 Rn1 Rm2 Rn2; sat16_asr Rm1, Rn1, Rm2, Rn2
8040 8.0xf7+8.0x8d+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_asr
8044 int srcreg1, srcreg2, dstreg1, dstreg2;
8048 srcreg1 = translate_rreg (SD_, RM1);
8049 srcreg2 = translate_rreg (SD_, RM2);
8050 dstreg1 = translate_rreg (SD_, RN1);
8051 dstreg2 = translate_rreg (SD_, RN2);
8053 if (State.regs[srcreg1] >= 0x7fff)
8054 State.regs[dstreg1] = 0x7fff;
8055 else if (State.regs[srcreg1] <= 0xffff8000)
8056 State.regs[dstreg1] = 0xffff8000;
8058 State.regs[dstreg1] = State.regs[srcreg1];
8060 temp = State.regs[dstreg2];
8061 temp >>= State.regs[srcreg2];
8062 State.regs[dstreg2] = temp;
8065 // 1111 0111 1001 1101 Rm1 Rn1 imm4 Rn2; sat16_asr Rm1, Rn1, imm4, Rn2
8066 8.0xf7+8.0x9d+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_asr
8070 int srcreg1, dstreg1, dstreg2;
8074 srcreg1 = translate_rreg (SD_, RM1);
8075 dstreg1 = translate_rreg (SD_, RN1);
8076 dstreg2 = translate_rreg (SD_, RN2);
8078 if (State.regs[srcreg1] >= 0x7fff)
8079 State.regs[dstreg1] = 0x7fff;
8080 else if (State.regs[srcreg1] <= 0xffff8000)
8081 State.regs[dstreg1] = 0xffff8000;
8083 State.regs[dstreg1] = State.regs[srcreg1];
8085 temp = State.regs[dstreg2];
8087 State.regs[dstreg2] = temp;
8090 // 1111 0111 1010 1101 Rm1 Rn1 Rm2 Rn2; sat16_lsr Rm1, Rn1, Rm2, Rn2
8091 8.0xf7+8.0xad+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_lsr
8095 int srcreg1, srcreg2, dstreg1, dstreg2;
8098 srcreg1 = translate_rreg (SD_, RM1);
8099 srcreg2 = translate_rreg (SD_, RM2);
8100 dstreg1 = translate_rreg (SD_, RN1);
8101 dstreg2 = translate_rreg (SD_, RN2);
8103 if (State.regs[srcreg1] >= 0x7fff)
8104 State.regs[dstreg1] = 0x7fff;
8105 else if (State.regs[srcreg1] <= 0xffff8000)
8106 State.regs[dstreg1] = 0xffff8000;
8108 State.regs[dstreg1] = State.regs[srcreg1];
8110 State.regs[dstreg2] >>= State.regs[srcreg2];
8113 // 1111 0111 1011 1101 Rm1 Rn1 imm4 Rn2; sat16_lsr Rm1, Rn1, imm4, Rn2
8114 8.0xf7+8.0xbd+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_lsr
8118 int srcreg1, dstreg1, dstreg2;
8122 srcreg1 = translate_rreg (SD_, RM1);
8123 dstreg1 = translate_rreg (SD_, RN1);
8124 dstreg2 = translate_rreg (SD_, RN2);
8126 if (State.regs[srcreg1] >= 0x7fff)
8127 State.regs[dstreg1] = 0x7fff;
8128 else if (State.regs[srcreg1] <= 0xffff8000)
8129 State.regs[dstreg1] = 0xffff8000;
8131 State.regs[dstreg1] = State.regs[srcreg1];
8133 State.regs[dstreg2] >>= IMM4;
8137 // 1111 0111 1100 1101 Rm1 Rn1 Rm2 Rn2; sat16_asl Rm1, Rn1, Rm2, Rn2
8138 8.0xf7+8.0xcd+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_asl
8142 int srcreg1, srcreg2, dstreg1, dstreg2;
8145 srcreg1 = translate_rreg (SD_, RM1);
8146 srcreg2 = translate_rreg (SD_, RM2);
8147 dstreg1 = translate_rreg (SD_, RN1);
8148 dstreg2 = translate_rreg (SD_, RN2);
8150 if (State.regs[srcreg1] >= 0x7fff)
8151 State.regs[dstreg1] = 0x7fff;
8152 else if (State.regs[srcreg1] <= 0xffff8000)
8153 State.regs[dstreg1] = 0xffff8000;
8155 State.regs[dstreg1] = State.regs[srcreg1];
8157 State.regs[dstreg2] <<= State.regs[srcreg2];
8160 // 1111 0111 1101 1101 Rm1 Rn1 imm4 Rn2; sat16_asl Rm1, Rn1, imm4, Rn2
8161 8.0xf7+8.0xdd+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_asl
8165 int srcreg1, dstreg1, dstreg2;
8169 srcreg1 = translate_rreg (SD_, RM1);
8170 dstreg1 = translate_rreg (SD_, RN1);
8171 dstreg2 = translate_rreg (SD_, RN2);
8173 if (State.regs[srcreg1] >= 0x7fff)
8174 State.regs[dstreg1] = 0x7fff;
8175 else if (State.regs[srcreg1] <= 0xffff8000)
8176 State.regs[dstreg1] = 0xffff8000;
8178 State.regs[dstreg1] = State.regs[srcreg1];
8180 State.regs[dstreg2] <<= IMM4;
8183 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0000; mov_llt (Rm+,imm4),Rn
8184 8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x0:D2:::mov_llt
8191 srcreg = translate_rreg (SD_, RM);
8192 dstreg = translate_rreg (SD_, RN);
8194 State.regs[dstreg] = load_word (State.regs[srcreg]);
8195 State.regs[srcreg] += EXTEND4 (IMM4);
8197 if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))
8199 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8204 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0001; mov_lgt (Rm+,imm4),Rn
8205 8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x1:D2:::mov_lgt
8212 srcreg = translate_rreg (SD_, RM);
8213 dstreg = translate_rreg (SD_, RN);
8215 State.regs[dstreg] = load_word (State.regs[srcreg]);
8216 State.regs[srcreg] += EXTEND4 (IMM4);
8219 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))))
8221 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8226 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0010; mov_lge (Rm+,imm4),Rn
8227 8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x2:D2:::mov_lge
8234 srcreg = translate_rreg (SD_, RM);
8235 dstreg = translate_rreg (SD_, RN);
8237 State.regs[dstreg] = load_word (State.regs[srcreg]);
8238 State.regs[srcreg] += EXTEND4 (IMM4);
8240 if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
8242 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8247 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0011; mov_lle (Rm+,imm4),Rn
8248 8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x3:D2:::mov_lle
8255 srcreg = translate_rreg (SD_, RM);
8256 dstreg = translate_rreg (SD_, RN);
8258 State.regs[dstreg] = load_word (State.regs[srcreg]);
8259 State.regs[srcreg] += EXTEND4 (IMM4);
8262 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
8264 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8269 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0100; mov_lcs (Rm+,imm4),Rn
8270 8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x4:D2:::mov_lcs
8277 srcreg = translate_rreg (SD_, RM);
8278 dstreg = translate_rreg (SD_, RN);
8280 State.regs[dstreg] = load_word (State.regs[srcreg]);
8281 State.regs[srcreg] += EXTEND4 (IMM4);
8285 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8290 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0101; mov_lhi (Rm+,imm4),Rn
8291 8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x5:D2:::mov_lhi
8298 srcreg = translate_rreg (SD_, RM);
8299 dstreg = translate_rreg (SD_, RN);
8301 State.regs[dstreg] = load_word (State.regs[srcreg]);
8302 State.regs[srcreg] += EXTEND4 (IMM4);
8304 if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
8306 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8311 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0110; mov_lcc (Rm+,imm4),Rn
8312 8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x6:D2:::mov_lcc
8319 srcreg = translate_rreg (SD_, RM);
8320 dstreg = translate_rreg (SD_, RN);
8322 State.regs[dstreg] = load_word (State.regs[srcreg]);
8323 State.regs[srcreg] += EXTEND4 (IMM4);
8327 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8332 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0111; mov_lls (Rm+,imm4),Rn
8333 8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x7:D2:::mov_lls
8340 srcreg = translate_rreg (SD_, RM);
8341 dstreg = translate_rreg (SD_, RN);
8343 State.regs[dstreg] = load_word (State.regs[srcreg]);
8344 State.regs[srcreg] += EXTEND4 (IMM4);
8346 if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
8348 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8353 // 1111 0111 1110 0000 Rm1 Rn1 imm4 1000; mov_leq (Rm+,imm4),Rn
8354 8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x8:D2:::mov_leq
8361 srcreg = translate_rreg (SD_, RM);
8362 dstreg = translate_rreg (SD_, RN);
8364 State.regs[dstreg] = load_word (State.regs[srcreg]);
8365 State.regs[srcreg] += EXTEND4 (IMM4);
8369 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8374 // 1111 0111 1110 0000 Rm1 Rn1 imm4 1001; mov_lne (Rm+,imm4),Rn
8375 8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x9:D2:::mov_lne
8382 srcreg = translate_rreg (SD_, RM);
8383 dstreg = translate_rreg (SD_, RN);
8385 State.regs[dstreg] = load_word (State.regs[srcreg]);
8386 State.regs[srcreg] += EXTEND4 (IMM4);
8390 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8395 // 1111 0111 1110 0000 Rm1 Rn1 imm4 1010; mov_lra (Rm+,imm4),Rn
8396 8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0xa:D2:::mov_lra
8403 srcreg = translate_rreg (SD_, RM);
8404 dstreg = translate_rreg (SD_, RN);
8406 State.regs[dstreg] = load_word (State.regs[srcreg]);
8407 State.regs[srcreg] += EXTEND4 (IMM4);
8409 State.regs[REG_PC] = State.regs[REG_LAR] - 4;