3 // Given an extended register number, translate it into an index into the
4 // register array. This is necessary as the upper 8 extended registers are
5 // actually synonyms for the d0-d3/a0-a3 registers.
9 :function:::int:translate_rreg:int rreg
12 /* The higher register numbers actually correspond to the
13 basic machine's address and data registers. */
14 if (rreg > 7 && rreg < 12)
15 return REG_A0 + rreg - 8;
16 else if (rreg > 11 && rreg < 16)
17 return REG_D0 + rreg - 12;
22 :function:::int:translate_xreg:int xreg
41 // 1111 0000 0010 00An; mov USP,An
42 8.0xf0+4.0x2,00,2.AN0:D0m:::mov
47 State.regs[REG_A0 + AN0] = State.regs[REG_USP];
51 // 1111 0000 0010 01An; mov SSP,An
52 8.0xf0+4.0x2,01,2.AN0:D0n:::mov
57 State.regs[REG_A0 + AN0] = State.regs[REG_SSP];
61 // 1111 0000 0010 10An; mov MSP,An
62 8.0xf0+4.0x2,10,2.AN0:D0o:::mov
67 State.regs[REG_A0 + AN0] = State.regs[REG_MSP];
71 // 1111 0000 0010 11An; mov PC,An
72 8.0xf0+4.0x2,11,2.AN0:D0p:::mov
77 State.regs[REG_A0 + AN0] = PC;
81 // 1111 0000 0011 Am00; mov Am,USP
82 8.0xf0+4.0x3,2.AM1,00:D0q:::mov
87 State.regs[REG_USP] = State.regs[REG_A0 + AM1];
90 // 1111 0000 0011 Am01; mov Am,SSP
91 8.0xf0+4.0x3,2.AM1,01:D0r:::mov
96 State.regs[REG_SSP] = State.regs[REG_A0 + AM1];
99 // 1111 0000 0011 Am10; mov Am,MSP
100 8.0xf0+4.0x3,2.AM1,10:D0s:::mov
105 State.regs[REG_MSP] = State.regs[REG_A0 + AM1];
109 // 1111 0000 1110 imm4; syscall
110 8.0xf0+4.0xe,IMM4:D0t:::syscall
114 unsigned int sp, next_pc;
117 sp = State.regs[REG_SP];
118 next_pc = State.regs[REG_PC] + 2;
119 store_word (sp - 4, next_pc);
120 store_word (sp - 8, PSW);
121 State.regs[REG_PC] = 0x40000000 + IMM4 * 8;
126 // 1111 0010 1110 11Dn; mov EPSW,Dn
127 8.0xf2+4.0xe,11,2.DN0:D0u:::mov
132 State.regs[REG_D0 + DN0] = PSW;
136 // 1111 0010 1111 Dm01; mov Dm,EPSW
137 8.0xf2+4.0xf,2.DM1,01:D0v:::mov
142 PSW = State.regs[REG_D0 + DM1];
145 // 1111 0101 00Am Rn; mov Am,Rn
146 8.0xf5+00,2.AM1,4.RN0:D0w:::mov
150 int destreg = translate_rreg (SD_, RN0);
153 State.regs[destreg] = State.regs[REG_A0 + AM1];
156 // 1111 0101 01Dm Rn; mov Dm,Rn
157 8.0xf5+01,2.DM1,4.RN0:D0x:::mov
161 int destreg = translate_rreg (SD_, RN0);
164 State.regs[destreg] = State.regs[REG_D0 + DM1];
167 // 1111 0101 10Rm An; mov Rm,An
168 8.0xf5+10,4.RM1,2.AN0:D0y:::mov
172 int destreg = translate_rreg (SD_, RM1);
175 State.regs[REG_A0 + AN0] = State.regs[destreg];
178 // 1111 0101 11Rm Dn; mov Rm,Dn
179 8.0xf5+11,4.RM1,2.DN0:D0z:::mov
183 int destreg = translate_rreg (SD_, RM1);
186 State.regs[REG_D0 + DN0] = State.regs[destreg];
190 // 1111 1000 1100 1110 regs....; movm (USP),regs
191 8.0xf8+8.0xce+8.REGS:D1a:::movm
195 unsigned long usp = State.regs[REG_USP];
204 State.regs[REG_LAR] = load_word (usp);
206 State.regs[REG_LIR] = load_word (usp);
208 State.regs[REG_MDR] = load_word (usp);
210 State.regs[REG_A0 + 1] = load_word (usp);
212 State.regs[REG_A0] = load_word (usp);
214 State.regs[REG_D0 + 1] = load_word (usp);
216 State.regs[REG_D0] = load_word (usp);
222 State.regs[REG_A0 + 3] = load_word (usp);
228 State.regs[REG_A0 + 2] = load_word (usp);
234 State.regs[REG_D0 + 3] = load_word (usp);
240 State.regs[REG_D0 + 2] = load_word (usp);
244 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
248 /* Need to restore MDQR, MCRH, MCRL, and MCVF */
250 State.regs[REG_E0 + 1] = load_word (usp);
252 State.regs[REG_E0 + 0] = load_word (usp);
258 State.regs[REG_E0 + 7] = load_word (usp);
260 State.regs[REG_E0 + 6] = load_word (usp);
262 State.regs[REG_E0 + 5] = load_word (usp);
264 State.regs[REG_E0 + 4] = load_word (usp);
270 State.regs[REG_E0 + 3] = load_word (usp);
272 State.regs[REG_E0 + 2] = load_word (usp);
277 /* And make sure to update the stack pointer. */
278 State.regs[REG_USP] = usp;
281 // 1111 1000 1100 1111 regs....; movm (USP),regs
282 8.0xf8+8.0xcf+8.REGS:D1b:::movm
286 unsigned long usp = State.regs[REG_USP];
289 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
294 store_word (usp, State.regs[REG_E0 + 2]);
296 store_word (usp, State.regs[REG_E0 + 3]);
302 store_word (usp, State.regs[REG_E0 + 4]);
304 store_word (usp, State.regs[REG_E0 + 5]);
306 store_word (usp, State.regs[REG_E0 + 6]);
308 store_word (usp, State.regs[REG_E0 + 7]);
314 store_word (usp, State.regs[REG_E0 + 0]);
316 store_word (usp, State.regs[REG_E0 + 1]);
318 /* Need to save MDQR, MCRH, MCRL, and MCVF */
325 store_word (usp, State.regs[REG_D0 + 2]);
331 store_word (usp, State.regs[REG_D0 + 3]);
337 store_word (usp, State.regs[REG_A0 + 2]);
343 store_word (usp, State.regs[REG_A0 + 3]);
349 store_word (usp, State.regs[REG_D0]);
351 store_word (usp, State.regs[REG_D0 + 1]);
353 store_word (usp, State.regs[REG_A0]);
355 store_word (usp, State.regs[REG_A0 + 1]);
357 store_word (usp, State.regs[REG_MDR]);
359 store_word (usp, State.regs[REG_LIR]);
361 store_word (usp, State.regs[REG_LAR]);
365 /* And make sure to update the stack pointer. */
366 State.regs[REG_USP] = usp;
369 // 1111 1100 1111 1100 imm32...; and imm32,EPSW
370 8.0xfc+8.0xfc+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:4a:::and
375 PSW &= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
378 // 1111 1100 1111 1101 imm32...; or imm32,EPSW
379 8.0xfc+8.0xfd+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::or
384 PSW |= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
387 // 1111 1001 0000 1000 Rm Rn; mov Rm,Rn (Rm != Rn)
388 8.0xf9+8.0x08+4.RM2,4.RN0!RM2:D1g:::mov
396 srcreg = translate_rreg (SD_, RM2);
397 dstreg = translate_rreg (SD_, RN0);
398 State.regs[dstreg] = State.regs[srcreg];
401 // 1111 1001 0001 1000 Rn Rn; ext Rn
402 8.0xf9+8.0x18+4.RN0,4.RN2=RN0:D1:::ext
409 srcreg = translate_rreg (SD_, RN0);
410 if (State.regs[srcreg] & 0x80000000)
411 State.regs[REG_MDR] = -1;
413 State.regs[REG_MDR] = 0;
416 // 1111 1001 0010 1000 Rm Rn; extb Rm,Rn
417 8.0xf9+8.0x28+4.RM2,4.RN0!RM2:D1:::extb
424 srcreg = translate_rreg (SD_, RM2);
425 dstreg = translate_rreg (SD_, RN0);
426 State.regs[dstreg] = EXTEND8 (State.regs[srcreg]);
429 // 1111 1001 0011 1000 Rm Rn; extbu Rm,Rn
430 8.0xf9+8.0x38+4.RM2,4.RN0!RM2:D1:::extbu
437 srcreg = translate_rreg (SD_, RM2);
438 dstreg = translate_rreg (SD_, RN0);
439 State.regs[dstreg] = State.regs[srcreg] & 0xff;
442 // 1111 1001 0100 1000 Rm Rn; exth Rm,Rn
443 8.0xf9+8.0x48+4.RM2,4.RN0!RM2:D1:::exth
450 srcreg = translate_rreg (SD_, RM2);
451 dstreg = translate_rreg (SD_, RN0);
452 State.regs[dstreg] = EXTEND16 (State.regs[srcreg]);
455 // 1111 1001 0101 1000 Rm Rn; exthu Rm,Rn
456 8.0xf9+8.0x58+4.RM2,4.RN0!RM2:D1:::exthu
463 srcreg = translate_rreg (SD_, RM2);
464 dstreg = translate_rreg (SD_, RN0);
465 State.regs[dstreg] = State.regs[srcreg] & 0xffff;
468 // 1111 1001 0110 1000 Rn Rn; clr Rn
469 8.0xf9+8.0x68+4.RM2,4.RN0=RM2:D1:::clr
476 dstreg = translate_rreg (SD_, RN0);
477 State.regs[dstreg] = 0;
479 PSW &= ~(PSW_V | PSW_C | PSW_N);
482 // 1111 1001 0111 1000 Rm Rn; add Rm,Rn
483 8.0xf9+8.0x78+4.RM2,4.RN0:D1b:::add
490 srcreg = translate_rreg (SD_, RM2);
491 dstreg = translate_rreg (SD_, RN0);
492 genericAdd (State.regs[srcreg], dstreg);
495 // 1111 1001 1000 1000 Rm Rn; addc Rm,Rn
496 8.0xf9+8.0x88+4.RM2,4.RN0:D1b:::addc
502 unsigned long reg1, reg2, sum;
505 srcreg = translate_rreg (SD_, RM2);
506 dstreg = translate_rreg (SD_, RN0);
508 reg1 = State.regs[srcreg];
509 reg2 = State.regs[dstreg];
510 sum = reg1 + reg2 + ((PSW & PSW_C) != 0);
511 State.regs[dstreg] = sum;
513 z = ((PSW & PSW_Z) != 0) && (sum == 0);
514 n = (sum & 0x80000000);
515 c = (sum < reg1) || (sum < reg2);
516 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
517 && (reg2 & 0x80000000) != (sum & 0x80000000));
519 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
520 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
521 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
524 // 1111 1001 1001 1000 Rm Rn; sub Rm,Rn
525 8.0xf9+8.0x98+4.RM2,4.RN0:D1b:::sub
532 srcreg = translate_rreg (SD_, RM2);
533 dstreg = translate_rreg (SD_, RN0);
534 genericSub (State.regs[srcreg], dstreg);
537 // 1111 1001 1010 1000 Rm Rn; subc Rm,Rn
538 8.0xf9+8.0xa8+4.RM2,4.RN0:D1b:::subc
544 unsigned long reg1, reg2, difference;
547 srcreg = translate_rreg (SD_, RM2);
548 dstreg = translate_rreg (SD_, RN0);
550 reg1 = State.regs[srcreg];
551 reg2 = State.regs[dstreg];
552 difference = reg2 - reg1 - ((PSW & PSW_C) != 0);
553 State.regs[dstreg] = difference;
555 z = ((PSW & PSW_Z) != 0) && (difference == 0);
556 n = (difference & 0x80000000);
558 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
559 && (reg2 & 0x80000000) != (difference & 0x80000000));
561 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
562 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
563 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
566 // 1111 1001 1011 1000 Rn Rn; inc Rn
567 8.0xf9+8.0xb8+4.RN0,4.RN2=RN0:D1:::inc
574 dstreg = translate_rreg (SD_, RN0);
575 genericAdd (1, dstreg);
578 // 1111 1001 1101 1000 Rn Rn; inc Rn
579 8.0xf9+8.0xc8+4.RN0,4.RN2=RN0:D1:::inc4
586 dstreg = translate_rreg (SD_, RN0);
587 State.regs[dstreg] += 4;
590 // 1111 1001 1101 1000 Rm Rn; cmp Rm,Rn
591 8.0xf9+8.0xd8+4.RM2,4.RN0:D1:::cmp
595 int srcreg1, srcreg2;
598 srcreg1 = translate_rreg (SD_, RN0);
599 srcreg2 = translate_rreg (SD_, RM2);
600 genericCmp (State.regs[srcreg2], State.regs[srcreg1]);
603 // 1111 1001 1110 1000 XRm Rn; mov XRm,Rn
604 8.0xf9+8.0xe8+4.XRM2,4.RN0:D1l:::mov
611 dstreg = translate_rreg (SD_, RN0);
612 srcreg = translate_xreg (SD_, XRM2);
614 State.regs[dstreg] = State.regs[srcreg];
617 // 1111 1001 1111 1000 Rm XRn; mov Rm,XRn
618 8.0xf9+8.0xf8+4.RM2,4.XRN0:D1m:::mov
625 srcreg = translate_rreg (SD_, RM2);
626 dstreg = translate_xreg (SD_, XRN0);
628 State.regs[dstreg] = State.regs[srcreg];
631 // 1111 1001 0000 1001 Rm Rn; and Rm,Rn
632 8.0xf9+8.0x09+4.RM2,4.RN0:D1a:::and
641 srcreg = translate_rreg (SD_, RM2);
642 dstreg = translate_rreg (SD_, RN0);
644 State.regs[dstreg] &= State.regs[srcreg];
645 z = (State.regs[dstreg] == 0);
646 n = (State.regs[dstreg] & 0x80000000) != 0;
647 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
648 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
651 // 1111 1001 0001 1001 Rm Rn; or Rm,Rn
652 8.0xf9+8.0x19+4.RM2,4.RN0:D1a:::or
660 srcreg = translate_rreg (SD_, RM2);
661 dstreg = translate_rreg (SD_, RN0);
663 State.regs[dstreg] |= State.regs[srcreg];
664 z = (State.regs[dstreg] == 0);
665 n = (State.regs[dstreg] & 0x80000000) != 0;
666 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
667 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
670 // 1111 1001 0010 1001 Rm Rn; xor Rm,Rn
671 8.0xf9+8.0x29+4.RM2,4.RN0:D1a:::xor
679 srcreg = translate_rreg (SD_, RM2);
680 dstreg = translate_rreg (SD_, RN0);
682 State.regs[dstreg] ^= State.regs[srcreg];
683 z = (State.regs[dstreg] == 0);
684 n = (State.regs[dstreg] & 0x80000000) != 0;
685 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
686 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
689 // 1111 1001 0011 1001 Rn Rn; not Rn
690 8.0xf9+8.0x39+4.RM2,4.RN0=RM2:D1:::not
698 dstreg = translate_rreg (SD_, RN0);
700 State.regs[dstreg] = ~State.regs[dstreg];
701 z = (State.regs[dstreg] == 0);
702 n = (State.regs[dstreg] & 0x80000000) != 0;
703 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
704 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
707 // 1111 1001 0100 1001 Rm Rn; asr Rm,Rn
708 8.0xf9+8.0x49+4.RM2,4.RN0:D1a:::asr
717 srcreg = translate_rreg (SD_, RM2);
718 dstreg = translate_rreg (SD_, RN0);
720 temp = State.regs[dstreg];
722 temp >>= State.regs[srcreg];
723 State.regs[dstreg] = temp;
724 z = (State.regs[dstreg] == 0);
725 n = (State.regs[dstreg] & 0x80000000) != 0;
726 PSW &= ~(PSW_Z | PSW_N | PSW_C);
727 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
730 // 1111 1001 0101 1001 Rm Rn; lsr Rm,Rn
731 8.0xf9+8.0x59+4.RM2,4.RN0:D1a:::lsr
740 srcreg = translate_rreg (SD_, RM2);
741 dstreg = translate_rreg (SD_, RN0);
743 c = State.regs[dstreg] & 1;
744 State.regs[dstreg] >>= State.regs[srcreg];
745 z = (State.regs[dstreg] == 0);
746 n = (State.regs[dstreg] & 0x80000000) != 0;
747 PSW &= ~(PSW_Z | PSW_N | PSW_C);
748 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
751 // 1111 1001 0110 1001 Rm Rn; asl Rm,Rn
752 8.0xf9+8.0x69+4.RM2,4.RN0:D1a:::asl
760 srcreg = translate_rreg (SD_, RM2);
761 dstreg = translate_rreg (SD_, RN0);
763 State.regs[dstreg] <<= State.regs[srcreg];
764 z = (State.regs[dstreg] == 0);
765 n = (State.regs[dstreg] & 0x80000000) != 0;
766 PSW &= ~(PSW_Z | PSW_N);
767 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
770 // 1111 1001 0111 1001 Rn Rn; asl2 Rn
771 8.0xf9+8.0x79+4.RM2,4.RN0=RM2:D1:::asl2
779 dstreg = translate_rreg (SD_, RN0);
781 State.regs[dstreg] <<= 2;
782 z = (State.regs[dstreg] == 0);
783 n = (State.regs[dstreg] & 0x80000000) != 0;
784 PSW &= ~(PSW_Z | PSW_N);
785 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
788 // 1111 1001 1000 1001 Rn Rn; ror Rn
789 8.0xf9+8.0x89+4.RM2,4.RN0=RM2:D1:::ror
798 dstreg = translate_rreg (SD_, RN0);
800 value = State.regs[dstreg];
804 value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0;
805 State.regs[dstreg] = value;
807 n = (value & 0x80000000) != 0;
808 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
809 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
812 // 1111 1001 1001 1001 Rn Rn; rol Rn
813 8.0xf9+8.0x99+4.RM2,4.RN0=RM2:D1:::rol
822 dstreg = translate_rreg (SD_, RN0);
824 value = State.regs[dstreg];
825 c = (value & 0x80000000) ? 1 : 0;
828 value |= ((PSW & PSW_C) != 0);
829 State.regs[dstreg] = value;
831 n = (value & 0x80000000) != 0;
832 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
833 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
836 // 1111 1001 1010 1001 Rm Rn; mul Rm,Rn
837 8.0xf9+8.0xa9+4.RM2,4.RN0:D1b:::mul
842 unsigned long long temp;
846 srcreg = translate_rreg (SD_, RM2);
847 dstreg = translate_rreg (SD_, RN0);
849 temp = ((signed64)(signed32)State.regs[dstreg]
850 * (signed64)(signed32)State.regs[srcreg]);
851 State.regs[dstreg] = temp & 0xffffffff;
852 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
853 z = (State.regs[dstreg] == 0);
854 n = (State.regs[dstreg] & 0x80000000) != 0;
855 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
856 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
859 // 1111 1001 1011 1001 Rm Rn; mulu Rm,Rn
860 8.0xf9+8.0xb9+4.RM2,4.RN0:D1b:::mulu
865 unsigned long long temp;
869 srcreg = translate_rreg (SD_, RM2);
870 dstreg = translate_rreg (SD_, RN0);
872 temp = ((unsigned64)State.regs[dstreg]
873 * (unsigned64)State.regs[srcreg]);
874 State.regs[dstreg] = temp & 0xffffffff;
875 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
876 z = (State.regs[dstreg] == 0);
877 n = (State.regs[dstreg] & 0x80000000) != 0;
878 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
879 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
882 // 1111 1001 1100 1001 Rm Rn; div Rm,Rn
883 8.0xf9+8.0xc9+4.RM2,4.RN0:D1b:::div
892 srcreg = translate_rreg (SD_, RM2);
893 dstreg = translate_rreg (SD_, RN0);
895 temp = State.regs[REG_MDR];
897 temp |= State.regs[dstreg];
898 State.regs[REG_MDR] = temp % (signed32)State.regs[srcreg];
899 temp /= (signed32)State.regs[srcreg];
900 State.regs[dstreg] = temp & 0xffffffff;
901 z = (State.regs[dstreg] == 0);
902 n = (State.regs[dstreg] & 0x80000000) != 0;
903 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
904 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
907 // 1111 1001 1101 1001 Rm Rn; divu Rm,Rn
908 8.0xf9+8.0xd9+4.RM2,4.RN0:D1b:::divu
913 unsigned long long temp;
917 srcreg = translate_rreg (SD_, RM2);
918 dstreg = translate_rreg (SD_, RN0);
920 temp = State.regs[REG_MDR];
922 temp |= State.regs[dstreg];
923 State.regs[REG_MDR] = temp % State.regs[srcreg];
924 temp /= State.regs[srcreg];
925 State.regs[dstreg] = temp & 0xffffffff;
926 z = (State.regs[dstreg] == 0);
927 n = (State.regs[dstreg] & 0x80000000) != 0;
928 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
929 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
933 // 1111 1001 0000 1010 Rm Rn; mov (Rm),Rn
934 8.0xf9+8.0x0a+4.RN2,4.RM0:D1h:::mov
941 srcreg = translate_rreg (SD_, RM0);
942 dstreg = translate_rreg (SD_, RN2);
943 State.regs[dstreg] = load_word (State.regs[srcreg]);
946 // 1111 1001 0001 1010 Rm Rn; mov Rm,(Rn)
947 8.0xf9+8.0x1a+4.RM2,4.RN0:D1i:::mov
954 srcreg = translate_rreg (SD_, RM2);
955 dstreg = translate_rreg (SD_, RN0);
956 store_word (State.regs[dstreg], State.regs[srcreg]);
959 // 1111 1001 0010 1010 Rm Rn; movbu (Rm),Rn
960 8.0xf9+8.0x2a+4.RN2,4.RM0:D1g:::movbu
967 srcreg = translate_rreg (SD_, RM0);
968 dstreg = translate_rreg (SD_, RN2);
969 State.regs[dstreg] = load_byte (State.regs[srcreg]);
972 // 1111 1001 0011 1010 Rm Rn; movbu Rm,(Rn)
973 8.0xf9+8.0x3a+4.RM2,4.RN0:D1i:::movbu
980 srcreg = translate_rreg (SD_, RM2);
981 dstreg = translate_rreg (SD_, RN0);
982 store_byte (State.regs[dstreg], State.regs[srcreg]);
985 // 1111 1001 0100 1010 Rm Rn; movhu (Rm),Rn
986 8.0xf9+8.0x4a+4.RN2,4.RM0:D1g:::movhu
993 srcreg = translate_rreg (SD_, RM0);
994 dstreg = translate_rreg (SD_, RN2);
995 State.regs[dstreg] = load_half (State.regs[srcreg]);
998 // 1111 1001 0101 1010 Rm Rn; movhu Rm,(Rn)
999 8.0xf9+8.0x5a+4.RM2,4.RN0:D1i:::movhu
1006 srcreg = translate_rreg (SD_, RM2);
1007 dstreg = translate_rreg (SD_, RN0);
1008 store_half (State.regs[dstreg], State.regs[srcreg]);
1011 // 1111 1001 0110 1010 Rm Rn; mov (Rm+),Rn
1012 8.0xf9+8.0x6a+4.RN2,4.RM0!RN2:D1y:::mov
1019 srcreg = translate_rreg (SD_, RM0);
1020 dstreg = translate_rreg (SD_, RN2);
1021 State.regs[dstreg] = load_word (State.regs[srcreg]);
1022 State.regs[srcreg] += 4;
1025 // 1111 1001 0111 1010 Rm Rn; mov Rm,(Rn+)
1026 8.0xf9+8.0x7a+4.RM2,4.RN0:D1z:::mov
1033 srcreg = translate_rreg (SD_, RM2);
1034 dstreg = translate_rreg (SD_, RN0);
1035 store_word (State.regs[dstreg], State.regs[srcreg]);
1036 State.regs[dstreg] += 4;
1039 // 1111 1001 1000 1010 Rn 0000; mov (sp),Rn
1040 8.0xf9+8.0x8a+4.RN2,4.0000:D1j:::mov
1047 dstreg = translate_rreg (SD_, RN2);
1048 State.regs[dstreg] = load_word (State.regs[REG_SP]);
1051 // 1111 1001 1001 1010 Rm 0000; mov Rm, (sp)
1052 8.0xf9+8.0x9a+4.RM2,4.0000:D1k:::mov
1059 srcreg = translate_rreg (SD_, RM2);
1060 store_word (State.regs[REG_SP], State.regs[srcreg]);
1063 // 1111 1001 1010 1010 Rn 0000; mobvu (sp),Rn
1064 8.0xf9+8.0xaa+4.RN2,4.0000:D1j:::movbu
1071 dstreg = translate_rreg (SD_, RN2);
1072 State.regs[dstreg] = load_byte (State.regs[REG_SP]);
1075 // 1111 1001 1011 1010 Rm 0000; movbu Rm, (sp)
1076 8.0xf9+8.0xba+4.RM2,4.0000:D1k:::movbu
1083 srcreg = translate_rreg (SD_, RM2);
1084 store_byte (State.regs[REG_SP], State.regs[srcreg]);
1087 // 1111 1001 1000 1100 Rn 0000; movhu (sp),Rn
1088 8.0xf9+8.0xca+4.RN2,4.0000:D1j:::movhu
1095 dstreg = translate_rreg (SD_, RN2);
1096 State.regs[dstreg] = load_half (State.regs[REG_SP]);
1099 // 1111 1001 1001 1101 Rm 0000; movhu Rm, (sp)
1100 8.0xf9+8.0xda+4.RM2,4.0000:D1k:::movhu
1107 srcreg = translate_rreg (SD_, RM2);
1108 store_half (State.regs[REG_SP], State.regs[srcreg]);
1111 // 1111 1001 1110 1010 Rm Rn; movhu (Rm+),Rn
1112 8.0xf9+8.0xea+4.RN2,4.RM0!RN2:D1y:::movhu
1119 srcreg = translate_rreg (SD_, RM0);
1120 dstreg = translate_rreg (SD_, RN2);
1121 State.regs[dstreg] = load_half (State.regs[srcreg]);
1122 State.regs[srcreg] += 2;
1125 // 1111 1001 1111 1010 Rm Rn; movhu Rm,(Rn+)
1126 8.0xf9+8.0xfa+4.RM2,4.RN0:D1z:::movhu
1133 srcreg = translate_rreg (SD_, RM2);
1134 dstreg = translate_rreg (SD_, RN0);
1135 store_half (State.regs[dstreg], State.regs[srcreg]);
1136 State.regs[dstreg] += 2;
1140 // 1111 1001 0000 1011 Rm Rn; mac Rm,Rn
1141 8.0xf9+8.0x0b+4.RM2,4.RN0:D1:::mac
1145 int srcreg1, srcreg2;
1146 long long temp, sum;
1150 srcreg1 = translate_rreg (SD_, RM2);
1151 srcreg2 = translate_rreg (SD_, RN0);
1153 temp = ((signed64)(signed32)State.regs[srcreg2]
1154 * (signed64)(signed32)State.regs[srcreg1]);
1155 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1156 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1157 State.regs[REG_MCRL] = sum;
1160 sum = State.regs[REG_MCRH] + temp + c;
1161 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1162 && (temp & 0x80000000) != (sum & 0x80000000));
1163 State.regs[REG_MCRH] = sum;
1165 State.regs[REG_MCVF] = 1;
1168 // 1111 1001 0001 1011 Rm Rn; macu Rm,Rn
1169 8.0xf9+8.0x1b+4.RM2,4.RN0:D1:::macu
1173 int srcreg1, srcreg2;
1174 unsigned long long temp, sum;
1178 srcreg1 = translate_rreg (SD_, RM2);
1179 srcreg2 = translate_rreg (SD_, RN0);
1181 temp = ((unsigned64)State.regs[srcreg2]
1182 * (unsigned64)State.regs[srcreg1]);
1183 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1184 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1185 State.regs[REG_MCRL] = sum;
1188 sum = State.regs[REG_MCRH] + temp + c;
1189 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1190 && (temp & 0x80000000) != (sum & 0x80000000));
1191 State.regs[REG_MCRH] = sum;
1193 State.regs[REG_MCVF] = 1;
1196 // 1111 1001 0010 1011 Rm Rn; macb Rm,Rn
1197 8.0xf9+8.0x2b+4.RM2,4.RN0:D1:::macb
1201 int srcreg1, srcreg2;
1206 srcreg1 = translate_rreg (SD_, RM2);
1207 srcreg2 = translate_rreg (SD_, RN0);
1209 temp = ((signed32)(signed8)(State.regs[srcreg2] & 0xff)
1210 * (signed32)(signed8)(State.regs[srcreg1] & 0xff));
1211 sum = State.regs[REG_MCRL] + temp;
1212 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1213 && (temp & 0x80000000) != (sum & 0x80000000));
1214 State.regs[REG_MCRL] = sum;
1216 State.regs[REG_MCVF] = 1;
1219 // 1111 1001 0011 1011 Rm Rn; macbu Rm,Rn
1220 8.0xf9+8.0x3b+4.RM2,4.RN0:D1:::macbu
1224 int srcreg1, srcreg2;
1225 long long temp, sum;
1229 srcreg1 = translate_rreg (SD_, RM2);
1230 srcreg2 = translate_rreg (SD_, RN0);
1232 temp = ((unsigned32)(State.regs[srcreg2] & 0xff)
1233 * (unsigned32)(State.regs[srcreg1] & 0xff));
1234 sum = State.regs[REG_MCRL] + temp;
1235 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1236 && (temp & 0x80000000) != (sum & 0x80000000));
1237 State.regs[REG_MCRL] = sum;
1239 State.regs[REG_MCVF] = 1;
1242 // 1111 1001 0100 1011 Rm Rn; mach Rm,Rn
1243 8.0xf9+8.0x4b+4.RM2,4.RN0:D1:::mach
1247 int srcreg1, srcreg2;
1248 long long temp, sum;
1252 srcreg1 = translate_rreg (SD_, RM2);
1253 srcreg2 = translate_rreg (SD_, RN0);
1255 temp = ((unsigned64)(signed16)(State.regs[srcreg2] & 0xffff)
1256 * (unsigned64)(signed16)(State.regs[srcreg1] & 0xffff));
1257 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1258 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1259 State.regs[REG_MCRL] = sum;
1262 sum = State.regs[REG_MCRH] + temp + c;
1263 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1264 && (temp & 0x80000000) != (sum & 0x80000000));
1265 State.regs[REG_MCRH] = sum;
1267 State.regs[REG_MCVF] = 1;
1270 // 1111 1001 0101 1011 Rm Rn; machu Rm,Rn
1271 8.0xf9+8.0x5b+4.RM2,4.RN0:D1:::machu
1275 int srcreg1, srcreg2;
1276 long long temp, sum;
1280 srcreg1 = translate_rreg (SD_, RM2);
1281 srcreg2 = translate_rreg (SD_, RN0);
1283 temp = ((unsigned64)(State.regs[srcreg2] & 0xffff)
1284 * (unsigned64)(State.regs[srcreg1] & 0xffff));
1285 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1286 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1287 State.regs[REG_MCRL] = sum;
1290 sum = State.regs[REG_MCRH] + temp + c;
1291 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1292 && (temp & 0x80000000) != (sum & 0x80000000));
1293 State.regs[REG_MCRH] = sum;
1295 State.regs[REG_MCVF] = 1;
1298 // 1111 1001 0110 1011 Rm Rn; dmach Rm,Rn
1299 8.0xf9+8.0x6b+4.RM2,4.RN0:D1:::dmach
1303 int srcreg1, srcreg2;
1304 long temp, temp2, sum;
1308 srcreg1 = translate_rreg (SD_, RM2);
1309 srcreg2 = translate_rreg (SD_, RN0);
1311 temp = ((signed32)(signed16)(State.regs[srcreg2] & 0xffff)
1312 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
1313 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
1314 * (signed32)(signed16)((State.regs[srcreg2] >> 16) & 0xffff));
1315 sum = temp + temp2 + State.regs[REG_MCRL];
1316 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1317 && (temp & 0x80000000) != (sum & 0x80000000));
1318 State.regs[REG_MCRL] = sum;
1320 State.regs[REG_MCVF] = 1;
1323 // 1111 1001 0111 1011 Rm Rn; dmachu Rm,Rn
1324 8.0xf9+8.0x7b+4.RM2,4.RN0:D1:::dmachu
1328 int srcreg1, srcreg2;
1329 unsigned long temp, temp2, sum;
1333 srcreg1 = translate_rreg (SD_, RM2);
1334 srcreg2 = translate_rreg (SD_, RN0);
1336 temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
1337 * (unsigned32)(State.regs[srcreg1] & 0xffff));
1338 temp2 = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
1339 * (unsigned32)((State.regs[srcreg2] >> 16) & 0xffff));
1340 sum = temp + temp2 + State.regs[REG_MCRL];
1341 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1342 && (temp & 0x80000000) != (sum & 0x80000000));
1343 State.regs[REG_MCRL] = sum;
1345 State.regs[REG_MCVF] = 1;
1348 // 1111 1001 1000 1011 Rm Rn; dmulh Rm,Rn
1349 8.0xf9+8.0x8b+4.RM2,4.RN0:D1:::dmulh
1357 srcreg = translate_rreg (SD_, RM2);
1358 dstreg = translate_rreg (SD_, RN0);
1360 temp = ((signed32)(signed16)(State.regs[dstreg] & 0xffff)
1361 * (signed32)(signed16)(State.regs[srcreg] & 0xffff));
1362 State.regs[REG_MDRQ] = temp;
1363 temp = ((signed32)(signed16)((State.regs[dstreg] >> 16) & 0xffff)
1364 * (signed32)(signed16)((State.regs[srcreg] >>16) & 0xffff));
1365 State.regs[dstreg] = temp;
1368 // 1111 1001 1001 1011 Rm Rn; dmulhu Rm,Rn
1369 8.0xf9+8.0x9b+4.RM2,4.RN0:D1:::dumachu
1377 srcreg = translate_rreg (SD_, RM2);
1378 dstreg = translate_rreg (SD_, RN0);
1380 temp = ((unsigned32)(State.regs[dstreg] & 0xffff)
1381 * (unsigned32)(State.regs[srcreg] & 0xffff));
1382 State.regs[REG_MDRQ] = temp;
1383 temp = ((unsigned32)((State.regs[dstreg] >> 16) & 0xffff)
1384 * (unsigned32)((State.regs[srcreg] >>16) & 0xffff));
1385 State.regs[dstreg] = temp;
1388 // 1111 1001 1010 1011 Rm Rn; sat16 Rm,Rn
1389 8.0xf9+8.0xab+4.RM2,4.RN0:D1:::sat16
1397 srcreg = translate_rreg (SD_, RM2);
1398 dstreg = translate_rreg (SD_, RN0);
1400 value = State.regs[srcreg];
1402 if (value >= 0x7fff)
1403 State.regs[dstreg] = 0x7fff;
1404 else if (value <= 0xffff8000)
1405 State.regs[dstreg] = 0xffff8000;
1407 State.regs[dstreg] = value;
1409 n = (State.regs[dstreg] & 0x8000) != 0;
1410 z = (State.regs[dstreg] == 0);
1411 PSW &= ~(PSW_Z | PSW_N);
1412 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1415 // 1111 1001 1011 1011 Rm Rn; mcste Rm,Rn
1416 8.0xf9+8.0xbb+4.RM2,4.RN0:D1:::mcste
1423 srcreg = translate_rreg (SD_, RM2);
1424 dstreg = translate_rreg (SD_, RN0);
1426 PSW &= ~(PSW_V | PSW_C);
1427 PSW |= (State.regs[REG_MCVF] ? PSW_V : 0);
1429 /* 32bit saturation. */
1430 if (State.regs[srcreg] == 0x20)
1434 tmp = State.regs[REG_MCRH];
1436 tmp += State.regs[REG_MCRL];
1438 if (tmp > 0x7fffffff)
1439 State.regs[dstreg] = 0x7fffffff;
1440 else if (tmp < 0xffffffff80000000LL)
1441 State.regs[dstreg] = 0x80000000;
1443 State.regs[dstreg] = tmp;
1445 /* 16bit saturation */
1446 else if (State.regs[srcreg] == 0x10)
1450 tmp = State.regs[REG_MCRH];
1452 tmp += State.regs[REG_MCRL];
1455 State.regs[dstreg] = 0x7fff;
1456 else if (tmp < 0xffffffffffff8000LL)
1457 State.regs[dstreg] = 0x8000;
1459 State.regs[dstreg] = tmp;
1461 /* 8 bit saturation */
1462 else if (State.regs[srcreg] == 0x8)
1466 tmp = State.regs[REG_MCRH];
1468 tmp += State.regs[REG_MCRL];
1471 State.regs[dstreg] = 0x7f;
1472 else if (tmp < 0xffffffffffffff80LL)
1473 State.regs[dstreg] = 0x80;
1475 State.regs[dstreg] = tmp;
1477 /* 9 bit saturation */
1478 else if (State.regs[srcreg] == 0x9)
1482 tmp = State.regs[REG_MCRH];
1484 tmp += State.regs[REG_MCRL];
1487 State.regs[dstreg] = 0x80;
1488 else if (tmp < 0xffffffffffffff81LL)
1489 State.regs[dstreg] = 0x81;
1491 State.regs[dstreg] = tmp;
1493 /* 9 bit saturation */
1494 else if (State.regs[srcreg] == 0x30)
1498 tmp = State.regs[REG_MCRH];
1500 tmp += State.regs[REG_MCRL];
1502 if (tmp > 0x7fffffffffffLL)
1503 tmp = 0x7fffffffffffLL;
1504 else if (tmp < 0xffff800000000000LL)
1505 tmp = 0xffff800000000000LL;
1508 State.regs[dstreg] = tmp;
1512 // 1111 1001 1100 1011 Rm Rn; swap Rm,Rn
1513 8.0xf9+8.0xcb+4.RM2,4.RN0:D1:::swap
1520 srcreg = translate_rreg (SD_, RM2);
1521 dstreg = translate_rreg (SD_, RN0);
1523 State.regs[dstreg] = (((State.regs[srcreg] & 0xff) << 24)
1524 | (((State.regs[srcreg] >> 8) & 0xff) << 16)
1525 | (((State.regs[srcreg] >> 16) & 0xff) << 8)
1526 | ((State.regs[srcreg] >> 24) & 0xff));
1529 // 1111 1101 1101 1011 Rm Rn; swaph Rm,Rn
1530 8.0xf9+8.0xdb+4.RM2,4.RN0:D1:::swaph
1537 srcreg = translate_rreg (SD_, RM2);
1538 dstreg = translate_rreg (SD_, RN0);
1540 State.regs[dstreg] = (((State.regs[srcreg] & 0xff) << 8)
1541 | ((State.regs[srcreg] >> 8) & 0xff)
1542 | (((State.regs[srcreg] >> 16) & 0xff) << 24)
1543 | (((State.regs[srcreg] >> 24) & 0xff) << 16));
1546 // 1111 1001 1110 1011 Rm Rn; swhw Rm,Rn
1547 8.0xf9+8.0xeb+4.RM2,4.RN0:D1:::swhw
1554 srcreg = translate_rreg (SD_, RM2);
1555 dstreg = translate_rreg (SD_, RN0);
1557 State.regs[dstreg] = (((State.regs[srcreg] & 0xffff) << 16)
1558 | ((State.regs[srcreg] >> 16) & 0xffff));
1561 // 1111 1001 1111 1011 Rm Rn; bsch Rm,Rn
1562 8.0xf9+8.0xfb+4.RM2,4.RN0:D1:::bsch
1571 srcreg = translate_rreg (SD_, RM2);
1572 dstreg = translate_rreg (SD_, RN0);
1574 temp = State.regs[srcreg];
1575 start = (State.regs[dstreg] & 0x1f) - 1;
1579 for (i = start; i >= 0; i--)
1581 if (temp & (1 << i))
1584 State.regs[dstreg] = i;
1592 State.regs[dstreg] = 0;
1595 PSW |= (c ? PSW_C : 0);
1599 // 1111 1011 0000 1000 Rn Rn IMM8; mov IMM8,Rn
1600 8.0xfb+8.0x08+4.RM2,4.RN0=RM2+8.IMM8:D2j:::mov
1607 dstreg = translate_rreg (SD_, RN0);
1608 State.regs[dstreg] = EXTEND8 (IMM8);
1611 // 1111 1011 0001 1000 Rn Rn IMM8; movu IMM8,Rn
1612 8.0xfb+8.0x18+4.RM2,4.RN0=RM2+8.IMM8:D2:::movu
1619 dstreg = translate_rreg (SD_, RN0);
1620 State.regs[dstreg] = IMM8 & 0xff;
1623 // 1111 1011 0111 1000 Rn Rn IMM8; add IMM8,Rn
1624 8.0xfb+8.0x78+4.RM2,4.RN0=RM2+8.IMM8:D2d:::add
1631 dstreg = translate_rreg (SD_, RN0);
1632 genericAdd (EXTEND8 (IMM8), dstreg);
1635 // 1111 1011 1000 1000 Rn Rn IMM8; addc IMM8,Rn
1636 8.0xfb+8.0x88+4.RM2,4.RN0=RM2+8.IMM8:D2d:::addc
1642 unsigned long reg1, reg2, sum;
1645 dstreg = translate_rreg (SD_, RN0);
1647 imm = EXTEND8 (IMM8);
1648 reg2 = State.regs[dstreg];
1649 sum = imm + reg2 + ((PSW & PSW_C) != 0);
1650 State.regs[dstreg] = sum;
1652 z = ((PSW & PSW_Z) != 0) && (sum == 0);
1653 n = (sum & 0x80000000);
1654 c = (sum < imm) || (sum < reg2);
1655 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
1656 && (reg2 & 0x80000000) != (sum & 0x80000000));
1658 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1659 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1660 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1663 // 1111 1011 1001 1000 Rn Rn IMM8; sub IMM8,Rn
1664 8.0xfb+8.0x98+4.RM2,4.RN0=RM2+8.IMM8:D2d:::sub
1671 dstreg = translate_rreg (SD_, RN0);
1673 genericSub (EXTEND8 (IMM8), dstreg);
1676 // 1111 1011 1010 1000 Rn Rn IMM8; subc IMM8,Rn
1677 8.0xfb+8.0xa8+4.RM2,4.RN0=RM2+8.IMM8:D2d:::subc
1683 unsigned long reg1, reg2, difference;
1686 dstreg = translate_rreg (SD_, RN0);
1688 imm = EXTEND8 (IMM8);
1689 reg2 = State.regs[dstreg];
1690 difference = reg2 - imm - ((PSW & PSW_C) != 0);
1691 State.regs[dstreg] = difference;
1693 z = ((PSW & PSW_Z) != 0) && (difference == 0);
1694 n = (difference & 0x80000000);
1696 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
1697 && (reg2 & 0x80000000) != (difference & 0x80000000));
1699 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1700 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1701 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1704 // 1111 1011 1101 1000 Rn Rn IMM8; cmp IMM8,Rn
1705 8.0xfb+8.0xd8+4.RM2,4.RN0=RM2+8.IMM8:D2b:::cmp
1712 srcreg = translate_rreg (SD_, RN0);
1713 genericCmp (EXTEND8 (IMM8), State.regs[srcreg]);
1716 // 1111 1011 1111 1000 XRn XRn IMM8; mov IMM8,XRn
1717 8.0xfb+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM8:D2k:::mov
1724 dstreg = translate_xreg (SD_, XRN0);
1726 State.regs[dstreg] = IMM8;
1729 // 1111 1011 0000 1001 Rn Rn IMM8; and IMM8,Rn
1730 8.0xfb+8.0x09+4.RM2,4.RN0=RM2+8.IMM8:D2d:::and
1738 dstreg = translate_rreg (SD_, RN0);
1740 State.regs[dstreg] &= (IMM8 & 0xff);
1741 z = (State.regs[dstreg] == 0);
1742 n = (State.regs[dstreg] & 0x80000000) != 0;
1743 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1744 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1747 // 1111 1011 0001 1001 Rn Rn IMM8; or IMM8,Rn
1748 8.0xfb+8.0x19+4.RM2,4.RN0=RM2+8.IMM8:D2d:::or
1756 dstreg = translate_rreg (SD_, RN0);
1758 State.regs[dstreg] |= (IMM8 & 0xff);
1759 z = (State.regs[dstreg] == 0);
1760 n = (State.regs[dstreg] & 0x80000000) != 0;
1761 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1762 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1765 // 1111 1011 0010 1001 Rn Rn IMM8; xor IMM8,Rn
1766 8.0xfb+8.0x29+4.RM2,4.RN0=RM2+8.IMM8:D2d:::xor
1774 dstreg = translate_rreg (SD_, RN0);
1776 State.regs[dstreg] ^= (IMM8 & 0xff);
1777 z = (State.regs[dstreg] == 0);
1778 n = (State.regs[dstreg] & 0x80000000) != 0;
1779 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1780 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1783 // 1111 1011 0100 1001 Rn Rn IMM8; asr IMM8,Rn
1784 8.0xfb+8.0x49+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asr
1793 dstreg = translate_rreg (SD_, RN0);
1795 temp = State.regs[dstreg];
1797 temp >>= (IMM8 & 0xff);
1798 State.regs[dstreg] = temp;
1799 z = (State.regs[dstreg] == 0);
1800 n = (State.regs[dstreg] & 0x80000000) != 0;
1801 PSW &= ~(PSW_Z | PSW_N | PSW_C);
1802 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1805 // 1111 1011 0101 1001 Rn Rn IMM8; lsr IMM8,Rn
1806 8.0xfb+8.0x59+4.RM2,4.RN0=RM2+8.IMM8:D2a:::lsr
1814 dstreg = translate_rreg (SD_, RN0);
1816 c = State.regs[dstreg] & 1;
1817 State.regs[dstreg] >>= (IMM8 & 0xff);
1818 z = (State.regs[dstreg] == 0);
1819 n = (State.regs[dstreg] & 0x80000000) != 0;
1820 PSW &= ~(PSW_Z | PSW_N | PSW_C);
1821 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1824 // 1111 1011 0110 1001 Rn Rn IMM8; asl IMM8,Rn
1825 8.0xfb+8.0x69+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asl
1833 dstreg = translate_rreg (SD_, RN0);
1835 State.regs[dstreg] <<= (IMM8 & 0xff);
1836 z = (State.regs[dstreg] == 0);
1837 n = (State.regs[dstreg] & 0x80000000) != 0;
1838 PSW &= ~(PSW_Z | PSW_N);
1839 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1842 // 1111 1011 1010 1001 Rn Rn IMM8; mul IMM8,Rn
1843 8.0xfb+8.0xa9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mul
1848 unsigned long long temp;
1852 dstreg = translate_rreg (SD_, RN0);
1854 temp = ((signed64)(signed32)State.regs[dstreg]
1855 * (signed64)(signed32)EXTEND8 (IMM8));
1856 State.regs[dstreg] = temp & 0xffffffff;
1857 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
1858 z = (State.regs[dstreg] == 0);
1859 n = (State.regs[dstreg] & 0x80000000) != 0;
1860 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1861 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1864 // 1111 1011 1011 1001 Rn Rn IMM8; mulu IMM8,Rn
1865 8.0xfb+8.0xb9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mulu
1870 unsigned long long temp;
1874 dstreg = translate_rreg (SD_, RN0);
1876 temp = ((unsigned64)State.regs[dstreg]
1877 * (unsigned64)(IMM8 & 0xff));
1878 State.regs[dstreg] = temp & 0xffffffff;
1879 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
1880 z = (State.regs[dstreg] == 0);
1881 n = (State.regs[dstreg] & 0x80000000) != 0;
1882 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1883 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1886 // 1111 1011 1110 1001 Rn Rn IMM8; btst imm8,Rn
1887 8.0xfb+8.0xe9+4.RN2,4.RM0=RN2+8.IMM8:D2l:::btst
1894 srcreg = translate_rreg (SD_, RM0);
1895 genericBtst(IMM8, State.regs[srcreg]);
1898 // 1111 1011 0000 1010 Rn Rm IMM8; mov (d8,Rm),Rn
1899 8.0xfb+8.0x0a+4.RN2,4.RM0+8.IMM8:D2l:::mov
1906 srcreg = translate_rreg (SD_, RM0);
1907 dstreg = translate_rreg (SD_, RN2);
1908 State.regs[dstreg] = load_word (State.regs[srcreg] + EXTEND8 (IMM8));
1911 // 1111 1011 0001 1010 Rn Rm IMM8; mov Rm,(d8,Rn)
1912 8.0xfb+8.0x1a+4.RM2,4.RN0+8.IMM8:D2m:::mov
1918 srcreg = translate_rreg (SD_, RM2);
1919 dstreg = translate_rreg (SD_, RN0);
1920 store_word (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1923 // 1111 1011 0010 1010 Rn Rm IMM8; movbu (d8,Rm),Rn
1924 8.0xfb+8.0x2a+4.RN2,4.RM0+8.IMM8:D2l:::movbu
1930 srcreg = translate_rreg (SD_, RM0);
1931 dstreg = translate_rreg (SD_, RN2);
1932 State.regs[dstreg] = load_byte (State.regs[srcreg] + EXTEND8 (IMM8));
1935 // 1111 1011 0011 1010 Rn Rm IMM8; movbu Rm,(d8,Rn)
1936 8.0xfb+8.0x3a+4.RM2,4.RN0+8.IMM8:D2m:::movbu
1942 srcreg = translate_rreg (SD_, RM2);
1943 dstreg = translate_rreg (SD_, RN0);
1944 store_byte (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1947 // 1111 1011 0100 1010 Rn Rm IMM8; movhu (d8,Rm),Rn
1948 8.0xfb+8.0x4a+4.RN2,4.RM0+8.IMM8:D2l:::movhu
1954 srcreg = translate_rreg (SD_, RM0);
1955 dstreg = translate_rreg (SD_, RN2);
1956 State.regs[dstreg] = load_half (State.regs[srcreg] + EXTEND8 (IMM8));
1959 // 1111 1011 0101 1010 Rn Rm IMM8; movhu Rm,(d8,Rn)
1960 8.0xfb+8.0x5a+4.RM2,4.RN0+8.IMM8:D2m:::movhu
1966 srcreg = translate_rreg (SD_, RM2);
1967 dstreg = translate_rreg (SD_, RN0);
1968 store_half (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1971 // 1111 1011 0110 1010 Rn Rm IMM8; mov (d8,Rm+),Rn
1972 8.0xfb+8.0x6a+4.RN2,4.RM0!RN2+8.IMM8:D2y:::mov
1979 srcreg = translate_rreg (SD_, RM0);
1980 dstreg = translate_rreg (SD_, RN2);
1981 State.regs[dstreg] = load_word (State.regs[srcreg]);
1982 State.regs[srcreg] += EXTEND8 (IMM8);
1985 // 1111 1011 0111 1010 Rn Rm IMM8; mov Rm,(d8,Rn+)
1986 8.0xfb+8.0x7a+4.RM2,4.RN0+8.IMM8:D2z:::mov
1992 srcreg = translate_rreg (SD_, RM2);
1993 dstreg = translate_rreg (SD_, RN0);
1994 store_word (State.regs[dstreg], State.regs[srcreg]);
1995 State.regs[dstreg] += EXTEND8 (IMM8);
1999 // 1111 1011 1000 1010 Rn 0000 IMM8; mov (d8,sp),Rn
2000 8.0xfb+8.0x8a+4.RN2,4.0x0+8.IMM8:D2n:::mov
2006 dstreg = translate_rreg (SD_, RN2);
2007 State.regs[dstreg] = load_word (State.regs[REG_SP] + EXTEND8 (IMM8));
2010 // 1111 1011 1001 1010 Rm 0000 IMM8; mov Rm,(d8,Rn)
2011 8.0xfb+8.0x9a+4.RM2,4.0x0+8.IMM8:D2o:::mov
2017 srcreg = translate_rreg (SD_, RM2);
2018 store_word (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
2021 // 1111 1011 1010 1010 Rn Rm IMM8; movbu (d8,sp),Rn
2022 8.0xfb+8.0xaa+4.RN2,4.0x0+8.IMM8:D2n:::movbu
2028 dstreg = translate_rreg (SD_, RN2);
2029 State.regs[dstreg] = load_byte (State.regs[REG_SP] + EXTEND8 (IMM8));
2032 // 1111 1011 1011 1010 Rn Rm IMM8; movbu Rm,(sp,Rn)
2033 8.0xfb+8.0xba+4.RM2,4.0x0+8.IMM8:D2o:::movbu
2039 srcreg = translate_rreg (SD_, RM2);
2040 store_byte (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
2043 // 1111 1011 1100 1010 Rn Rm IMM8; movhu (d8,sp),Rn
2044 8.0xfb+8.0xca+4.RN2,4.0x0+8.IMM8:D2n:::movhu
2050 dstreg = translate_rreg (SD_, RN2);
2051 State.regs[dstreg] = load_half (State.regs[REG_SP] + EXTEND8 (IMM8));
2054 // 1111 1011 1101 1010 Rn Rm IMM8; movhu Rm,(d8,sp)
2055 8.0xfb+8.0xda+4.RM2,4.0x0+8.IMM8:D2o:::movhu
2061 srcreg = translate_rreg (SD_, RM2);
2062 store_half (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
2065 // 1111 1011 1110 1010 Rn Rm IMM8; movhu (d8,Rm+),Rn
2066 8.0xfb+8.0xea+4.RN2,4.RM0!RN2+8.IMM8:D2y:::movhu
2073 srcreg = translate_rreg (SD_, RM0);
2074 dstreg = translate_rreg (SD_, RN2);
2075 State.regs[dstreg] = load_half (State.regs[srcreg]);
2076 State.regs[srcreg] += EXTEND8 (IMM8);
2079 // 1111 1011 1111 1010 Rn Rm IMM8; movhu Rm,(d8,Rn+)
2080 8.0xfb+8.0xfa+4.RM2,4.RN0+8.IMM8:D2z:::movhu
2086 srcreg = translate_rreg (SD_, RM2);
2087 dstreg = translate_rreg (SD_, RN0);
2088 store_half (State.regs[dstreg], State.regs[srcreg]);
2089 State.regs[dstreg] += EXTEND8 (IMM8);
2093 // 1111 1011 0000 1011 Rn Rn IMM8; mac imm8,Rn
2094 8.0xfb+8.0x0b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mac
2098 long long temp, sum;
2102 srcreg = translate_rreg (SD_, RN2);
2104 temp = ((signed64)(signed32)EXTEND8 (IMM8)
2105 * (signed64)(signed32)State.regs[srcreg]);
2106 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2107 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2108 State.regs[REG_MCRL] = sum;
2111 sum = State.regs[REG_MCRH] + temp + c;
2112 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2113 && (temp & 0x80000000) != (sum & 0x80000000));
2114 State.regs[REG_MCRH] = sum;
2116 State.regs[REG_MCVF] = 1;
2119 // 1111 1011 0001 1011 Rn Rn IMM8; macu imm8,Rn
2120 8.0xfb+8.0x1b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macu
2124 long long temp, sum;
2128 srcreg = translate_rreg (SD_, RN2);
2130 temp = ((unsigned64) (IMM8)
2131 * (unsigned64)State.regs[srcreg]);
2132 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2133 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2134 State.regs[REG_MCRL] = sum;
2137 sum = State.regs[REG_MCRH] + temp + c;
2138 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2139 && (temp & 0x80000000) != (sum & 0x80000000));
2140 State.regs[REG_MCRH] = sum;
2142 State.regs[REG_MCVF] = 1;
2145 // 1111 1011 0010 1011 Rn Rn IMM8; macb imm8,Rn
2146 8.0xfb+8.0x2b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macb
2150 long long temp, sum;
2154 srcreg = translate_rreg (SD_, RN2);
2156 temp = ((signed64)(signed8)EXTEND8 (IMM8)
2157 * (signed64)(signed8)State.regs[srcreg] & 0xff);
2158 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2159 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2160 State.regs[REG_MCRL] = sum;
2163 sum = State.regs[REG_MCRH] + temp + c;
2164 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2165 && (temp & 0x80000000) != (sum & 0x80000000));
2166 State.regs[REG_MCRH] = sum;
2168 State.regs[REG_MCVF] = 1;
2171 // 1111 1011 0011 1011 Rn Rn IMM8; macbu imm8,Rn
2172 8.0xfb+8.0x3b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macbu
2176 long long temp, sum;
2180 srcreg = translate_rreg (SD_, RN2);
2182 temp = ((unsigned64) (IMM8)
2183 * (unsigned64)State.regs[srcreg] & 0xff);
2184 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2185 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2186 State.regs[REG_MCRL] = sum;
2189 sum = State.regs[REG_MCRH] + temp + c;
2190 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2191 && (temp & 0x80000000) != (sum & 0x80000000));
2192 State.regs[REG_MCRH] = sum;
2194 State.regs[REG_MCVF] = 1;
2197 // 1111 1011 0100 1011 Rn Rn IMM8; mach imm8,Rn
2198 8.0xfb+8.0x4b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mach
2202 long long temp, sum;
2206 srcreg = translate_rreg (SD_, RN2);
2208 temp = ((signed64)(signed16)EXTEND8 (IMM8)
2209 * (signed64)(signed16)State.regs[srcreg] & 0xffff);
2210 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2211 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2212 State.regs[REG_MCRL] = sum;
2215 sum = State.regs[REG_MCRH] + temp + c;
2216 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2217 && (temp & 0x80000000) != (sum & 0x80000000));
2218 State.regs[REG_MCRH] = sum;
2220 State.regs[REG_MCVF] = 1;
2223 // 1111 1011 0101 1011 Rn Rn IMM8; machu imm8,Rn
2224 8.0xfb+8.0x5b+4.RN2,4.RN0=RN2+8.IMM8:D2:::machu
2228 long long temp, sum;
2232 srcreg = translate_rreg (SD_, RN2);
2234 temp = ((unsigned64) (IMM8)
2235 * (unsigned64)State.regs[srcreg] & 0xffff);
2236 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2237 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2238 State.regs[REG_MCRL] = sum;
2241 sum = State.regs[REG_MCRH] + temp + c;
2242 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2243 && (temp & 0x80000000) != (sum & 0x80000000));
2244 State.regs[REG_MCRH] = sum;
2246 State.regs[REG_MCVF] = 1;
2249 // 1111 1011 1011 1011 Rn Rn IMM8; mcste imm8,Rn
2250 8.0xfb+8.0xbb+4.RN2,4.RN0=RN2+8.IMM8:D2:::mcste
2256 dstreg = translate_rreg (SD_, RN0);
2258 PSW &= ~(PSW_V | PSW_C);
2259 PSW |= (State.regs[REG_MCVF] ? PSW_V : 0);
2261 /* 32bit saturation. */
2266 tmp = State.regs[REG_MCRH];
2268 tmp += State.regs[REG_MCRL];
2270 if (tmp > 0x7fffffff)
2271 State.regs[dstreg] = 0x7fffffff;
2272 else if (tmp < 0xffffffff80000000LL)
2273 State.regs[dstreg] = 0x80000000;
2275 State.regs[dstreg] = tmp;
2277 /* 16bit saturation */
2278 else if (IMM8 == 0x10)
2282 tmp = State.regs[REG_MCRH];
2284 tmp += State.regs[REG_MCRL];
2287 State.regs[dstreg] = 0x7fff;
2288 else if (tmp < 0xffffffffffff8000LL)
2289 State.regs[dstreg] = 0x8000;
2291 State.regs[dstreg] = tmp;
2293 /* 8 bit saturation */
2294 else if (IMM8 == 0x8)
2298 tmp = State.regs[REG_MCRH];
2300 tmp += State.regs[REG_MCRL];
2303 State.regs[dstreg] = 0x7f;
2304 else if (tmp < 0xffffffffffffff80LL)
2305 State.regs[dstreg] = 0x80;
2307 State.regs[dstreg] = tmp;
2309 /* 9 bit saturation */
2310 else if (IMM8 == 0x9)
2314 tmp = State.regs[REG_MCRH];
2316 tmp += State.regs[REG_MCRL];
2319 State.regs[dstreg] = 0x80;
2320 else if (tmp < 0xffffffffffffff81LL)
2321 State.regs[dstreg] = 0x81;
2323 State.regs[dstreg] = tmp;
2325 /* 9 bit saturation */
2326 else if (IMM8 == 0x30)
2330 tmp = State.regs[REG_MCRH];
2332 tmp += State.regs[REG_MCRL];
2334 if (tmp > 0x7fffffffffffLL)
2335 tmp = 0x7fffffffffffLL;
2336 else if (tmp < 0xffff800000000000LL)
2337 tmp = 0xffff800000000000LL;
2340 State.regs[dstreg] = tmp;
2344 // 1111 1011 0111 1100 Rm Rn Rd; add Rm,Rn,Rd
2345 8.0xfb+8.0x7c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::add
2350 unsigned long sum, source1, source2;
2351 int srcreg1, srcreg2, dstreg;
2354 srcreg1 = translate_rreg (SD_, RM2);
2355 srcreg2 = translate_rreg (SD_, RN0);
2356 dstreg = translate_rreg (SD_, RD0);
2358 source1 = State.regs[srcreg1];
2359 source2 = State.regs[srcreg2];
2360 sum = source1 + source2;
2361 State.regs[dstreg] = sum;
2364 n = (sum & 0x80000000);
2365 c = (sum < source1) || (sum < source2);
2366 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2367 && (source1 & 0x80000000) != (sum & 0x80000000));
2369 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2370 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2371 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2374 // 1111 1011 1000 1100 Rm Rn Rd; addc Rm,Rn,Rd
2375 8.0xfb+8.0x8c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::addc
2380 unsigned long sum, source1, source2;
2381 int srcreg1, srcreg2, dstreg;
2384 srcreg1 = translate_rreg (SD_, RM2);
2385 srcreg2 = translate_rreg (SD_, RN0);
2386 dstreg = translate_rreg (SD_, RD0);
2388 source1 = State.regs[srcreg1];
2389 source2 = State.regs[srcreg2];
2390 sum = source1 + source2 + ((PSW & PSW_C) != 0);
2391 State.regs[dstreg] = sum;
2393 z = ((PSW & PSW_Z) != 0) && (sum == 0);
2394 n = (sum & 0x80000000);
2395 c = (sum < source1) || (sum < source2);
2396 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2397 && (source1 & 0x80000000) != (sum & 0x80000000));
2399 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2400 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2401 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2404 // 1111 1011 1001 1100 Rm Rn Rd; sub Rm,Rn,Rd
2405 8.0xfb+8.0x9c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::sub
2410 unsigned long difference, source1, source2;
2411 int srcreg1, srcreg2, dstreg;
2414 srcreg1 = translate_rreg (SD_, RM2);
2415 srcreg2 = translate_rreg (SD_, RN0);
2416 dstreg = translate_rreg (SD_, RD0);
2418 source1 = State.regs[srcreg1];
2419 source2 = State.regs[srcreg2];
2420 difference = source2 - source1;
2421 State.regs[dstreg] = difference;
2423 z = (difference == 0);
2424 n = (difference & 0x80000000);
2425 c = (source1 > source1);
2426 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2427 && (source1 & 0x80000000) != (difference & 0x80000000));
2429 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2430 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2431 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2434 // 1111 1011 1010 1100 Rm Rn Rd; subc Rm,Rn,Rd
2435 8.0xfb+8.0xac+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::subc
2440 unsigned long difference, source1, source2;
2441 int srcreg1, srcreg2, dstreg;
2444 srcreg1 = translate_rreg (SD_, RM2);
2445 srcreg2 = translate_rreg (SD_, RN0);
2446 dstreg = translate_rreg (SD_, RD0);
2448 source1 = State.regs[srcreg1];
2449 source2 = State.regs[srcreg2];
2450 difference = source2 - source1 - ((PSW & PSW_C) != 0);
2451 State.regs[dstreg] = difference;
2453 z = ((PSW & PSW_Z) != 0) && (difference == 0);
2454 n = (difference & 0x80000000);
2455 c = (source1 > source2);
2456 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2457 && (source1 & 0x80000000) != (difference & 0x80000000));
2459 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2460 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2461 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2464 // 1111 1011 0000 1101 Rm Rn Rd; and Rm,Rn,Rd
2465 8.0xfb+8.0x0d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::and
2470 int srcreg1, srcreg2, dstreg;
2473 srcreg1 = translate_rreg (SD_, RM2);
2474 srcreg2 = translate_rreg (SD_, RN0);
2475 dstreg = translate_rreg (SD_, RD0);
2477 State.regs[dstreg] = State.regs[srcreg1] & State.regs[srcreg2];
2479 z = (State.regs[dstreg] == 0);
2480 n = (State.regs[dstreg] & 0x80000000);
2482 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2483 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2486 // 1111 1011 0001 1101 Rm Rn Rd; or Rm,Rn,Rd
2487 8.0xfb+8.0x1d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::or
2492 int srcreg1, srcreg2, dstreg;
2495 srcreg1 = translate_rreg (SD_, RM2);
2496 srcreg2 = translate_rreg (SD_, RN0);
2497 dstreg = translate_rreg (SD_, RD0);
2499 State.regs[dstreg] = State.regs[srcreg1] | State.regs[srcreg2];
2501 z = (State.regs[dstreg] == 0);
2502 n = (State.regs[dstreg] & 0x80000000);
2504 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2505 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2508 // 1111 1011 0010 1101 Rm Rn Rd; xor Rm,Rn,Rd
2509 8.0xfb+8.0x2d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::xor
2514 int srcreg1, srcreg2, dstreg;
2517 srcreg1 = translate_rreg (SD_, RM2);
2518 srcreg2 = translate_rreg (SD_, RN0);
2519 dstreg = translate_rreg (SD_, RD0);
2521 State.regs[dstreg] = State.regs[srcreg1] ^ State.regs[srcreg2];
2523 z = (State.regs[dstreg] == 0);
2524 n = (State.regs[dstreg] & 0x80000000);
2526 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2527 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2530 // 1111 1011 0100 1101 Rm Rn Rd; asr Rm,Rn,Rd
2531 8.0xfb+8.0x4d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asr
2537 int srcreg1, srcreg2, dstreg;
2540 srcreg1 = translate_rreg (SD_, RM2);
2541 srcreg2 = translate_rreg (SD_, RN0);
2542 dstreg = translate_rreg (SD_, RD0);
2544 temp = State.regs[srcreg2];
2546 temp >>= State.regs[srcreg1];
2547 State.regs[dstreg] = temp;
2549 z = (State.regs[dstreg] == 0);
2550 n = (State.regs[dstreg] & 0x80000000);
2552 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2553 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2556 // 1111 1011 0101 1101 Rm Rn Rd; lsr Rm,Rn,Rd
2557 8.0xfb+8.0x5d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::lsr
2562 int srcreg1, srcreg2, dstreg;
2565 srcreg1 = translate_rreg (SD_, RM2);
2566 srcreg2 = translate_rreg (SD_, RN0);
2567 dstreg = translate_rreg (SD_, RD0);
2569 c = State.regs[srcreg2] & 1;
2570 State.regs[dstreg] = State.regs[srcreg2] >> State.regs[srcreg1];
2572 z = (State.regs[dstreg] == 0);
2573 n = (State.regs[dstreg] & 0x80000000);
2575 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2576 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2579 // 1111 1011 0110 1101 Rm Rn Rd; asl Rm,Rn,Rd
2580 8.0xfb+8.0x6d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asl
2585 int srcreg1, srcreg2, dstreg;
2588 srcreg1 = translate_rreg (SD_, RM2);
2589 srcreg2 = translate_rreg (SD_, RN0);
2590 dstreg = translate_rreg (SD_, RD0);
2592 State.regs[dstreg] = State.regs[srcreg2] << State.regs[srcreg1];
2594 z = (State.regs[dstreg] == 0);
2595 n = (State.regs[dstreg] & 0x80000000);
2597 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2598 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2601 // 1111 1011 1010 1101 Rm Rn Rd1 Rd2; mul Rm,Rn,Rd1,Rd2
2602 8.0xfb+8.0xad+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mul
2606 int srcreg1, srcreg2, dstreg1, dstreg2;
2607 signed long long temp;
2611 srcreg1 = translate_rreg (SD_, RM2);
2612 srcreg2 = translate_rreg (SD_, RN0);
2613 dstreg1 = translate_rreg (SD_, RD0);
2614 dstreg2 = translate_rreg (SD_, RD2);
2616 temp = ((signed64)(signed32)State.regs[srcreg1]
2617 * (signed64)(signed32)State.regs[srcreg2]);
2618 State.regs[dstreg2] = temp & 0xffffffff;
2619 State.regs[dstreg1] = (temp & 0xffffffff00000000LL) >> 32;
2621 z = (State.regs[dstreg1] == 0) && (State.regs[dstreg2] == 0);
2622 n = (State.regs[dstreg1] & 0x80000000);
2624 PSW &= ~(PSW_Z | PSW_N);
2625 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2628 // 1111 1011 1011 1101 Rm Rn Rd1 Rd2; mulu Rm,Rn,Rd1,Rd2
2629 8.0xfb+8.0xbd+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mulu
2633 int srcreg1, srcreg2, dstreg1, dstreg2;
2634 signed long long temp;
2638 srcreg1 = translate_rreg (SD_, RM2);
2639 srcreg2 = translate_rreg (SD_, RN0);
2640 dstreg1 = translate_rreg (SD_, RD0);
2641 dstreg2 = translate_rreg (SD_, RD2);
2643 temp = ((unsigned64)State.regs[srcreg1]
2644 * (unsigned64)State.regs[srcreg2]);
2645 State.regs[dstreg2] = temp & 0xffffffff;
2646 State.regs[dstreg1] = (temp & 0xffffffff00000000LL) >> 32;
2648 z = (State.regs[dstreg1] == 0) && (State.regs[dstreg2] == 0);
2649 n = (State.regs[dstreg1] & 0x80000000);
2651 PSW &= ~(PSW_Z | PSW_N);
2652 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2655 // 1111 1011 0000 1110 Rn 0000 abs8 ; mov (abs8),Rn
2656 8.0xfb+8.0x0e+4.RN2,4.0x0+8.IMM8:D2p:::mov
2663 dstreg = translate_rreg (SD_, RN2);
2664 State.regs[dstreg] = load_word (IMM8);
2667 // 1111 1011 0001 1110 Rm 0000 abs8 ; mov Rn,(abs8)
2668 8.0xfb+8.0x1e+4.RM2,4.0x0+8.IMM8:D2q:::mov
2675 srcreg = translate_rreg (SD_, RM2);
2676 store_word (IMM8, State.regs[srcreg]);
2679 // 1111 1011 0010 1110 Rn 0000 abs8 ; movbu (abs8),Rn
2680 8.0xfb+8.0x2e+4.RN2,4.0x0+8.IMM8:D2p:::movbu
2687 dstreg = translate_rreg (SD_, RN2);
2688 State.regs[dstreg] = load_byte (IMM8);
2691 // 1111 1011 0011 1110 Rm 0000 abs8 ; movbu Rn,(abs8)
2692 8.0xfb+8.0x3e+4.RM2,4.0x0+8.IMM8:D2q:::movbu
2699 srcreg = translate_rreg (SD_, RM2);
2700 store_byte (IMM8, State.regs[srcreg]);
2703 // 1111 1011 0100 1110 Rn 0000 abs8 ; movhu (abs8),Rn
2704 8.0xfb+8.0x4e+4.RN2,4.0x0+8.IMM8:D2p:::movhu
2711 dstreg = translate_rreg (SD_, RN2);
2712 State.regs[dstreg] = load_half (IMM8);
2715 // 1111 1011 0101 1110 Rm 0000 abs8 ; movhu Rn,(abs8)
2716 8.0xfb+8.0x5e+4.RM2,4.0x0+8.IMM8:D2q:::movhu
2723 srcreg = translate_rreg (SD_, RM2);
2724 store_half (IMM8, State.regs[srcreg]);
2727 // 1111 1011 1000 1110 Ri Rm Rn; mov (Ri,Rm),Rn
2728 8.0xfb+8.0x8e+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::mov
2732 int srcreg1, srcreg2, dstreg;
2735 srcreg1 = translate_rreg (SD_, RM0);
2736 srcreg1 = translate_rreg (SD_, RI0);
2737 dstreg = translate_rreg (SD_, RN0);
2738 State.regs[dstreg] = load_word (State.regs[srcreg1] + State.regs[srcreg2]);
2741 // 1111 1011 1001 1110 Ri Rm Rn; mov Rn,(Ri,Rm)
2742 8.0xfb+8.0x9e+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::mov
2746 int srcreg, dstreg1, dstreg2;
2749 srcreg = translate_rreg (SD_, RM0);
2750 dstreg1 = translate_rreg (SD_, RI0);
2751 dstreg2 = translate_rreg (SD_, RN0);
2752 store_word (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
2755 // 1111 1011 1010 1110 Ri Rm Rn; movbu (Ri,Rm),Rn
2756 8.0xfb+8.0xae+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movbu
2760 int srcreg1, srcreg2, dstreg;
2763 srcreg1 = translate_rreg (SD_, RM0);
2764 srcreg1 = translate_rreg (SD_, RI0);
2765 dstreg = translate_rreg (SD_, RN0);
2766 State.regs[dstreg] = load_byte (State.regs[srcreg1] + State.regs[srcreg2]);
2769 // 1111 1011 1011 1110 Ri Rm Rn; movbu Rn,(Ri,Rm)
2770 8.0xfb+8.0xbe+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movbu
2774 int srcreg, dstreg1, dstreg2;
2777 srcreg = translate_rreg (SD_, RM0);
2778 dstreg1 = translate_rreg (SD_, RI0);
2779 dstreg2 = translate_rreg (SD_, RN0);
2780 store_byte (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
2783 // 1111 1011 1100 1110 Ri Rm Rn; movhu (Ri,Rm),Rn
2784 8.0xfb+8.0xce+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movhu
2788 int srcreg1, srcreg2, dstreg;
2791 srcreg1 = translate_rreg (SD_, RM0);
2792 srcreg1 = translate_rreg (SD_, RI0);
2793 dstreg = translate_rreg (SD_, RN0);
2794 State.regs[dstreg] = load_half (State.regs[srcreg1] + State.regs[srcreg2]);
2797 // 1111 1011 1101 1110 Ri Rm Rn; movhu Rn,(Ri,Rm)
2798 8.0xfb+8.0xde+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movhu
2802 int srcreg, dstreg1, dstreg2;
2805 srcreg = translate_rreg (SD_, RM0);
2806 dstreg1 = translate_rreg (SD_, RI0);
2807 dstreg2 = translate_rreg (SD_, RN0);
2808 store_half (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
2811 // 1111 1011 0000 1111 Rm Rn Rd1 Rd2; mac Rm,Rn,Rd1,Rd2
2812 8.0xfb+8.0x0f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mac
2816 int srcreg1, srcreg2, dstreg1, dstreg2;
2817 signed long long temp;
2822 srcreg1 = translate_rreg (SD_, RM2);
2823 srcreg2 = translate_rreg (SD_, RN0);
2824 dstreg1 = translate_rreg (SD_, RD0);
2825 dstreg2 = translate_rreg (SD_, RD2);
2827 temp = ((signed64)(signed32)State.regs[srcreg1]
2828 * (signed64)(signed32)State.regs[srcreg2]);
2830 sum = State.regs[dstreg2] + (temp & 0xffffffff);
2831 c = (sum < State.regs[dstreg2]) || (sum < (temp & 0xffffffff));
2832 State.regs[dstreg2] = sum;
2835 sum = State.regs[dstreg1] + temp + c;
2836 v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
2837 && (temp & 0x80000000) != (sum & 0x80000000));
2838 State.regs[dstreg1] = sum;
2841 State.regs[REG_MCVF] = 1;
2843 PSW |= (( v ? PSW_V : 0));
2847 // 1111 1011 0001 1111 Rm Rn Rd1 Rd2; macu Rm,Rn,Rd1,Rd2
2848 8.0xfb+8.0x1f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::macu
2852 int srcreg1, srcreg2, dstreg1, dstreg2;
2853 signed long long temp;
2858 srcreg1 = translate_rreg (SD_, RM2);
2859 srcreg2 = translate_rreg (SD_, RN0);
2860 dstreg1 = translate_rreg (SD_, RD0);
2861 dstreg2 = translate_rreg (SD_, RD2);
2863 temp = ((unsigned64)State.regs[srcreg1]
2864 * (unsigned64)State.regs[srcreg2]);
2866 sum = State.regs[dstreg2] + (temp & 0xffffffff);
2867 c = (sum < State.regs[dstreg2]) || (sum < (temp & 0xffffffff));
2868 State.regs[dstreg2] = sum;
2871 sum = State.regs[dstreg1] + temp + c;
2872 v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
2873 && (temp & 0x80000000) != (sum & 0x80000000));
2874 State.regs[dstreg1] = sum;
2877 State.regs[REG_MCVF] = 1;
2879 PSW |= (( v ? PSW_V : 0));
2883 // 1111 1011 0010 1111 Rm Rn Rd1; macb Rm,Rn,Rd1
2884 8.0xfb+8.0x2f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macb
2888 int srcreg1, srcreg2, dstreg;
2893 srcreg1 = translate_rreg (SD_, RM2);
2894 srcreg2 = translate_rreg (SD_, RN0);
2895 dstreg = translate_rreg (SD_, RD0);
2897 temp = ((signed32)(State.regs[srcreg2] & 0xff)
2898 * (signed32)(State.regs[srcreg1] & 0xff));
2899 sum = State.regs[dstreg] + temp;
2900 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2901 && (temp & 0x80000000) != (sum & 0x80000000));
2902 State.regs[dstreg] = sum;
2905 State.regs[REG_MCVF] = 1;
2907 PSW |= ((v ? PSW_V : 0));
2911 // 1111 1011 0011 1111 Rm Rn Rd1; macbu Rm,Rn,Rd1
2912 8.0xfb+8.0x3f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macbu
2916 int srcreg1, srcreg2, dstreg;
2921 srcreg1 = translate_rreg (SD_, RM2);
2922 srcreg2 = translate_rreg (SD_, RN0);
2923 dstreg = translate_rreg (SD_, RD0);
2925 temp = ((unsigned32)(State.regs[srcreg2] & 0xff)
2926 * (unsigned32)(State.regs[srcreg1] & 0xff));
2927 sum = State.regs[dstreg] + temp;
2928 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2929 && (temp & 0x80000000) != (sum & 0x80000000));
2930 State.regs[dstreg] = sum;
2933 State.regs[REG_MCVF] = 1;
2935 PSW |= ((v ? PSW_V : 0));
2939 // 1111 1011 0100 1111 Rm Rn Rd1; mach Rm,Rn,Rd1,Rd2
2940 8.0xfb+8.0x4f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mach
2944 int srcreg1, srcreg2, dstreg1, dstreg2;
2945 long long temp, sum;
2949 srcreg1 = translate_rreg (SD_, RM2);
2950 srcreg2 = translate_rreg (SD_, RN0);
2951 dstreg1 = translate_rreg (SD_, RD0);
2952 dstreg2 = translate_rreg (SD_, RD0);
2954 temp = ((signed32)(State.regs[srcreg2] & 0xffff)
2955 * (signed32)(State.regs[srcreg1] & 0xffff));
2956 State.regs[dstreg2] += (temp & 0xffffffff);
2957 sum = State.regs[dstreg1] + ((temp >> 32) & 0xffffffff);
2958 v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
2959 && (temp & 0x80000000) != (sum & 0x80000000));
2960 State.regs[dstreg1] = sum;
2963 State.regs[REG_MCVF] = 1;
2965 PSW |= ((v ? PSW_V : 0));
2969 // 1111 1011 0101 1111 Rm Rn Rd1; machu Rm,Rn,Rd1,Rd2
2970 8.0xfb+8.0x5f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::machu
2974 int srcreg1, srcreg2, dstreg1, dstreg2;
2975 long long temp, sum;
2979 srcreg1 = translate_rreg (SD_, RM2);
2980 srcreg2 = translate_rreg (SD_, RN0);
2981 dstreg1 = translate_rreg (SD_, RD0);
2982 dstreg2 = translate_rreg (SD_, RD0);
2984 temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
2985 * (unsigned32)(State.regs[srcreg1] & 0xffff));
2986 State.regs[dstreg2] += (temp & 0xffffffff);
2987 sum = State.regs[dstreg1] + ((temp >> 32) & 0xffffffff);
2988 v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
2989 && (temp & 0x80000000) != (sum & 0x80000000));
2990 State.regs[dstreg1] = sum;
2993 State.regs[REG_MCVF] = 1;
2995 PSW |= ((v ? PSW_V : 0));
2999 // 1111 1011 0110 1111 Rm Rn Rd1; dmach Rm,Rn,Rd1
3000 8.0xfb+8.0x6f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmach
3004 int srcreg1, srcreg2, dstreg;
3005 long temp, temp2, sum;
3009 srcreg1 = translate_rreg (SD_, RM2);
3010 srcreg2 = translate_rreg (SD_, RN0);
3011 dstreg = translate_rreg (SD_, RD0);
3013 temp = ((signed32)(State.regs[srcreg2] & 0xffff)
3014 * (signed32)(State.regs[srcreg1] & 0xffff));
3015 temp2 = ((signed32)((State.regs[srcreg1] >> 16) & 0xffff)
3016 * (signed32)((State.regs[srcreg2] >> 16) & 0xffff));
3017 sum = temp + temp2 + State.regs[dstreg];
3018 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
3019 && (temp & 0x80000000) != (sum & 0x80000000));
3020 State.regs[dstreg] = sum;
3023 State.regs[REG_MCVF] = 1;
3025 PSW |= ((v ? PSW_V : 0));
3029 // 1111 1011 0111 1111 Rm Rn Rd1; dmachu Rm,Rn,Rd1
3030 8.0xfb+8.0x7f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmachu
3034 int srcreg1, srcreg2, dstreg;
3035 long temp, temp2, sum;
3039 srcreg1 = translate_rreg (SD_, RM2);
3040 srcreg2 = translate_rreg (SD_, RN0);
3041 dstreg = translate_rreg (SD_, RD0);
3043 temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
3044 * (unsigned32)(State.regs[srcreg1] & 0xffff));
3045 temp2 = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
3046 * (unsigned32)((State.regs[srcreg2] >> 16) & 0xffff));
3047 sum = temp + temp2 + State.regs[dstreg];
3048 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
3049 && (temp & 0x80000000) != (sum & 0x80000000));
3050 State.regs[dstreg] = sum;
3053 State.regs[REG_MCVF] = 1;
3055 PSW |= ((v ? PSW_V : 0));
3059 // 1111 1011 1000 1111 Rm Rn Rd1 Rd2; dmulh Rm,Rn,Rd1,Rd2
3060 8.0xfb+8.0x8f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::dmulh
3064 int srcreg1, srcreg2, dstreg1, dstreg2;
3065 signed long long temp;
3068 srcreg1 = translate_rreg (SD_, RM2);
3069 srcreg2 = translate_rreg (SD_, RN0);
3070 dstreg1 = translate_rreg (SD_, RD0);
3071 dstreg2 = translate_rreg (SD_, RD2);
3073 temp = ((signed32)(State.regs[srcreg1] & 0xffff)
3074 * (signed32)(State.regs[srcreg1] & 0xffff));
3075 State.regs[dstreg2] = temp;
3076 temp = ((signed32)((State.regs[srcreg1] >> 16) & 0xffff)
3077 * (signed32)((State.regs[srcreg1] >>16) & 0xffff));
3078 State.regs[dstreg1] = temp;
3081 // 1111 1011 1001 1111 Rm Rn Rd1 Rd2; dmulhu Rm,Rn,Rd1,Rd2
3082 8.0xfb+8.0x9f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::dmulhu
3086 int srcreg1, srcreg2, dstreg1, dstreg2;
3087 signed long long temp;
3090 srcreg1 = translate_rreg (SD_, RM2);
3091 srcreg2 = translate_rreg (SD_, RN0);
3092 dstreg1 = translate_rreg (SD_, RD0);
3093 dstreg2 = translate_rreg (SD_, RD2);
3095 temp = ((unsigned32)(State.regs[srcreg1] & 0xffff)
3096 * (unsigned32)(State.regs[srcreg1] & 0xffff));
3097 State.regs[dstreg2] = temp;
3098 temp = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
3099 * (unsigned32)((State.regs[srcreg1] >>16) & 0xffff));
3100 State.regs[dstreg1] = temp;
3103 // 1111 1011 1010 1111 Rm Rn; sat24 Rm,Rn
3104 8.0xfb+8.0xaf+4.RM2,4.RN0+8.0x0:D2:::sat24
3112 srcreg = translate_rreg (SD_, RM2);
3113 dstreg = translate_rreg (SD_, RN0);
3115 value = State.regs[srcreg];
3117 if (value >= 0x7fffff)
3118 State.regs[dstreg] = 0x7fffff;
3119 else if (value <= 0xff800000)
3120 State.regs[dstreg] = 0xff800000;
3122 State.regs[dstreg] = value;
3124 n = (State.regs[dstreg] & 0x800000) != 0;
3125 z = (State.regs[dstreg] == 0);
3126 PSW &= ~(PSW_Z | PSW_N);
3127 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3130 // 1111 1011 1111 1111 Rm Rn Rd1; bsch Rm,Rn,Rd1
3131 8.0xfb+8.0xff+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::bsch
3136 int srcreg1, srcreg2, dstreg;
3140 srcreg1 = translate_rreg (SD_, RM2);
3141 srcreg2 = translate_rreg (SD_, RN0);
3142 dstreg = translate_rreg (SD_, RD0);
3144 temp = State.regs[srcreg1];
3145 start = (State.regs[srcreg2] & 0x1f) - 1;
3149 for (i = start; i >= 0; i--)
3151 if (temp & (1 << i))
3154 State.regs[dstreg] = i;
3162 State.regs[dstreg] = 0;
3165 PSW |= (c ? PSW_C : 0);
3168 // 1111 1101 0000 1000 Rn Rn IMM32; mov imm24,Rn
3169 8.0xfd+8.0x08+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::mov
3176 dstreg = translate_rreg (SD_, RN0);
3177 State.regs[dstreg] = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3180 // 1111 1101 0001 1000 Rn Rn IMM32; movu imm24,Rn
3181 8.0xfd+8.0x18+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4k:::movu
3188 dstreg = translate_rreg (SD_, RN0);
3189 State.regs[dstreg] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff;
3192 // 1111 1101 0111 1000 Rn Rn IMM32; add imm24,Rn
3193 8.0xfd+8.0x78+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4c:::add
3200 dstreg = translate_rreg (SD_, RN0);
3201 genericAdd (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), dstreg);
3204 // 1111 1101 1000 1000 Rn Rn IMM32; addc imm24,Rn
3205 8.0xfd+8.0x88+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::addc
3209 int dstreg, z, n, c, v;
3210 unsigned long sum, imm, reg2;
3213 dstreg = translate_rreg (SD_, RN0);
3215 imm = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3216 reg2 = State.regs[dstreg];
3217 sum = imm + reg2 + ((PSW & PSW_C) != 0);
3218 State.regs[dstreg] = sum;
3220 z = ((PSW & PSW_Z) != 0) && (sum == 0);
3221 n = (sum & 0x80000000);
3222 c = (sum < imm) || (sum < reg2);
3223 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
3224 && (reg2 & 0x80000000) != (sum & 0x80000000));
3226 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3227 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3228 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3231 // 1111 1101 1001 1000 Rn Rn IMM32; sub imm24,Rn
3232 8.0xfd+8.0x98+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::sub
3239 dstreg = translate_rreg (SD_, RN0);
3240 genericSub (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), dstreg);
3243 // 1111 1101 1010 1000 Rn Rn IMM32; subc imm24,Rn
3244 8.0xfd+8.0xa8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::subc
3248 int dstreg, z, n, c, v;
3249 unsigned long difference, imm, reg2;
3252 dstreg = translate_rreg (SD_, RN0);
3254 imm = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3255 reg2 = State.regs[dstreg];
3256 difference = reg2 - imm - ((PSW & PSW_C) != 0);
3257 State.regs[dstreg] = difference;
3259 z = ((PSW & PSW_Z) != 0) && (difference == 0);
3260 n = (difference & 0x80000000);
3262 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
3263 && (reg2 & 0x80000000) != (difference & 0x80000000));
3265 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3266 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3267 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3270 // 1111 1101 1101 1000 Rn Rn IMM32; cmp imm24,Rn
3271 8.0xfd+8.0xd8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::cmp
3278 srcreg = translate_rreg (SD_, RN0);
3279 genericCmp (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), State.regs[srcreg]);
3282 // 1111 1101 1111 1000 XRn XRn IMM32; mov imm24,XRn
3283 8.0xfd+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM24A+8.IMM24B+8.IMM24C:D4o:::mov
3290 dstreg = translate_xreg (SD_, XRN0);
3292 State.regs[dstreg] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff;
3295 // 1111 1101 0000 1001 Rn Rn IMM24; and imm24,Rn
3296 8.0xfd+8.0x09+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::and
3304 dstreg = translate_rreg (SD_, RN0);
3306 State.regs[dstreg] &= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
3307 z = (State.regs[dstreg] == 0);
3308 n = (State.regs[dstreg] & 0x80000000) != 0;
3309 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3310 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3313 // 1111 1101 0001 1001 Rn Rn IMM24; or imm24,Rn
3314 8.0xfd+8.0x19+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::or
3322 dstreg = translate_rreg (SD_, RN0);
3324 State.regs[dstreg] |= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
3325 z = (State.regs[dstreg] == 0);
3326 n = (State.regs[dstreg] & 0x80000000) != 0;
3327 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3328 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3331 // 1111 1101 0010 1001 Rn Rn IMM24; xor imm24,Rn
3332 8.0xfd+8.0x29+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::xor
3340 dstreg = translate_rreg (SD_, RN0);
3342 State.regs[dstreg] ^= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
3343 z = (State.regs[dstreg] == 0);
3344 n = (State.regs[dstreg] & 0x80000000) != 0;
3345 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3346 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3349 // 1111 1101 0100 1001 Rn Rn IMM24; asr imm24,Rn
3350 8.0xfd+8.0x49+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asr
3359 dstreg = translate_rreg (SD_, RN0);
3361 temp = State.regs[dstreg];
3363 temp >>= (FETCH24 (IMM24A, IMM24B, IMM24C));
3364 State.regs[dstreg] = temp;
3365 z = (State.regs[dstreg] == 0);
3366 n = (State.regs[dstreg] & 0x80000000) != 0;
3367 PSW &= ~(PSW_Z | PSW_N | PSW_C);
3368 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
3372 // 1111 1101 0101 1001 Rn Rn IMM24; lsr imm24,Rn
3373 8.0xfd+8.0x59+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::lsr
3381 dstreg = translate_rreg (SD_, RN0);
3383 c = State.regs[dstreg] & 1;
3384 State.regs[dstreg] >>= (FETCH24 (IMM24A, IMM24B, IMM24C));
3385 z = (State.regs[dstreg] == 0);
3386 n = (State.regs[dstreg] & 0x80000000) != 0;
3387 PSW &= ~(PSW_Z | PSW_N | PSW_C);
3388 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
3391 // 1111 1101 0110 1001 Rn Rn IMM24; asl imm24,Rn
3392 8.0xfd+8.0x69+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asl
3400 dstreg = translate_rreg (SD_, RN0);
3402 State.regs[dstreg] <<= (FETCH24 (IMM24A, IMM24B, IMM24C));
3403 z = (State.regs[dstreg] == 0);
3404 n = (State.regs[dstreg] & 0x80000000) != 0;
3405 PSW &= ~(PSW_Z | PSW_N);
3406 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3409 // 1111 1101 1010 1001 Rn Rn IMM24; mul imm24,Rn
3410 8.0xfd+8.0xa9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mul
3415 unsigned long long temp;
3419 dstreg = translate_rreg (SD_, RN0);
3421 temp = ((signed64)(signed32)State.regs[dstreg]
3422 * (signed64)(signed32)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)));
3423 State.regs[dstreg] = temp & 0xffffffff;
3424 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
3425 z = (State.regs[dstreg] == 0);
3426 n = (State.regs[dstreg] & 0x80000000) != 0;
3427 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3428 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3431 // 1111 1101 1011 1001 Rn Rn IMM24; mulu imm24,Rn
3432 8.0xfd+8.0xb9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mulu
3437 unsigned long long temp;
3441 dstreg = translate_rreg (SD_, RN0);
3443 temp = ((unsigned64)State.regs[dstreg]
3444 * (unsigned64)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)));
3445 State.regs[dstreg] = temp & 0xffffffff;
3446 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
3447 z = (State.regs[dstreg] == 0);
3448 n = (State.regs[dstreg] & 0x80000000) != 0;
3449 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3450 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3453 // 1111 1101 1110 1001 Rn Rn IMM24; btst imm24,,Rn
3454 8.0xfd+8.0xe9+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::btst
3461 srcreg = translate_rreg (SD_, RN0);
3462 genericBtst (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3465 // 1111 1101 0000 1010 Rn Rm IMM24; mov (d24,Rm),Rn
3466 8.0xfd+8.0x0a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::mov
3473 srcreg = translate_rreg (SD_, RM0);
3474 dstreg = translate_rreg (SD_, RN2);
3475 State.regs[dstreg] = load_word (State.regs[srcreg]
3476 + EXTEND24 (FETCH24 (IMM24A,
3480 // 1111 1101 0001 1010 Rm Rn IMM24; mov Rm,(d24,Rn)
3481 8.0xfd+8.0x1a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::mov
3488 srcreg = translate_rreg (SD_, RM2);
3489 dstreg = translate_rreg (SD_, RN0);
3490 store_word (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3491 State.regs[srcreg]);
3494 // 1111 1101 0010 1010 Rn Rm IMM24; movbu (d24,Rm),Rn
3495 8.0xfd+8.0x2a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movbu
3502 srcreg = translate_rreg (SD_, RM0);
3503 dstreg = translate_rreg (SD_, RN2);
3504 State.regs[dstreg] = load_byte (State.regs[srcreg]
3505 + EXTEND24 (FETCH24 (IMM24A,
3509 // 1111 1101 0011 1010 Rm Rn IMM24; movbu Rm,(d24,Rn)
3510 8.0xfd+8.0x3a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movbu
3517 srcreg = translate_rreg (SD_, RM2);
3518 dstreg = translate_rreg (SD_, RN0);
3519 store_byte (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3520 State.regs[srcreg]);
3523 // 1111 1101 0100 1010 Rn Rm IMM24; movhu (d24,Rm),Rn
3524 8.0xfd+8.0x4a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movhu
3531 srcreg = translate_rreg (SD_, RM0);
3532 dstreg = translate_rreg (SD_, RN2);
3533 State.regs[dstreg] = load_half (State.regs[srcreg]
3534 + EXTEND24 (FETCH24 (IMM24A,
3538 // 1111 1101 0101 1010 Rm Rn IMM24; movhu Rm,(d24,Rn)
3539 8.0xfd+8.0x5a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movhu
3546 srcreg = translate_rreg (SD_, RM2);
3547 dstreg = translate_rreg (SD_, RN0);
3548 store_half (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3549 State.regs[srcreg]);
3552 // 1111 1101 0110 1010 Rn Rm IMM24; mov (d24,Rm+),Rn
3553 8.0xfd+8.0x6a+4.RN2,4.RM0!RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::mov
3560 srcreg = translate_rreg (SD_, RM0);
3561 dstreg = translate_rreg (SD_, RN2);
3562 State.regs[dstreg] = load_word (State.regs[srcreg]);
3563 State.regs[srcreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3566 // 1111 1101 0111 1010 Rm Rn IMM24; mov Rm,(d24,Rn+)
3567 8.0xfd+8.0x7a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mov
3574 srcreg = translate_rreg (SD_, RM2);
3575 dstreg = translate_rreg (SD_, RN0);
3576 store_word (State.regs[dstreg], State.regs[srcreg]);
3577 State.regs[dstreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3581 // 1111 1101 1000 1010 Rn 0000 IMM24; mov (d24,sp),Rn
3582 8.0xfd+8.0x8a+4.RN2,4.0x0+IMM24A+8.IMM24B+8.IMM24C:D4r:::mov
3589 dstreg = translate_rreg (SD_, RN2);
3590 State.regs[dstreg] = load_word (State.regs[REG_SP]
3591 + EXTEND24 (FETCH24 (IMM24A,
3595 // 1111 1101 1001 1010 Rm 0000 IMM24; mov Rm,(d24,sp)
3596 8.0xfd+8.0x9a+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::mov
3603 srcreg = translate_rreg (SD_, RM2);
3604 store_word (State.regs[REG_SP] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3605 State.regs[srcreg]);
3608 // 1111 1101 1010 1010 Rn 0000 IMM24; movbu (d24,Rm),Rn
3609 8.0xfd+8.0xaa+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movbu
3616 dstreg = translate_rreg (SD_, RN2);
3617 State.regs[dstreg] = load_byte (State.regs[REG_SP]
3618 + EXTEND24 (FETCH24 (IMM24A,
3622 // 1111 1101 1011 1010 Rm 0000 IMM24; movbu Rm,(d24,sp)
3623 8.0xfd+8.0xba+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movbu
3630 srcreg = translate_rreg (SD_, RM2);
3631 store_byte (State.regs[REG_SP] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3632 State.regs[srcreg]);
3635 // 1111 1101 1100 1010 Rn 0000 IMM24; movhu (d24,sp),Rn
3636 8.0xfd+8.0xca+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movhu
3643 dstreg = translate_rreg (SD_, RN2);
3644 State.regs[dstreg] = load_half (State.regs[REG_SP]
3645 + EXTEND24 (FETCH24 (IMM24A,
3649 // 1111 1101 1101 1010 Rm Rn IMM24; movhu Rm,(d24,sp)
3650 8.0xfd+8.0xda+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movhu
3657 srcreg = translate_rreg (SD_, RM2);
3658 store_half (State.regs[REG_SP] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3659 State.regs[srcreg]);
3662 // 1111 1101 1110 1010 Rn Rm IMM24; movhu (d24,Rm+),Rn
3663 8.0xfd+8.0xea+4.RN2,4.RM0!RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::movhu
3670 srcreg = translate_rreg (SD_, RM0);
3671 dstreg = translate_rreg (SD_, RN2);
3672 State.regs[dstreg] = load_half (State.regs[srcreg]);
3673 State.regs[dstreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3676 // 1111 1101 1111 1010 Rm Rn IMM24; movhu Rm,(d24,Rn+)
3677 8.0xfd+8.0xfa+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::movhu
3684 srcreg = translate_rreg (SD_, RM2);
3685 dstreg = translate_rreg (SD_, RN0);
3686 store_half (State.regs[dstreg], State.regs[srcreg]);
3687 State.regs[srcreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3690 // 1111 1101 0000 1011 Rn IMM24; mac imm24,Rn
3691 8.0xfd+8.0x0b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mac
3696 long long temp, sum;
3700 srcreg = translate_rreg (SD_, RN2);
3702 temp = ((signed64)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C))
3703 * (signed64)State.regs[srcreg]);
3704 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3705 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3706 State.regs[REG_MCRL] = sum;
3709 sum = State.regs[REG_MCRH] + temp + c;
3710 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3711 && (temp & 0x80000000) != (sum & 0x80000000));
3712 State.regs[REG_MCRH] = sum;
3714 State.regs[REG_MCVF] = 1;
3717 // 1111 1101 0001 1011 Rn IMM24; macu imm24,Rn
3718 8.0xfd+8.0x1b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macu
3723 long long temp, sum;
3727 srcreg = translate_rreg (SD_, RN2);
3729 temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C))
3730 * (unsigned64)State.regs[srcreg]);
3731 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3732 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3733 State.regs[REG_MCRL] = sum;
3736 sum = State.regs[REG_MCRH] + temp + c;
3737 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3738 && (temp & 0x80000000) != (sum & 0x80000000));
3739 State.regs[REG_MCRH] = sum;
3741 State.regs[REG_MCVF] = 1;
3744 // 1111 1101 0010 1011 Rn IMM24; macb imm24,Rn
3745 8.0xfd+8.0x2b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macb
3750 long long temp, sum;
3754 srcreg = translate_rreg (SD_, RN2);
3756 temp = ((signed64)EXTEND8 (FETCH24 (IMM24A, IMM24B, IMM24C))
3757 * (signed64)State.regs[srcreg] & 0xff);
3758 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3759 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3760 State.regs[REG_MCRL] = sum;
3763 sum = State.regs[REG_MCRH] + temp + c;
3764 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3765 && (temp & 0x80000000) != (sum & 0x80000000));
3766 State.regs[REG_MCRH] = sum;
3768 State.regs[REG_MCVF] = 1;
3771 // 1111 1101 0011 1011 Rn IMM24; macbu imm24,Rn
3772 8.0xfd+8.0x3b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macbu
3777 long long temp, sum;
3781 srcreg = translate_rreg (SD_, RN2);
3783 temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C))
3784 * (unsigned64)State.regs[srcreg] & 0xff);
3785 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3786 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3787 State.regs[REG_MCRL] = sum;
3790 sum = State.regs[REG_MCRH] + temp + c;
3791 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3792 && (temp & 0x80000000) != (sum & 0x80000000));
3793 State.regs[REG_MCRH] = sum;
3795 State.regs[REG_MCVF] = 1;
3798 // 1111 1101 0100 1011 Rn IMM24; mach imm24,Rn
3799 8.0xfd+8.0x4b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mach
3804 long long temp, sum;
3808 srcreg = translate_rreg (SD_, RN2);
3810 temp = ((signed64)EXTEND16 (FETCH24 (IMM24A, IMM24B, IMM24C))
3811 * (signed64)State.regs[srcreg] & 0xffff);
3812 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3813 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3814 State.regs[REG_MCRL] = sum;
3817 sum = State.regs[REG_MCRH] + temp + c;
3818 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3819 && (temp & 0x80000000) != (sum & 0x80000000));
3820 State.regs[REG_MCRH] = sum;
3822 State.regs[REG_MCVF] = 1;
3825 // 1111 1101 0101 1011 Rn IMM24; machu imm24,Rn
3826 8.0xfd+8.0x5b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::machu
3831 long long temp, sum;
3835 srcreg = translate_rreg (SD_, RN2);
3837 temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffff)
3838 * (unsigned64)State.regs[srcreg] & 0xffff);
3839 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3840 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3841 State.regs[REG_MCRL] = sum;
3844 sum = State.regs[REG_MCRH] + temp + c;
3845 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3846 && (temp & 0x80000000) != (sum & 0x80000000));
3847 State.regs[REG_MCRH] = sum;
3849 State.regs[REG_MCVF] = 1;
3852 // 1111 1101 0000 1110 Rn 0000 ABS24; mov (abs24),Rn
3853 8.0xfd+8.0x0e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::mov
3860 dstreg = translate_rreg (SD_, RN2);
3861 State.regs[dstreg] = load_word (FETCH24 (IMM24A, IMM24B, IMM24C));
3864 // 1111 1101 0001 1110 Rm 0000 ABS24; mov Rm,(abs24)
3865 8.0xfd+8.0x1e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4v:::mov
3872 srcreg = translate_rreg (SD_, RM2);
3873 store_word (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3877 // 1111 1101 0010 1110 Rn 0000 ABS24; movbu (abs24),Rn
3878 8.0xfd+8.0x2e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movbu
3885 dstreg = translate_rreg (SD_, RN2);
3886 State.regs[dstreg] = load_byte (FETCH24 (IMM24A, IMM24B, IMM24C));
3889 // 1111 1101 0011 1110 Rm 0000 ABS24; movbu Rm,(abs24)
3890 8.0xfd+8.0x3e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movbu
3897 srcreg = translate_rreg (SD_, RM2);
3898 store_byte (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3902 // 1111 1101 0100 1110 Rn 0000 ABS24; movhu (abs24),Rn
3903 8.0xfd+8.0x4e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movhu
3910 dstreg = translate_rreg (SD_, RN2);
3911 State.regs[dstreg] = load_half (FETCH24 (IMM24A, IMM24B, IMM24C));
3914 // 1111 1101 0101 1110 Rm 0000 ABS24; movhu Rm,(abs24)
3915 8.0xfd+8.0x5e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movhu
3922 srcreg = translate_rreg (SD_, RM2);
3923 store_half (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3927 // 1111 1110 0000 1000 Rn Rn IMM32; mov imm32,Rn
3928 8.0xfe+8.0x08+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mov
3935 dstreg = translate_rreg (SD_, RN0);
3936 State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
3939 // 1111 1110 0001 1000 Rn Rn IMM32; movu imm32,Rn
3940 8.0xfe+8.0x18+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movu
3947 dstreg = translate_rreg (SD_, RN0);
3948 State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
3951 // 1111 1110 0111 1000 Rn Rn IMM32; add imm32,Rn
3952 8.0xfe+8.0x78+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::add
3959 dstreg = translate_rreg (SD_, RN0);
3960 genericAdd (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), dstreg);
3963 // 1111 1110 1000 1000 Rn Rn IMM32; addc imm32,Rn
3964 8.0xfe+8.0x88+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::addc
3969 unsigned int imm, reg2, sum;
3973 dstreg = translate_rreg (SD_, RN0);
3975 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
3976 reg2 = State.regs[dstreg];
3977 sum = imm + reg2 + ((PSW & PSW_C) != 0);
3978 State.regs[dstreg] = sum;
3980 z = ((PSW & PSW_Z) != 0) && (sum == 0);
3981 n = (sum & 0x80000000);
3982 c = (sum < imm) || (sum < reg2);
3983 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
3984 && (reg2 & 0x80000000) != (sum & 0x80000000));
3986 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3987 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3988 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3991 // 1111 1110 1001 1000 Rn Rn IMM32; sub imm32,Rn
3992 8.0xfe+8.0x98+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::sub
3999 dstreg = translate_rreg (SD_, RN0);
4000 genericSub (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), dstreg);
4003 // 1111 1110 1010 1000 Rn Rn IMM32; subc imm32,Rn
4004 8.0xfe+8.0xa8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::subc
4009 unsigned int imm, reg2, difference;
4013 dstreg = translate_rreg (SD_, RN0);
4015 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4016 reg2 = State.regs[dstreg];
4017 difference = reg2 - imm - ((PSW & PSW_C) != 0);
4018 State.regs[dstreg] = difference;
4020 z = ((PSW & PSW_Z) != 0) && (difference == 0);
4021 n = (difference & 0x80000000);
4023 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
4024 && (reg2 & 0x80000000) != (difference & 0x80000000));
4026 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4027 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
4028 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
4031 // 1111 1110 0111 1000 Rn Rn IMM32; cmp imm32,Rn
4032 8.0xfe+8.0xd8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::cmp
4039 srcreg = translate_rreg (SD_, RN0);
4040 genericCmp (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4043 // 1111 1110 1111 1000 XRn XRn IMM32; mov imm32,XRn
4044 8.0xfe+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::mov
4051 dstreg = translate_xreg (SD_, XRN0);
4053 State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
4056 // 1111 1110 0000 1001 Rn Rn IMM32; and imm32,Rn
4057 8.0xfe+8.0x09+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::and
4065 dstreg = translate_rreg (SD_, RN0);
4067 State.regs[dstreg] &= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4068 z = (State.regs[dstreg] == 0);
4069 n = (State.regs[dstreg] & 0x80000000) != 0;
4070 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4071 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4074 // 1111 1110 0001 1001 Rn Rn IMM32; or imm32,Rn
4075 8.0xfe+8.0x19+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::or
4083 dstreg = translate_rreg (SD_, RN0);
4085 State.regs[dstreg] |= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4086 z = (State.regs[dstreg] == 0);
4087 n = (State.regs[dstreg] & 0x80000000) != 0;
4088 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4089 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4092 // 1111 1110 0010 1001 Rn Rn IMM32; xor imm32,Rn
4093 8.0xfe+8.0x29+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::xor
4101 dstreg = translate_rreg (SD_, RN0);
4103 State.regs[dstreg] ^= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4104 z = (State.regs[dstreg] == 0);
4105 n = (State.regs[dstreg] & 0x80000000) != 0;
4106 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4107 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4110 // 1111 1110 0100 1001 Rn Rn IMM32; asr imm32,Rn
4111 8.0xfe+8.0x49+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asr
4120 dstreg = translate_rreg (SD_, RN0);
4122 temp = State.regs[dstreg];
4124 temp >>= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4125 State.regs[dstreg] = temp;
4126 z = (State.regs[dstreg] == 0);
4127 n = (State.regs[dstreg] & 0x80000000) != 0;
4128 PSW &= ~(PSW_Z | PSW_N | PSW_C);
4129 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
4132 // 1111 1110 0101 1001 Rn Rn IMM32; lsr imm32,Rn
4133 8.0xfe+8.0x59+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::lsr
4141 dstreg = translate_rreg (SD_, RN0);
4143 c = State.regs[dstreg] & 1;
4144 State.regs[dstreg] >>= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4145 z = (State.regs[dstreg] == 0);
4146 n = (State.regs[dstreg] & 0x80000000) != 0;
4147 PSW &= ~(PSW_Z | PSW_N | PSW_C);
4148 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
4151 // 1111 1110 0110 1001 Rn Rn IMM32; asl imm32,Rn
4152 8.0xfe+8.0x69+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asl
4160 dstreg = translate_rreg (SD_, RN0);
4162 State.regs[dstreg] <<= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4163 z = (State.regs[dstreg] == 0);
4164 n = (State.regs[dstreg] & 0x80000000) != 0;
4165 PSW &= ~(PSW_Z | PSW_N);
4166 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4169 // 1111 1110 1010 1001 Rn Rn IMM32; mul imm32,Rn
4170 8.0xfe+8.0xa9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mul
4175 unsigned long long temp;
4179 dstreg = translate_rreg (SD_, RN0);
4181 temp = ((signed64)(signed32)State.regs[dstreg]
4182 * (signed64)(signed32)(FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)));
4183 State.regs[dstreg] = temp & 0xffffffff;
4184 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
4185 z = (State.regs[dstreg] == 0);
4186 n = (State.regs[dstreg] & 0x80000000) != 0;
4187 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4188 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4191 // 1111 1110 1011 1001 Rn Rn IMM32; mulu imm32,Rn
4192 8.0xfe+8.0xb9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mulu
4197 unsigned long long temp;
4201 dstreg = translate_rreg (SD_, RN0);
4203 temp = ((unsigned64)State.regs[dstreg]
4204 * (unsigned64) (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)));
4205 State.regs[dstreg] = temp & 0xffffffff;
4206 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
4207 z = (State.regs[dstreg] == 0);
4208 n = (State.regs[dstreg] & 0x80000000) != 0;
4209 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4210 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4213 // 1111 1110 1110 1001 Rn Rn IMM32; btst imm32,Rn
4214 8.0xfe+8.0xe9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5a:::btst
4221 srcreg = translate_rreg (SD_, RN0);
4222 genericBtst (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4225 // 1111 1110 0000 1010 Rn Rm IMM32; mov (d32,Rm),Rn
4226 8.0xfe+8.0x0a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::mov
4233 srcreg = translate_rreg (SD_, RM0);
4234 dstreg = translate_rreg (SD_, RN2);
4235 State.regs[dstreg] = load_word (State.regs[srcreg]
4236 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4239 // 1111 1110 0001 1010 Rm Rn IMM32; mov Rm,(d32,Rn)
4240 8.0xfe+8.0x1a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5g:::mov
4247 srcreg = translate_rreg (SD_, RM2);
4248 dstreg = translate_rreg (SD_, RN0);
4249 store_word (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4250 State.regs[srcreg]);
4253 // 1111 1110 0010 1010 Rn Rm IMM32; movbu (d32,Rm),Rn
4254 8.0xfe+8.0x2a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movbu
4261 srcreg = translate_rreg (SD_, RM0);
4262 dstreg = translate_rreg (SD_, RN2);
4263 State.regs[dstreg] = load_byte (State.regs[srcreg]
4264 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4267 // 1111 1110 0011 1010 Rm Rn IMM32; movbu Rm,(d32,Rn)
4268 8.0xfe+8.0x3a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movbu
4275 srcreg = translate_rreg (SD_, RM2);
4276 dstreg = translate_rreg (SD_, RN0);
4277 store_byte (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4278 State.regs[srcreg]);
4281 // 1111 1110 0100 1010 Rn Rm IMM32; movhu (d32,Rm),Rn
4282 8.0xfe+8.0x4a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movhu
4289 srcreg = translate_rreg (SD_, RM0);
4290 dstreg = translate_rreg (SD_, RN2);
4291 State.regs[dstreg] = load_half (State.regs[srcreg]
4292 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4295 // 1111 1110 0101 1010 Rm Rn IMM32; movhu Rm,(d32,Rn)
4296 8.0xfe+8.0x5a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movhu
4303 srcreg = translate_rreg (SD_, RM2);
4304 dstreg = translate_rreg (SD_, RN0);
4305 store_half (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4306 State.regs[srcreg]);
4309 // 1111 1110 0110 1010 Rn Rm IMM32; mov (d32,Rm+),Rn
4310 8.0xfe+8.0x6a+4.RN2,4.RM0!RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::mov
4317 srcreg = translate_rreg (SD_, RM0);
4318 dstreg = translate_rreg (SD_, RN2);
4319 State.regs[dstreg] = load_word (State.regs[srcreg]);
4320 State.regs[srcreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4323 // 1111 1110 0111 1010 Rm Rn IMM32; mov Rm,(d32,Rn+)
4324 8.0xfe+8.0x7a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5z:::mov
4331 srcreg = translate_rreg (SD_, RM2);
4332 dstreg = translate_rreg (SD_, RN0);
4333 store_word (State.regs[dstreg], State.regs[srcreg]);
4334 State.regs[dstreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4338 // 1111 1110 1000 1010 Rn 0000 IMM32; mov (d32,sp),Rn
4339 8.0xfe+8.0x8a+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::mov
4346 dstreg = translate_rreg (SD_, RN2);
4347 State.regs[dstreg] = load_word (State.regs[REG_SP]
4348 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4351 // 1111 1110 1001 1010 Rm 0000 IMM32; mov Rm,(d32,sp)
4352 8.0xfe+8.0x9a+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::mov
4359 srcreg = translate_rreg (SD_, RM2);
4360 store_word (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4361 State.regs[srcreg]);
4364 // 1111 1110 1010 1010 Rn 0000 IMM32; movbu (d32,sp),Rn
4365 8.0xfe+8.0xaa+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movbu
4372 dstreg = translate_rreg (SD_, RN2);
4373 State.regs[dstreg] = load_byte (State.regs[REG_SP]
4374 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4377 // 1111 1110 1011 1010 Rm 0000 IMM32; movbu Rm,(d32,sp)
4378 8.0xfe+8.0xba+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movbu
4385 srcreg = translate_rreg (SD_, RM2);
4386 store_byte (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4387 State.regs[srcreg]);
4390 // 1111 1110 1100 1010 Rn 0000 IMM32; movhu (d32,sp),Rn
4391 8.0xfe+8.0xca+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movhu
4398 dstreg = translate_rreg (SD_, RN2);
4399 State.regs[dstreg] = load_half (State.regs[REG_SP]
4400 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4403 // 1111 1110 1101 1010 Rm 0000 IMM32; movhu Rm,(d32,sp)
4404 8.0xfe+8.0xda+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movhu
4411 srcreg = translate_rreg (SD_, RM2);
4412 store_half (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4413 State.regs[srcreg]);
4417 // 1111 1110 1110 1010 Rn Rm IMM32; movhu (d32,Rm+),Rn
4418 8.0xfe+8.0xea+4.RN2,4.RM0!RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::movhu
4425 srcreg = translate_rreg (SD_, RM0);
4426 dstreg = translate_rreg (SD_, RN2);
4427 State.regs[dstreg] = load_half (State.regs[srcreg]);
4428 State.regs[srcreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4431 // 1111 1110 1111 1010 Rm Rn IMM32; movhu Rm,(d32,Rn+)
4432 8.0xfe+8.0xfa+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::movhu
4439 srcreg = translate_rreg (SD_, RM2);
4440 dstreg = translate_rreg (SD_, RN0);
4441 store_half (State.regs[dstreg], State.regs[srcreg]);
4442 State.regs[dstreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4446 // 1111 1110 0000 1011 Rn Rn IMM32; mac imm32,Rn
4447 8.0xfe+8.0x0b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mac
4452 long long temp, sum;
4456 srcreg = translate_rreg (SD_, RN0);
4457 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4459 temp = ((signed64)(signed32)State.regs[srcreg]
4460 * (signed64)(signed32)imm);
4461 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
4462 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
4463 State.regs[REG_MCRL] = sum;
4466 sum = State.regs[REG_MCRH] + temp + c;
4467 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
4468 && (temp & 0x80000000) != (sum & 0x80000000));
4469 State.regs[REG_MCRH] = sum;
4471 State.regs[REG_MCVF] = 1;
4474 // 1111 1110 0001 1011 Rn Rn IMM32; macu imm32,Rn
4475 8.0xfe+8.0x1b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macu
4480 long long temp, sum;
4484 srcreg = translate_rreg (SD_, RN0);
4485 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4487 temp = ((unsigned64)State.regs[srcreg]
4489 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
4490 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
4491 State.regs[REG_MCRL] = sum;
4494 sum = State.regs[REG_MCRH] + temp + c;
4495 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
4496 && (temp & 0x80000000) != (sum & 0x80000000));
4497 State.regs[REG_MCRH] = sum;
4499 State.regs[REG_MCVF] = 1;
4502 // 1111 1110 0010 1011 Rn Rn IMM32; macb imm32,Rn
4503 8.0xfe+8.0x2b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macb
4512 srcreg = translate_rreg (SD_, RN0);
4513 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4515 temp = ((signed32)(signed8)(State.regs[srcreg] & 0xff)
4516 * (signed32)(signed8)(imm & 0xff));
4517 sum = State.regs[REG_MCRL] + temp;
4518 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
4519 && (temp & 0x80000000) != (sum & 0x80000000));
4520 State.regs[REG_MCRL] = sum;
4522 State.regs[REG_MCVF] = 1;
4525 // 1111 1110 0011 1011 Rn Rn IMM32; macbu imm32,Rn
4526 8.0xfe+8.0x3b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macbu
4535 srcreg = translate_rreg (SD_, RN0);
4536 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4538 temp = ((unsigned32)(State.regs[srcreg] & 0xff)
4539 * (unsigned32)(imm & 0xff));
4540 sum = State.regs[REG_MCRL] + temp;
4541 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
4542 && (temp & 0x80000000) != (sum & 0x80000000));
4543 State.regs[REG_MCRL] = sum;
4545 State.regs[REG_MCVF] = 1;
4548 // 1111 1110 0100 1011 Rn Rn IMM32; mach imm32,Rn
4549 8.0xfe+8.0x4b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mach
4558 srcreg = translate_rreg (SD_, RN0);
4559 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4561 temp = ((signed32)(signed16)(State.regs[srcreg] & 0xffff)
4562 * (signed32)(signed16)(imm & 0xffff));
4563 sum = State.regs[REG_MCRL] + temp;
4564 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
4565 && (temp & 0x80000000) != (sum & 0x80000000));
4566 State.regs[REG_MCRL] = sum;
4568 State.regs[REG_MCVF] = 1;
4571 // 1111 1110 0101 1011 Rn Rn IMM32; machu imm32,Rn
4572 8.0xfe+8.0x5b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::machu
4581 srcreg = translate_rreg (SD_, RN0);
4582 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4584 temp = ((unsigned32)(State.regs[srcreg] & 0xffff)
4585 * (unsigned32)(imm & 0xffff));
4586 sum = State.regs[REG_MCRL] + temp;
4587 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
4588 && (temp & 0x80000000) != (sum & 0x80000000));
4589 State.regs[REG_MCRL] = sum;
4591 State.regs[REG_MCVF] = 1;
4594 // 1111 1110 0110 1011 Rn Rn IMM32; dmach imm32,Rn
4595 8.0xfe+8.0x6b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmach
4600 long temp, temp2, sum;
4604 srcreg = translate_rreg (SD_, RN0);
4605 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4607 temp = ((signed32)(signed16)(State.regs[srcreg] & 0xffff)
4608 * (signed32)(signed16)(imm & 0xffff));
4609 temp2 = ((signed32)(signed16)((State.regs[srcreg] >> 16) & 0xffff)
4610 * (signed32)(signed16)((imm >> 16) & 0xffff));
4611 sum = temp + temp2 + State.regs[REG_MCRL];
4612 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
4613 && (temp & 0x80000000) != (sum & 0x80000000));
4614 State.regs[REG_MCRL] = sum;
4616 State.regs[REG_MCVF] = 1;
4619 // 1111 1110 0111 1011 Rn Rn IMM32; dmachu imm32,Rn
4620 8.0xfe+8.0x7b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmachu
4625 long temp, temp2, sum;
4629 srcreg = translate_rreg (SD_, RN0);
4630 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4632 temp = ((unsigned32)(State.regs[srcreg] & 0xffff)
4633 * (unsigned32)(imm & 0xffff));
4634 temp2 = ((unsigned32)((State.regs[srcreg] >> 16) & 0xffff)
4635 * (unsigned32)((imm >> 16) & 0xffff));
4636 sum = temp + temp2 + State.regs[REG_MCRL];
4637 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
4638 && (temp & 0x80000000) != (sum & 0x80000000));
4639 State.regs[REG_MCRL] = sum;
4641 State.regs[REG_MCVF] = 1;
4644 // 1111 1110 1000 1011 Rn Rn IMM32; dmulh imm32,Rn
4645 8.0xfe+8.0x8b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmulh
4653 dstreg = translate_rreg (SD_, RN0);
4654 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4656 temp = ((signed32)(signed16)(State.regs[dstreg] & 0xffff)
4657 * (signed32)(signed16)(imm & 0xffff));
4658 State.regs[REG_MDRQ] = temp;
4659 temp = ((signed32)(signed16)((State.regs[dstreg] >> 16) & 0xffff)
4660 * (signed32)(signed16)((imm>>16) & 0xffff));
4661 State.regs[dstreg] = temp;
4664 // 1111 1110 1001 1011 Rn Rn IMM32; dmulhu imm32,Rn
4665 8.0xfe+8.0x9b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmulhu
4673 dstreg = translate_rreg (SD_, RN0);
4674 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4676 temp = ((unsigned32)(State.regs[dstreg] & 0xffff)
4677 * (unsigned32)(imm & 0xffff));
4678 State.regs[REG_MDRQ] = temp;
4679 temp = ((unsigned32)((State.regs[dstreg] >> 16) & 0xffff)
4680 * (unsigned32)((imm >>16) & 0xffff));
4681 State.regs[dstreg] = temp;
4684 // 1111 1110 0000 1110 Rn 0000 IMM32; mov (abs32),Rn
4685 8.0xfe+8.0x0e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5h:::mov
4692 dstreg = translate_rreg (SD_, RN2);
4693 State.regs[dstreg] = load_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4696 // 1111 1110 0001 1110 Rm 0000 IMM32; mov Rn,(abs32)
4697 8.0xfe+8.0x1e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::mov
4704 srcreg = translate_rreg (SD_, RM2);
4705 store_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4708 // 1111 1110 0020 1110 Rn 0000 IMM32; movbu (abs32),Rn
4709 8.0xfe+8.0x2e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5i:::movbu
4716 dstreg = translate_rreg (SD_, RN2);
4717 State.regs[dstreg] = load_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4720 // 1111 1110 0011 1110 Rm 0000 IMM32; movbu Rn,(abs32)
4721 8.0xfe+8.0x3e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movbu
4728 srcreg = translate_rreg (SD_, RM2);
4729 store_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4732 // 1111 1110 0100 1110 Rn 0000 IMM32; movhu (abs32),Rn
4733 8.0xfe+8.0x4e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5j:::movhu
4740 dstreg = translate_rreg (SD_, RN2);
4741 State.regs[dstreg] = load_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4744 // 1111 1110 0101 1110 Rm 0000 IMM32; movhu Rn,(abs32)
4745 8.0xfe+8.0x5e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movhu
4752 srcreg = translate_rreg (SD_, RM2);
4753 store_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4756 // 1111 0111 0000 0000 Rm1 Rn1 Rm2 Rn2; add_add Rm1, Rn1, Rm2, Rn2
4757 8.0xf7+8.0x00+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_add
4761 int srcreg1, srcreg2, dstreg1, dstreg2;
4765 srcreg1 = translate_rreg (SD_, RM1);
4766 srcreg2 = translate_rreg (SD_, RM2);
4767 dstreg1 = translate_rreg (SD_, RN1);
4768 dstreg2 = translate_rreg (SD_, RN2);
4770 result1 = State.regs[dstreg1] + State.regs[srcreg1];
4771 State.regs[dstreg2] += State.regs[srcreg2];
4772 State.regs[dstreg1] = result1;
4775 // 1111 0111 0001 0000 Rm1 Rn1 imm4 Rn2; add_add Rm1, Rn1, imm4, Rn2
4776 8.0xf7+8.0x10+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_add
4780 int srcreg1, dstreg1, dstreg2;
4784 srcreg1 = translate_rreg (SD_, RM1);
4785 dstreg1 = translate_rreg (SD_, RN1);
4786 dstreg2 = translate_rreg (SD_, RN2);
4788 result1 = State.regs[dstreg1] + State.regs[srcreg1];
4789 State.regs[dstreg2] += EXTEND4 (IMM4);
4790 State.regs[dstreg1] = result1;
4793 // 1111 0111 0010 0000 Rm1 Rn1 Rm2 Rn2; add_sub Rm1, Rn1, Rm2, Rn2
4794 8.0xf7+8.0x20+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_sub
4798 int srcreg1, srcreg2, dstreg1, dstreg2;
4802 srcreg1 = translate_rreg (SD_, RM1);
4803 srcreg2 = translate_rreg (SD_, RM2);
4804 dstreg1 = translate_rreg (SD_, RN1);
4805 dstreg2 = translate_rreg (SD_, RN2);
4807 result1 = State.regs[dstreg1] + State.regs[srcreg1];
4808 State.regs[dstreg2] -= State.regs[srcreg2];
4809 State.regs[dstreg1] = result1;
4812 // 1111 0111 0011 0000 Rm1 Rn1 imm4 Rn2; add_sub Rm1, Rn1, imm4, Rn2
4813 8.0xf7+8.0x30+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_sub
4817 int srcreg1, dstreg1, dstreg2;
4821 srcreg1 = translate_rreg (SD_, RM1);
4822 dstreg1 = translate_rreg (SD_, RN1);
4823 dstreg2 = translate_rreg (SD_, RN2);
4825 result1 = State.regs[dstreg1] + State.regs[srcreg1];
4826 State.regs[dstreg2] -= EXTEND4 (IMM4);
4827 State.regs[dstreg1] = result1;
4830 // 1111 0111 0100 0000 Rm1 Rn1 Rm2 Rn2; add_cmp Rm1, Rn1, Rm2, Rn2
4831 8.0xf7+8.0x40+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_cmp
4835 int srcreg1, srcreg2, dstreg1, dstreg2;
4838 srcreg1 = translate_rreg (SD_, RM1);
4839 srcreg2 = translate_rreg (SD_, RM2);
4840 dstreg1 = translate_rreg (SD_, RN1);
4841 dstreg2 = translate_rreg (SD_, RN2);
4843 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
4844 State.regs[dstreg1] += State.regs[srcreg1];
4847 // 1111 0111 0101 0000 Rm1 Rn1 imm4 Rn2; add_cmp Rm1, Rn1, imm4, Rn2
4848 8.0xf7+8.0x50+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_cmp
4852 int srcreg1, dstreg1, dstreg2;
4855 srcreg1 = translate_rreg (SD_, RM1);
4856 dstreg1 = translate_rreg (SD_, RN1);
4857 dstreg2 = translate_rreg (SD_, RN2);
4859 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
4860 State.regs[dstreg1] += State.regs[srcreg1];
4863 // 1111 0111 0110 0000 Rm1 Rn1 Rm2 Rn2; add_mov Rm1, Rn1, Rm2, Rn2
4864 8.0xf7+8.0x60+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_mov
4868 int srcreg1, srcreg2, dstreg1, dstreg2;
4872 srcreg1 = translate_rreg (SD_, RM1);
4873 srcreg2 = translate_rreg (SD_, RM2);
4874 dstreg1 = translate_rreg (SD_, RN1);
4875 dstreg2 = translate_rreg (SD_, RN2);
4877 result1 = State.regs[dstreg1] + State.regs[srcreg1];
4878 State.regs[dstreg2] = State.regs[srcreg2];
4879 State.regs[dstreg1] = result1;
4882 // 1111 0111 0111 0000 Rm1 Rn1 imm4 Rn2; add_mov Rm1, Rn1, imm4, Rn2
4883 8.0xf7+8.0x70+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_mov
4887 int srcreg1, dstreg1, dstreg2;
4891 srcreg1 = translate_rreg (SD_, RM1);
4892 dstreg1 = translate_rreg (SD_, RN1);
4893 dstreg2 = translate_rreg (SD_, RN2);
4895 result1 = State.regs[dstreg1] + State.regs[srcreg1];
4896 State.regs[dstreg2] = EXTEND4 (IMM4);
4897 State.regs[dstreg1] = result1;
4900 // 1111 0111 1000 0000 Rm1 Rn1 Rm2 Rn2; add_asr Rm1, Rn1, Rm2, Rn2
4901 8.0xf7+8.0x80+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_asr
4905 int srcreg1, srcreg2, dstreg1, dstreg2;
4910 srcreg1 = translate_rreg (SD_, RM1);
4911 srcreg2 = translate_rreg (SD_, RM2);
4912 dstreg1 = translate_rreg (SD_, RN1);
4913 dstreg2 = translate_rreg (SD_, RN2);
4915 result1 = State.regs[dstreg1] + State.regs[srcreg1];
4916 temp = State.regs[dstreg2];
4917 temp >>= State.regs[srcreg2];
4918 State.regs[dstreg2] = temp;
4919 State.regs[dstreg1] = result1;
4922 // 1111 0111 1001 0000 Rm1 Rn1 imm4 Rn2; add_asr Rm1, Rn1, imm4, Rn2
4923 8.0xf7+8.0x90+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_asr
4927 int srcreg1, dstreg1, dstreg2;
4932 srcreg1 = translate_rreg (SD_, RM1);
4933 dstreg1 = translate_rreg (SD_, RN1);
4934 dstreg2 = translate_rreg (SD_, RN2);
4936 result1 = State.regs[dstreg1] + State.regs[srcreg1];
4937 temp = State.regs[dstreg2];
4939 State.regs[dstreg2] = temp;
4940 State.regs[dstreg1] = result1;
4943 // 1111 0111 1010 0000 Rm1 Rn1 Rm2 Rn2; add_lsr Rm1, Rn1, Rm2, Rn2
4944 8.0xf7+8.0xa0+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_lsr
4948 int srcreg1, srcreg2, dstreg1, dstreg2;
4952 srcreg1 = translate_rreg (SD_, RM1);
4953 srcreg2 = translate_rreg (SD_, RM2);
4954 dstreg1 = translate_rreg (SD_, RN1);
4955 dstreg2 = translate_rreg (SD_, RN2);
4957 result1 = State.regs[dstreg1] + State.regs[srcreg1];
4958 State.regs[dstreg2] >>= State.regs[srcreg2];
4959 State.regs[dstreg1] = result1;
4962 // 1111 0111 1011 0000 Rm1 Rn1 imm4 Rn2; add_lsr Rm1, Rn1, imm4, Rn2
4963 8.0xf7+8.0xb0+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_lsr
4967 int srcreg1, dstreg1, dstreg2;
4972 srcreg1 = translate_rreg (SD_, RM1);
4973 dstreg1 = translate_rreg (SD_, RN1);
4974 dstreg2 = translate_rreg (SD_, RN2);
4976 result1 = State.regs[dstreg1] + State.regs[srcreg1];
4977 State.regs[dstreg2] >>= IMM4;
4978 State.regs[dstreg1] = result1;
4982 // 1111 0111 1100 0000 Rm1 Rn1 Rm2 Rn2; add_asl Rm1, Rn1, Rm2, Rn2
4983 8.0xf7+8.0xc0+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_asl
4987 int srcreg1, srcreg2, dstreg1, dstreg2;
4991 srcreg1 = translate_rreg (SD_, RM1);
4992 srcreg2 = translate_rreg (SD_, RM2);
4993 dstreg1 = translate_rreg (SD_, RN1);
4994 dstreg2 = translate_rreg (SD_, RN2);
4996 result1 = State.regs[dstreg1] + State.regs[srcreg1];
4997 State.regs[dstreg2] <<= State.regs[srcreg2];
4998 State.regs[dstreg1] = result1;
5001 // 1111 0111 1101 0000 Rm1 Rn1 imm4 Rn2; add_asl Rm1, Rn1, imm4, Rn2
5002 8.0xf7+8.0xd0+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_asl
5006 int srcreg1, dstreg1, dstreg2;
5011 srcreg1 = translate_rreg (SD_, RM1);
5012 dstreg1 = translate_rreg (SD_, RN1);
5013 dstreg2 = translate_rreg (SD_, RN2);
5015 result1 = State.regs[dstreg1] + State.regs[srcreg1];
5016 State.regs[dstreg2] <<= IMM4;
5017 State.regs[dstreg1] = result1;
5020 // 1111 0111 0000 0001 Rm1 Rn1 Rm2 Rn2; cmp_add Rm1, Rn1, Rm2, Rn2
5021 8.0xf7+8.0x01+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_add
5025 int srcreg1, srcreg2, dstreg1, dstreg2;
5028 srcreg1 = translate_rreg (SD_, RM1);
5029 srcreg2 = translate_rreg (SD_, RM2);
5030 dstreg1 = translate_rreg (SD_, RN1);
5031 dstreg2 = translate_rreg (SD_, RN2);
5033 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5034 State.regs[dstreg2] += State.regs[srcreg2];
5037 // 1111 0111 0001 0001 Rm1 Rn1 imm4 Rn2; cmp_add Rm1, Rn1, imm4, Rn2
5038 8.0xf7+8.0x11+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_add
5042 int srcreg1, dstreg1, dstreg2;
5045 srcreg1 = translate_rreg (SD_, RM1);
5046 dstreg1 = translate_rreg (SD_, RN1);
5047 dstreg2 = translate_rreg (SD_, RN2);
5049 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5050 State.regs[dstreg2] += EXTEND4 (IMM4);
5053 // 1111 0111 0010 0001 Rm1 Rn1 Rm2 Rn2; cmp_sub Rm1, Rn1, Rm2, Rn2
5054 8.0xf7+8.0x21+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_sub
5058 int srcreg1, srcreg2, dstreg1, dstreg2;
5061 srcreg1 = translate_rreg (SD_, RM1);
5062 srcreg2 = translate_rreg (SD_, RM2);
5063 dstreg1 = translate_rreg (SD_, RN1);
5064 dstreg2 = translate_rreg (SD_, RN2);
5066 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5067 State.regs[dstreg2] -= State.regs[srcreg2];
5070 // 1111 0111 0011 0001 Rm1 Rn1 imm4 Rn2; cmp_sub Rm1, Rn1, imm4, Rn2
5071 8.0xf7+8.0x31+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_sub
5075 int srcreg1, dstreg1, dstreg2;
5078 srcreg1 = translate_rreg (SD_, RM1);
5079 dstreg1 = translate_rreg (SD_, RN1);
5080 dstreg2 = translate_rreg (SD_, RN2);
5082 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5083 State.regs[dstreg2] -= EXTEND4 (IMM4);
5086 // 1111 0111 0110 0001 Rm1 Rn1 Rm2 Rn2; cmp_mov Rm1, Rn1, Rm2, Rn2
5087 8.0xf7+8.0x61+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_mov
5091 int srcreg1, srcreg2, dstreg1, dstreg2;
5094 srcreg1 = translate_rreg (SD_, RM1);
5095 srcreg2 = translate_rreg (SD_, RM2);
5096 dstreg1 = translate_rreg (SD_, RN1);
5097 dstreg2 = translate_rreg (SD_, RN2);
5099 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5100 State.regs[dstreg2] = State.regs[srcreg2];
5103 // 1111 0111 0111 0001 Rm1 Rn1 imm4 Rn2; cmp_mov Rm1, Rn1, imm4, Rn2
5104 8.0xf7+8.0x71+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_mov
5108 int srcreg1, dstreg1, dstreg2;
5111 srcreg1 = translate_rreg (SD_, RM1);
5112 dstreg1 = translate_rreg (SD_, RN1);
5113 dstreg2 = translate_rreg (SD_, RN2);
5115 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5116 State.regs[dstreg2] = EXTEND4 (IMM4);
5119 // 1111 0111 1000 0001 Rm1 Rn1 Rm2 Rn2; cmp_asr Rm1, Rn1, Rm2, Rn2
5120 8.0xf7+8.0x81+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_asr
5124 int srcreg1, srcreg2, dstreg1, dstreg2;
5128 srcreg1 = translate_rreg (SD_, RM1);
5129 srcreg2 = translate_rreg (SD_, RM2);
5130 dstreg1 = translate_rreg (SD_, RN1);
5131 dstreg2 = translate_rreg (SD_, RN2);
5133 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5134 temp = State.regs[dstreg2];
5135 temp >>= State.regs[srcreg2];
5136 State.regs[dstreg2] = temp;
5139 // 1111 0111 1001 0001 Rm1 Rn1 imm4 Rn2; cmp_asr Rm1, Rn1, imm4, Rn2
5140 8.0xf7+8.0x91+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_asr
5144 int srcreg1, dstreg1, dstreg2;
5148 srcreg1 = translate_rreg (SD_, RM1);
5149 dstreg1 = translate_rreg (SD_, RN1);
5150 dstreg2 = translate_rreg (SD_, RN2);
5152 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5153 temp = State.regs[dstreg2];
5155 State.regs[dstreg2] = temp;
5158 // 1111 0111 1010 0001 Rm1 Rn1 Rm2 Rn2; cmp_lsr Rm1, Rn1, Rm2, Rn2
5159 8.0xf7+8.0xa1+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_lsr
5163 int srcreg1, srcreg2, dstreg1, dstreg2;
5166 srcreg1 = translate_rreg (SD_, RM1);
5167 srcreg2 = translate_rreg (SD_, RM2);
5168 dstreg1 = translate_rreg (SD_, RN1);
5169 dstreg2 = translate_rreg (SD_, RN2);
5171 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5172 State.regs[dstreg2] >>= State.regs[srcreg2];
5175 // 1111 0111 1011 0001 Rm1 Rn1 imm4 Rn2; cmp_lsr Rm1, Rn1, imm4, Rn2
5176 8.0xf7+8.0xb1+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_lsr
5180 int srcreg1, dstreg1, dstreg2;
5184 srcreg1 = translate_rreg (SD_, RM1);
5185 dstreg1 = translate_rreg (SD_, RN1);
5186 dstreg2 = translate_rreg (SD_, RN2);
5188 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5189 State.regs[dstreg2] >>= IMM4;
5193 // 1111 0111 1100 0001 Rm1 Rn1 Rm2 Rn2; cmp_asl Rm1, Rn1, Rm2, Rn2
5194 8.0xf7+8.0xc1+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_asl
5198 int srcreg1, srcreg2, dstreg1, dstreg2;
5201 srcreg1 = translate_rreg (SD_, RM1);
5202 srcreg2 = translate_rreg (SD_, RM2);
5203 dstreg1 = translate_rreg (SD_, RN1);
5204 dstreg2 = translate_rreg (SD_, RN2);
5206 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5207 State.regs[dstreg2] <<= State.regs[srcreg2];
5210 // 1111 0111 1101 0001 Rm1 Rn1 imm4 Rn2; cmp_asl Rm1, Rn1, imm4, Rn2
5211 8.0xf7+8.0xd1+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_asl
5215 int srcreg1, dstreg1, dstreg2;
5219 srcreg1 = translate_rreg (SD_, RM1);
5220 dstreg1 = translate_rreg (SD_, RN1);
5221 dstreg2 = translate_rreg (SD_, RN2);
5223 genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5224 State.regs[dstreg2] <<= IMM4;
5227 // 1111 0111 0000 0010 Rm1 Rn1 Rm2 Rn2; sub_add Rm1, Rn1, Rm2, Rn2
5228 8.0xf7+8.0x02+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_add
5232 int srcreg1, srcreg2, dstreg1, dstreg2;
5236 srcreg1 = translate_rreg (SD_, RM1);
5237 srcreg2 = translate_rreg (SD_, RM2);
5238 dstreg1 = translate_rreg (SD_, RN1);
5239 dstreg2 = translate_rreg (SD_, RN2);
5241 result1 = State.regs[dstreg1] - State.regs[srcreg1];
5242 State.regs[dstreg2] += State.regs[srcreg2];
5243 State.regs[dstreg1] = result1;
5246 // 1111 0111 0001 0010 Rm1 Rn1 imm4 Rn2; sub_add Rm1, Rn1, imm4, Rn2
5247 8.0xf7+8.0x12+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_add
5251 int srcreg1, dstreg1, dstreg2;
5255 srcreg1 = translate_rreg (SD_, RM1);
5256 dstreg1 = translate_rreg (SD_, RN1);
5257 dstreg2 = translate_rreg (SD_, RN2);
5259 result1 = State.regs[dstreg1] - State.regs[srcreg1];
5260 State.regs[dstreg2] += EXTEND4 (IMM4);
5261 State.regs[dstreg1] = result1;
5264 // 1111 0111 0010 0010 Rm1 Rn1 Rm2 Rn2; sub_sub Rm1, Rn1, Rm2, Rn2
5265 8.0xf7+8.0x22+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_sub
5269 int srcreg1, srcreg2, dstreg1, dstreg2;
5273 srcreg1 = translate_rreg (SD_, RM1);
5274 srcreg2 = translate_rreg (SD_, RM2);
5275 dstreg1 = translate_rreg (SD_, RN1);
5276 dstreg2 = translate_rreg (SD_, RN2);
5278 result1 = State.regs[dstreg1] - State.regs[srcreg1];
5279 State.regs[dstreg2] -= State.regs[srcreg2];
5280 State.regs[dstreg1] = result1;
5283 // 1111 0111 0011 0010 Rm1 Rn1 imm4 Rn2; sub_sub Rm1, Rn1, imm4, Rn2
5284 8.0xf7+8.0x32+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_sub
5288 int srcreg1, dstreg1, dstreg2;
5292 srcreg1 = translate_rreg (SD_, RM1);
5293 dstreg1 = translate_rreg (SD_, RN1);
5294 dstreg2 = translate_rreg (SD_, RN2);
5296 result1 = State.regs[dstreg1] - State.regs[srcreg1];
5297 State.regs[dstreg2] -= EXTEND4 (IMM4);
5298 State.regs[dstreg1] = result1;
5301 // 1111 0111 0100 0010 Rm1 Rn1 Rm2 Rn2; sub_cmp Rm1, Rn1, Rm2, Rn2
5302 8.0xf7+8.0x42+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_cmp
5306 int srcreg1, srcreg2, dstreg1, dstreg2;
5309 srcreg1 = translate_rreg (SD_, RM1);
5310 srcreg2 = translate_rreg (SD_, RM2);
5311 dstreg1 = translate_rreg (SD_, RN1);
5312 dstreg2 = translate_rreg (SD_, RN2);
5314 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
5315 State.regs[dstreg1] -= State.regs[srcreg1];
5318 // 1111 0111 0101 0010 Rm1 Rn1 imm4 Rn2; sub_cmp Rm1, Rn1, imm4, Rn2
5319 8.0xf7+8.0x52+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_cmp
5323 int srcreg1, dstreg1, dstreg2;
5327 srcreg1 = translate_rreg (SD_, RM1);
5328 dstreg1 = translate_rreg (SD_, RN1);
5329 dstreg2 = translate_rreg (SD_, RN2);
5331 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
5332 State.regs[dstreg1] -= State.regs[srcreg1];
5335 // 1111 0111 0110 0010 Rm1 Rn1 Rm2 Rn2; sub_mov Rm1, Rn1, Rm2, Rn2
5336 8.0xf7+8.0x62+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_mov
5340 int srcreg1, srcreg2, dstreg1, dstreg2;
5344 srcreg1 = translate_rreg (SD_, RM1);
5345 srcreg2 = translate_rreg (SD_, RM2);
5346 dstreg1 = translate_rreg (SD_, RN1);
5347 dstreg2 = translate_rreg (SD_, RN2);
5349 result1 = State.regs[dstreg1] - State.regs[srcreg1];
5350 State.regs[dstreg2] = State.regs[srcreg2];
5351 State.regs[dstreg1] = result1;
5354 // 1111 0111 0111 0010 Rm1 Rn1 imm4 Rn2; sub_mov Rm1, Rn1, imm4, Rn2
5355 8.0xf7+8.0x72+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_mov
5359 int srcreg1, dstreg1, dstreg2;
5363 srcreg1 = translate_rreg (SD_, RM1);
5364 dstreg1 = translate_rreg (SD_, RN1);
5365 dstreg2 = translate_rreg (SD_, RN2);
5367 result1 = State.regs[dstreg1] - State.regs[srcreg1];
5368 State.regs[dstreg2] = EXTEND4 (IMM4);
5369 State.regs[dstreg1] = result1;
5372 // 1111 0111 1000 0010 Rm1 Rn1 Rm2 Rn2; sub_asr Rm1, Rn1, Rm2, Rn2
5373 8.0xf7+8.0x82+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_asr
5377 int srcreg1, srcreg2, dstreg1, dstreg2;
5382 srcreg1 = translate_rreg (SD_, RM1);
5383 srcreg2 = translate_rreg (SD_, RM2);
5384 dstreg1 = translate_rreg (SD_, RN1);
5385 dstreg2 = translate_rreg (SD_, RN2);
5387 result1 = State.regs[dstreg1] - State.regs[srcreg1];
5388 temp = State.regs[dstreg2];
5389 temp >>= State.regs[srcreg2];
5390 State.regs[dstreg2] = temp;
5391 State.regs[dstreg1] = result1;
5394 // 1111 0111 1001 0010 Rm1 Rn1 imm4 Rn2; sub_asr Rm1, Rn1, imm4, Rn2
5395 8.0xf7+8.0x92+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_asr
5399 int srcreg1, dstreg1, dstreg2;
5404 srcreg1 = translate_rreg (SD_, RM1);
5405 dstreg1 = translate_rreg (SD_, RN1);
5406 dstreg2 = translate_rreg (SD_, RN2);
5408 result1 = State.regs[dstreg1] - State.regs[srcreg1];
5409 temp = State.regs[dstreg2];
5411 State.regs[dstreg2] = temp;
5412 State.regs[dstreg1] = result1;
5415 // 1111 0111 1010 0010 Rm1 Rn1 Rm2 Rn2; sub_lsr Rm1, Rn1, Rm2, Rn2
5416 8.0xf7+8.0xa2+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_lsr
5420 int srcreg1, srcreg2, dstreg1, dstreg2;
5424 srcreg1 = translate_rreg (SD_, RM1);
5425 srcreg2 = translate_rreg (SD_, RM2);
5426 dstreg1 = translate_rreg (SD_, RN1);
5427 dstreg2 = translate_rreg (SD_, RN2);
5429 result1 = State.regs[dstreg1] - State.regs[srcreg1];
5430 State.regs[dstreg2] >>= State.regs[srcreg2];
5431 State.regs[dstreg1] = result1;
5434 // 1111 0111 1011 0010 Rm1 Rn1 imm4 Rn2; sub_lsr Rm1, Rn1, imm4, Rn2
5435 8.0xf7+8.0xb2+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_lsr
5439 int srcreg1, dstreg1, dstreg2;
5444 srcreg1 = translate_rreg (SD_, RM1);
5445 dstreg1 = translate_rreg (SD_, RN1);
5446 dstreg2 = translate_rreg (SD_, RN2);
5448 result1 = State.regs[dstreg1] - State.regs[srcreg1];
5449 State.regs[dstreg2] >>= IMM4;
5450 State.regs[dstreg1] = result1;
5454 // 1111 0111 1100 0010 Rm1 Rn1 Rm2 Rn2; sub_asl Rm1, Rn1, Rm2, Rn2
5455 8.0xf7+8.0xc2+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_asl
5459 int srcreg1, srcreg2, dstreg1, dstreg2;
5463 srcreg1 = translate_rreg (SD_, RM1);
5464 srcreg2 = translate_rreg (SD_, RM2);
5465 dstreg1 = translate_rreg (SD_, RN1);
5466 dstreg2 = translate_rreg (SD_, RN2);
5468 result1 = State.regs[dstreg1] - State.regs[srcreg1];
5469 State.regs[dstreg2] <<= State.regs[srcreg2];
5470 State.regs[dstreg1] = result1;
5473 // 1111 0111 1101 0010 Rm1 Rn1 imm4 Rn2; sub_asl Rm1, Rn1, imm4, Rn2
5474 8.0xf7+8.0xd2+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_asl
5478 int srcreg1, dstreg1, dstreg2;
5483 srcreg1 = translate_rreg (SD_, RM1);
5484 dstreg1 = translate_rreg (SD_, RN1);
5485 dstreg2 = translate_rreg (SD_, RN2);
5487 result1 = State.regs[dstreg1] - State.regs[srcreg1];
5488 State.regs[dstreg2] <<= IMM4;
5489 State.regs[dstreg1] = result1;
5492 // 1111 0111 0000 0011 Rm1 Rn1 Rm2 Rn2; mov_add Rm1, Rn1, Rm2, Rn2
5493 8.0xf7+8.0x03+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_add
5497 int srcreg1, srcreg2, dstreg1, dstreg2;
5501 srcreg1 = translate_rreg (SD_, RM1);
5502 srcreg2 = translate_rreg (SD_, RM2);
5503 dstreg1 = translate_rreg (SD_, RN1);
5504 dstreg2 = translate_rreg (SD_, RN2);
5506 result1 = State.regs[srcreg1];
5507 State.regs[dstreg2] += State.regs[srcreg2];
5508 State.regs[dstreg1] = result1;
5511 // 1111 0111 0001 0011 Rm1 Rn1 imm4 Rn2; mov_add Rm1, Rn1, imm4, Rn2
5512 8.0xf7+8.0x13+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_add
5516 int srcreg1, dstreg1, dstreg2;
5520 srcreg1 = translate_rreg (SD_, RM1);
5521 dstreg1 = translate_rreg (SD_, RN1);
5522 dstreg2 = translate_rreg (SD_, RN2);
5524 result1 = State.regs[srcreg1];
5525 State.regs[dstreg2] += EXTEND4 (IMM4);
5526 State.regs[dstreg1] = result1;
5529 // 1111 0111 0010 0011 Rm1 Rn1 Rm2 Rn2; mov_sub Rm1, Rn1, Rm2, Rn2
5530 8.0xf7+8.0x23+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_sub
5534 int srcreg1, srcreg2, dstreg1, dstreg2;
5538 srcreg1 = translate_rreg (SD_, RM1);
5539 srcreg2 = translate_rreg (SD_, RM2);
5540 dstreg1 = translate_rreg (SD_, RN1);
5541 dstreg2 = translate_rreg (SD_, RN2);
5543 result1 = State.regs[srcreg1];
5544 State.regs[dstreg2] -= State.regs[srcreg2];
5545 State.regs[dstreg1] = result1;
5548 // 1111 0111 0011 0011 Rm1 Rn1 imm4 Rn2; mov_sub Rm1, Rn1, imm4, Rn2
5549 8.0xf7+8.0x33+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_sub
5553 int srcreg1, dstreg1, dstreg2;
5557 srcreg1 = translate_rreg (SD_, RM1);
5558 dstreg1 = translate_rreg (SD_, RN1);
5559 dstreg2 = translate_rreg (SD_, RN2);
5561 result1 = State.regs[srcreg1];
5562 State.regs[dstreg2] -= EXTEND4 (IMM4);
5563 State.regs[dstreg1] = result1;
5566 // 1111 0111 0100 0011 Rm1 Rn1 Rm2 Rn2; mov_cmp Rm1, Rn1, Rm2, Rn2
5567 8.0xf7+8.0x43+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_cmp
5571 int srcreg1, srcreg2, dstreg1, dstreg2;
5574 srcreg1 = translate_rreg (SD_, RM1);
5575 srcreg2 = translate_rreg (SD_, RM2);
5576 dstreg1 = translate_rreg (SD_, RN1);
5577 dstreg2 = translate_rreg (SD_, RN2);
5579 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
5580 State.regs[dstreg1] = State.regs[srcreg1];
5583 // 1111 0111 0101 0011 Rm1 Rn1 imm4 Rn2; mov_cmp Rm1, Rn1, imm4, Rn2
5584 8.0xf7+8.0x53+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_cmp
5588 int srcreg1, dstreg1, dstreg2;
5591 srcreg1 = translate_rreg (SD_, RM1);
5592 dstreg1 = translate_rreg (SD_, RN1);
5593 dstreg2 = translate_rreg (SD_, RN2);
5595 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
5596 State.regs[dstreg1] = State.regs[srcreg1];
5599 // 1111 0111 0110 0011 Rm1 Rn1 Rm2 Rn2; mov_mov Rm1, Rn1, Rm2, Rn2
5600 8.0xf7+8.0x63+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_mov
5604 int srcreg1, srcreg2, dstreg1, dstreg2;
5608 srcreg1 = translate_rreg (SD_, RM1);
5609 srcreg2 = translate_rreg (SD_, RM2);
5610 dstreg1 = translate_rreg (SD_, RN1);
5611 dstreg2 = translate_rreg (SD_, RN2);
5613 result1 = State.regs[srcreg1];
5614 State.regs[dstreg2] = State.regs[srcreg2];
5615 State.regs[dstreg1] = result1;
5618 // 1111 0111 0111 0011 Rm1 Rn1 imm4 Rn2; mov_mov Rm1, Rn1, imm4, Rn2
5619 8.0xf7+8.0x73+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_mov
5623 int srcreg1, dstreg1, dstreg2;
5627 srcreg1 = translate_rreg (SD_, RM1);
5628 dstreg1 = translate_rreg (SD_, RN1);
5629 dstreg2 = translate_rreg (SD_, RN2);
5631 result1 = State.regs[srcreg1];
5632 State.regs[dstreg2] = EXTEND4 (IMM4);
5633 State.regs[dstreg1] = result1;
5636 // 1111 0111 1000 0011 Rm1 Rn1 Rm2 Rn2; mov_asr Rm1, Rn1, Rm2, Rn2
5637 8.0xf7+8.0x83+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_asr
5641 int srcreg1, srcreg2, dstreg1, dstreg2;
5646 srcreg1 = translate_rreg (SD_, RM1);
5647 srcreg2 = translate_rreg (SD_, RM2);
5648 dstreg1 = translate_rreg (SD_, RN1);
5649 dstreg2 = translate_rreg (SD_, RN2);
5651 result1 = State.regs[srcreg1];
5652 temp = State.regs[dstreg2];
5653 temp >>= State.regs[srcreg2];
5654 State.regs[dstreg2] = temp;
5655 State.regs[dstreg1] = result1;
5658 // 1111 0111 1001 0011 Rm1 Rn1 imm4 Rn2; mov_asr Rm1, Rn1, imm4, Rn2
5659 8.0xf7+8.0x93+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_asr
5663 int srcreg1, dstreg1, dstreg2;
5668 srcreg1 = translate_rreg (SD_, RM1);
5669 dstreg1 = translate_rreg (SD_, RN1);
5670 dstreg2 = translate_rreg (SD_, RN2);
5672 result1 = State.regs[srcreg1];
5673 temp = State.regs[dstreg2];
5675 State.regs[dstreg2] = temp;
5676 State.regs[dstreg1] = result1;
5679 // 1111 0111 1010 0011 Rm1 Rn1 Rm2 Rn2; mov_lsr Rm1, Rn1, Rm2, Rn2
5680 8.0xf7+8.0xa3+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_lsr
5684 int srcreg1, srcreg2, dstreg1, dstreg2;
5688 srcreg1 = translate_rreg (SD_, RM1);
5689 srcreg2 = translate_rreg (SD_, RM2);
5690 dstreg1 = translate_rreg (SD_, RN1);
5691 dstreg2 = translate_rreg (SD_, RN2);
5693 result1 = State.regs[srcreg1];
5694 State.regs[dstreg2] >>= State.regs[srcreg2];
5695 State.regs[dstreg1] = result1;
5698 // 1111 0111 1011 0011 Rm1 Rn1 imm4 Rn2; mov_lsr Rm1, Rn1, imm4, Rn2
5699 8.0xf7+8.0xb3+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_lsr
5703 int srcreg1, dstreg1, dstreg2;
5708 srcreg1 = translate_rreg (SD_, RM1);
5709 dstreg1 = translate_rreg (SD_, RN1);
5710 dstreg2 = translate_rreg (SD_, RN2);
5712 result1 = State.regs[srcreg1];
5713 State.regs[dstreg2] >>= IMM4;
5714 State.regs[dstreg1] = result1;
5718 // 1111 0111 1100 0011 Rm1 Rn1 Rm2 Rn2; mov_asl Rm1, Rn1, Rm2, Rn2
5719 8.0xf7+8.0xc3+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_asl
5723 int srcreg1, srcreg2, dstreg1, dstreg2;
5727 srcreg1 = translate_rreg (SD_, RM1);
5728 srcreg2 = translate_rreg (SD_, RM2);
5729 dstreg1 = translate_rreg (SD_, RN1);
5730 dstreg2 = translate_rreg (SD_, RN2);
5732 result1 = State.regs[srcreg1];
5733 State.regs[dstreg2] <<= State.regs[srcreg2];
5734 State.regs[dstreg1] = result1;
5737 // 1111 0111 1101 0011 Rm1 Rn1 imm4 Rn2; mov_asl Rm1, Rn1, imm4, Rn2
5738 8.0xf7+8.0xd3+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_asl
5742 int srcreg1, dstreg1, dstreg2;
5747 srcreg1 = translate_rreg (SD_, RM1);
5748 dstreg1 = translate_rreg (SD_, RN1);
5749 dstreg2 = translate_rreg (SD_, RN2);
5751 result1 = State.regs[srcreg1];
5752 State.regs[dstreg2] <<= IMM4;
5753 State.regs[dstreg1] = result1;
5756 // 1111 0111 0000 0100 imm4 Rn1 Rm2 Rn2; add_add imm4, Rn1, Rm2, Rn2
5757 8.0xf7+8.0x04+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_add
5761 int srcreg2, dstreg1, dstreg2;
5765 srcreg2 = translate_rreg (SD_, RM2);
5766 dstreg1 = translate_rreg (SD_, RN1);
5767 dstreg2 = translate_rreg (SD_, RN2);
5769 result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5770 State.regs[dstreg2] += State.regs[srcreg2];
5771 State.regs[dstreg1] = result1;
5774 // 1111 0111 0001 0100 imm4 Rn1 imm4 Rn2; add_add imm4, Rn1, imm4, Rn2
5775 8.0xf7+8.0x14+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_add
5779 int dstreg1, dstreg2;
5783 dstreg1 = translate_rreg (SD_, RN1);
5784 dstreg2 = translate_rreg (SD_, RN2);
5786 result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5787 State.regs[dstreg2] += EXTEND4 (IMM4);
5788 State.regs[dstreg1] = result1;
5791 // 1111 0111 0010 0100 imm4 Rn1 Rm2 Rn2; add_sub imm4, Rn1, Rm2, Rn2
5792 8.0xf7+8.0x24+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_sub
5796 int srcreg2, dstreg1, dstreg2;
5800 srcreg2 = translate_rreg (SD_, RM2);
5801 dstreg1 = translate_rreg (SD_, RN1);
5802 dstreg2 = translate_rreg (SD_, RN2);
5804 result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5805 State.regs[dstreg2] -= State.regs[srcreg2];
5806 State.regs[dstreg1] = result1;
5809 // 1111 0111 0011 0100 imm4 Rn1 imm4 Rn2; add_sub imm4, Rn1, imm4, Rn2
5810 8.0xf7+8.0x34+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_sub
5814 int dstreg1, dstreg2;
5818 dstreg1 = translate_rreg (SD_, RN1);
5819 dstreg2 = translate_rreg (SD_, RN2);
5821 result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5822 State.regs[dstreg2] -= EXTEND4 (IMM4);
5823 State.regs[dstreg1] = result1;
5826 // 1111 0111 0100 0100 imm4 Rn1 Rm2 Rn2; add_cmp imm4, Rn1, Rm2, Rn2
5827 8.0xf7+8.0x44+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_cmp
5831 int srcreg2, dstreg1, dstreg2;
5834 srcreg2 = translate_rreg (SD_, RM2);
5835 dstreg1 = translate_rreg (SD_, RN1);
5836 dstreg2 = translate_rreg (SD_, RN2);
5838 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
5839 State.regs[dstreg1] += EXTEND4 (IMM4A);
5842 // 1111 0111 0101 0100 imm4 Rn1 imm4 Rn2; add_cmp imm4, Rn1, imm4, Rn2
5843 8.0xf7+8.0x54+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_cmp
5847 int dstreg1, dstreg2;
5850 dstreg1 = translate_rreg (SD_, RN1);
5851 dstreg2 = translate_rreg (SD_, RN2);
5853 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
5854 State.regs[dstreg1] += EXTEND4 (IMM4A);
5857 // 1111 0111 0110 0100 imm4 Rn1 Rm2 Rn2; add_mov imm4, Rn1, Rm2, Rn2
5858 8.0xf7+8.0x64+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_mov
5862 int srcreg2, dstreg1, dstreg2;
5866 srcreg2 = translate_rreg (SD_, RM2);
5867 dstreg1 = translate_rreg (SD_, RN1);
5868 dstreg2 = translate_rreg (SD_, RN2);
5870 result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5871 State.regs[dstreg2] = State.regs[srcreg2];
5872 State.regs[dstreg1] = result1;
5875 // 1111 0111 0111 0100 imm4 Rn1 imm4 Rn2; add_mov imm4, Rn1, imm4, Rn2
5876 8.0xf7+8.0x74+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_mov
5880 int dstreg1, dstreg2;
5884 dstreg1 = translate_rreg (SD_, RN1);
5885 dstreg2 = translate_rreg (SD_, RN2);
5887 result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5888 State.regs[dstreg2] = EXTEND4 (IMM4);
5889 State.regs[dstreg1] = result1;
5892 // 1111 0111 1000 0100 imm4 Rn1 Rm2 Rn2; add_asr imm4, Rn1, Rm2, Rn2
5893 8.0xf7+8.0x84+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_asr
5897 int srcreg2, dstreg1, dstreg2;
5902 srcreg2 = translate_rreg (SD_, RM2);
5903 dstreg1 = translate_rreg (SD_, RN1);
5904 dstreg2 = translate_rreg (SD_, RN2);
5906 result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5907 temp = State.regs[dstreg2];
5908 temp >>= State.regs[srcreg2];
5909 State.regs[dstreg2] = temp;
5910 State.regs[dstreg1] = result1;
5913 // 1111 0111 1001 0100 imm4 Rn1 imm4 Rn2; add_asr imm4, Rn1, imm4, Rn2
5914 8.0xf7+8.0x94+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_asr
5918 int dstreg1, dstreg2;
5923 dstreg1 = translate_rreg (SD_, RN1);
5924 dstreg2 = translate_rreg (SD_, RN2);
5926 result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5927 temp = State.regs[dstreg2];
5929 State.regs[dstreg2] = temp;
5930 State.regs[dstreg1] = result1;
5933 // 1111 0111 1010 0100 imm4 Rn1 Rm2 Rn2; add_lsr imm4, Rn1, Rm2, Rn2
5934 8.0xf7+8.0xa4+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_lsr
5938 int srcreg2, dstreg1, dstreg2;
5942 srcreg2 = translate_rreg (SD_, RM2);
5943 dstreg1 = translate_rreg (SD_, RN1);
5944 dstreg2 = translate_rreg (SD_, RN2);
5946 result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5947 State.regs[dstreg2] >>= State.regs[srcreg2];
5948 State.regs[dstreg1] = result1;
5951 // 1111 0111 1011 0100 imm4 Rn1 imm4 Rn2; add_lsr imm4, Rn1, imm4, Rn2
5952 8.0xf7+8.0xb4+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_lsr
5956 int dstreg1, dstreg2;
5961 dstreg1 = translate_rreg (SD_, RN1);
5962 dstreg2 = translate_rreg (SD_, RN2);
5964 result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5965 State.regs[dstreg2] >>= IMM4;
5966 State.regs[dstreg1] = result1;
5970 // 1111 0111 1100 0100 imm4 Rn1 Rm2 Rn2; add_asl imm4, Rn1, Rm2, Rn2
5971 8.0xf7+8.0xc4+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_asl
5975 int srcreg2, dstreg1, dstreg2;
5979 srcreg2 = translate_rreg (SD_, RM2);
5980 dstreg1 = translate_rreg (SD_, RN1);
5981 dstreg2 = translate_rreg (SD_, RN2);
5983 result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5984 State.regs[dstreg2] <<= State.regs[srcreg2];
5985 State.regs[dstreg1] = result1;
5988 // 1111 0111 1101 0100 imm4 Rn1 imm4 Rn2; add_asl imm4, Rn1, imm4, Rn2
5989 8.0xf7+8.0xd4+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_asl
5993 int dstreg1, dstreg2;
5998 dstreg1 = translate_rreg (SD_, RN1);
5999 dstreg2 = translate_rreg (SD_, RN2);
6001 result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
6002 State.regs[dstreg2] <<= IMM4;
6003 State.regs[dstreg1] = result1;
6006 // 1111 0111 0000 0101 imm4 Rn1 Rm2 Rn2; cmp_add imm4, Rn1, Rm2, Rn2
6007 8.0xf7+8.0x05+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_add
6011 int srcreg2, dstreg1, dstreg2;
6014 srcreg2 = translate_rreg (SD_, RM2);
6015 dstreg1 = translate_rreg (SD_, RN1);
6016 dstreg2 = translate_rreg (SD_, RN2);
6018 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6019 State.regs[dstreg2] += State.regs[srcreg2];
6022 // 1111 0111 0001 0101 imm4 Rn1 imm4 Rn2; cmp_add imm4, Rn1, imm4, Rn2
6023 8.0xf7+8.0x15+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_add
6027 int dstreg1, dstreg2;
6030 dstreg1 = translate_rreg (SD_, RN1);
6031 dstreg2 = translate_rreg (SD_, RN2);
6033 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6034 State.regs[dstreg2] += EXTEND4 (IMM4);
6037 // 1111 0111 0010 0101 imm4 Rn1 Rm2 Rn2; cmp_sub imm4, Rn1, Rm2, Rn2
6038 8.0xf7+8.0x25+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_sub
6042 int srcreg2, dstreg1, dstreg2;
6045 srcreg2 = translate_rreg (SD_, RM2);
6046 dstreg1 = translate_rreg (SD_, RN1);
6047 dstreg2 = translate_rreg (SD_, RN2);
6049 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6050 State.regs[dstreg2] -= State.regs[srcreg2];
6053 // 1111 0111 0011 0101 imm4 Rn1 imm4 Rn2; cmp_sub imm4, Rn1, imm4, Rn2
6054 8.0xf7+8.0x35+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_sub
6058 int dstreg1, dstreg2;
6061 dstreg1 = translate_rreg (SD_, RN1);
6062 dstreg2 = translate_rreg (SD_, RN2);
6064 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6065 State.regs[dstreg2] -= EXTEND4 (IMM4);
6068 // 1111 0111 0110 0101 imm4 Rn1 Rm2 Rn2; cmp_mov imm4, Rn1, Rm2, Rn2
6069 8.0xf7+8.0x65+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_mov
6073 int srcreg2, dstreg1, dstreg2;
6076 srcreg2 = translate_rreg (SD_, RM2);
6077 dstreg1 = translate_rreg (SD_, RN1);
6078 dstreg2 = translate_rreg (SD_, RN2);
6080 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6081 State.regs[dstreg2] = State.regs[srcreg2];
6084 // 1111 0111 0111 0101 imm4 Rn1 imm4 Rn2; cmp_mov imm4, Rn1, imm4, Rn2
6085 8.0xf7+8.0x75+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_mov
6089 int dstreg1, dstreg2;
6092 dstreg1 = translate_rreg (SD_, RN1);
6093 dstreg2 = translate_rreg (SD_, RN2);
6095 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6096 State.regs[dstreg2] = EXTEND4 (IMM4);
6099 // 1111 0111 1000 0101 imm4 Rn1 Rm2 Rn2; cmp_asr imm4, Rn1, Rm2, Rn2
6100 8.0xf7+8.0x85+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_asr
6104 int srcreg2, dstreg1, dstreg2;
6108 srcreg2 = translate_rreg (SD_, RM2);
6109 dstreg1 = translate_rreg (SD_, RN1);
6110 dstreg2 = translate_rreg (SD_, RN2);
6112 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6113 temp = State.regs[dstreg2];
6114 temp >>= State.regs[srcreg2];
6115 State.regs[dstreg2] = temp;
6118 // 1111 0111 1001 0101 imm4 Rn1 imm4 Rn2; cmp_asr imm4, Rn1, imm4, Rn2
6119 8.0xf7+8.0x95+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_asr
6123 int dstreg1, dstreg2;
6127 dstreg1 = translate_rreg (SD_, RN1);
6128 dstreg2 = translate_rreg (SD_, RN2);
6130 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6131 temp = State.regs[dstreg2];
6133 State.regs[dstreg2] = temp;
6136 // 1111 0111 1010 0101 imm4 Rn1 Rm2 Rn2; cmp_lsr imm4, Rn1, Rm2, Rn2
6137 8.0xf7+8.0xa5+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_lsr
6141 int srcreg2, dstreg1, dstreg2;
6144 srcreg2 = translate_rreg (SD_, RM2);
6145 dstreg1 = translate_rreg (SD_, RN1);
6146 dstreg2 = translate_rreg (SD_, RN2);
6148 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6149 State.regs[dstreg2] >>= State.regs[srcreg2];
6152 // 1111 0111 1011 0101 imm4 Rn1 imm4 Rn2; cmp_lsr imm4, Rn1, imm4, Rn2
6153 8.0xf7+8.0xb5+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_lsr
6157 int dstreg1, dstreg2;
6161 dstreg1 = translate_rreg (SD_, RN1);
6162 dstreg2 = translate_rreg (SD_, RN2);
6164 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6165 State.regs[dstreg2] >>= IMM4;
6169 // 1111 0111 1100 0101 imm4 Rn1 Rm2 Rn2; cmp_asl imm4, Rn1, Rm2, Rn2
6170 8.0xf7+8.0xc5+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_asl
6174 int srcreg2, dstreg1, dstreg2;
6177 srcreg2 = translate_rreg (SD_, RM2);
6178 dstreg1 = translate_rreg (SD_, RN1);
6179 dstreg2 = translate_rreg (SD_, RN2);
6181 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6182 State.regs[dstreg2] <<= State.regs[srcreg2];
6185 // 1111 0111 1101 0101 imm4 Rn1 imm4 Rn2; cmp_asl imm4, Rn1, imm4, Rn2
6186 8.0xf7+8.0xd5+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_asl
6190 int dstreg1, dstreg2;
6194 dstreg1 = translate_rreg (SD_, RN1);
6195 dstreg2 = translate_rreg (SD_, RN2);
6197 genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6198 State.regs[dstreg2] <<= IMM4;
6201 // 1111 0111 0000 0110 imm4 Rn1 Rm2 Rn2; sub_add imm4, Rn1, Rm2, Rn2
6202 8.0xf7+8.0x06+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_add
6206 int srcreg2, dstreg1, dstreg2;
6210 srcreg2 = translate_rreg (SD_, RM2);
6211 dstreg1 = translate_rreg (SD_, RN1);
6212 dstreg2 = translate_rreg (SD_, RN2);
6214 result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6215 State.regs[dstreg2] += State.regs[srcreg2];
6216 State.regs[dstreg1] = result1;
6219 // 1111 0111 0001 0110 imm4 Rn1 imm4 Rn2; sub_add imm4, Rn1, imm4, Rn2
6220 8.0xf7+8.0x16+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_add
6224 int dstreg1, dstreg2;
6228 dstreg1 = translate_rreg (SD_, RN1);
6229 dstreg2 = translate_rreg (SD_, RN2);
6231 result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6232 State.regs[dstreg2] += EXTEND4 (IMM4);
6233 State.regs[dstreg1] = result1;
6236 // 1111 0111 0010 0110 imm4 Rn1 Rm2 Rn2; sub_sub imm4, Rn1, Rm2, Rn2
6237 8.0xf7+8.0x26+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_sub
6241 int srcreg2, dstreg1, dstreg2;
6245 srcreg2 = translate_rreg (SD_, RM2);
6246 dstreg1 = translate_rreg (SD_, RN1);
6247 dstreg2 = translate_rreg (SD_, RN2);
6249 result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6250 State.regs[dstreg2] -= State.regs[srcreg2];
6251 State.regs[dstreg1] = result1;
6254 // 1111 0111 0011 0110 imm4 Rn1 imm4 Rn2; sub_sub imm4, Rn1, imm4, Rn2
6255 8.0xf7+8.0x36+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_sub
6259 int dstreg1, dstreg2;
6263 dstreg1 = translate_rreg (SD_, RN1);
6264 dstreg2 = translate_rreg (SD_, RN2);
6266 result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6267 State.regs[dstreg2] -= EXTEND4 (IMM4);
6268 State.regs[dstreg1] = result1;
6271 // 1111 0111 0100 0110 imm4 Rn1 Rm2 Rn2; sub_cmp imm4, Rn1, Rm2, Rn2
6272 8.0xf7+8.0x46+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_cmp
6276 int srcreg2, dstreg1, dstreg2;
6280 srcreg2 = translate_rreg (SD_, RM2);
6281 dstreg1 = translate_rreg (SD_, RN1);
6282 dstreg2 = translate_rreg (SD_, RN2);
6284 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
6285 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6288 // 1111 0111 0101 0110 imm4 Rn1 imm4 Rn2; sub_cmp imm4, Rn1, imm4, Rn2
6289 8.0xf7+8.0x56+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_cmp
6293 int dstreg1, dstreg2;
6297 dstreg1 = translate_rreg (SD_, RN1);
6298 dstreg2 = translate_rreg (SD_, RN2);
6300 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
6301 State.regs[dstreg1] -= EXTEND4 (IMM4A);
6304 // 1111 0111 0110 0110 imm4 Rn1 Rm2 Rn2; sub_mov imm4, Rn1, Rm2, Rn2
6305 8.0xf7+8.0x66+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_mov
6309 int srcreg2, dstreg1, dstreg2;
6313 srcreg2 = translate_rreg (SD_, RM2);
6314 dstreg1 = translate_rreg (SD_, RN1);
6315 dstreg2 = translate_rreg (SD_, RN2);
6317 result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6318 State.regs[dstreg2] = State.regs[srcreg2];
6319 State.regs[dstreg1] = result1;
6322 // 1111 0111 0111 0110 imm4 Rn1 imm4 Rn2; sub_mov imm4, Rn1, imm4, Rn2
6323 8.0xf7+8.0x76+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_mov
6327 int dstreg1, dstreg2;
6331 dstreg1 = translate_rreg (SD_, RN1);
6332 dstreg2 = translate_rreg (SD_, RN2);
6334 result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6335 State.regs[dstreg2] = EXTEND4 (IMM4);
6336 State.regs[dstreg1] = result1;
6339 // 1111 0111 1000 0110 imm4 Rn1 Rm2 Rn2; sub_asr imm4, Rn1, Rm2, Rn2
6340 8.0xf7+8.0x86+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_asr
6344 int srcreg2, dstreg1, dstreg2;
6349 srcreg2 = translate_rreg (SD_, RM2);
6350 dstreg1 = translate_rreg (SD_, RN1);
6351 dstreg2 = translate_rreg (SD_, RN2);
6353 result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6354 temp = State.regs[dstreg2];
6355 temp >>= State.regs[srcreg2];
6356 State.regs[dstreg2] = temp;
6357 State.regs[dstreg1] = result1;
6360 // 1111 0111 1001 0110 imm4 Rn1 imm4 Rn2; sub_asr imm4, Rn1, imm4, Rn2
6361 8.0xf7+8.0x96+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_asr
6365 int dstreg1, dstreg2;
6370 dstreg1 = translate_rreg (SD_, RN1);
6371 dstreg2 = translate_rreg (SD_, RN2);
6373 result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6374 temp = State.regs[dstreg2];
6376 State.regs[dstreg2] = temp;
6377 State.regs[dstreg1] = result1;
6380 // 1111 0111 1010 0110 imm4 Rn1 Rm2 Rn2; sub_lsr imm4, Rn1, Rm2, Rn2
6381 8.0xf7+8.0xa6+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_lsr
6385 int srcreg2, dstreg1, dstreg2;
6389 srcreg2 = translate_rreg (SD_, RM2);
6390 dstreg1 = translate_rreg (SD_, RN1);
6391 dstreg2 = translate_rreg (SD_, RN2);
6393 result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6394 State.regs[dstreg2] >>= State.regs[srcreg2];
6395 State.regs[dstreg1] = result1;
6398 // 1111 0111 1011 0110 imm4 Rn1 imm4 Rn2; sub_lsr imm4, Rn1, imm4, Rn2
6399 8.0xf7+8.0xb6+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_lsr
6403 int dstreg1, dstreg2;
6408 dstreg1 = translate_rreg (SD_, RN1);
6409 dstreg2 = translate_rreg (SD_, RN2);
6411 result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6412 State.regs[dstreg2] >>= IMM4;
6413 State.regs[dstreg1] = result1;
6417 // 1111 0111 1100 0110 imm4 Rn1 Rm2 Rn2; sub_asl imm4, Rn1, Rm2, Rn2
6418 8.0xf7+8.0xc6+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_asl
6422 int srcreg2, dstreg1, dstreg2;
6426 srcreg2 = translate_rreg (SD_, RM2);
6427 dstreg1 = translate_rreg (SD_, RN1);
6428 dstreg2 = translate_rreg (SD_, RN2);
6430 result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6431 State.regs[dstreg2] <<= State.regs[srcreg2];
6432 State.regs[dstreg1] = result1;
6435 // 1111 0111 1101 0110 imm4 Rn1 imm4 Rn2; sub_asl imm4, Rn1, imm4, Rn2
6436 8.0xf7+8.0xd6+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_asl
6440 int dstreg1, dstreg2;
6445 dstreg1 = translate_rreg (SD_, RN1);
6446 dstreg2 = translate_rreg (SD_, RN2);
6448 result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6449 State.regs[dstreg2] <<= IMM4;
6450 State.regs[dstreg1] = result1;
6453 // 1111 0111 0000 0111 imm4 Rn1 Rm2 Rn2; mov_add imm4, Rn1, Rm2, Rn2
6454 8.0xf7+8.0x07+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_add
6458 int srcreg2, dstreg1, dstreg2;
6462 srcreg2 = translate_rreg (SD_, RM2);
6463 dstreg1 = translate_rreg (SD_, RN1);
6464 dstreg2 = translate_rreg (SD_, RN2);
6466 result1 = EXTEND4 (IMM4A);
6467 State.regs[dstreg2] += State.regs[srcreg2];
6468 State.regs[dstreg1] = result1;
6471 // 1111 0111 0001 0111 imm4 Rn1 imm4 Rn2; mov_add imm4, Rn1, imm4, Rn2
6472 8.0xf7+8.0x17+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_add
6476 int dstreg1, dstreg2;
6480 dstreg1 = translate_rreg (SD_, RN1);
6481 dstreg2 = translate_rreg (SD_, RN2);
6483 result1 = EXTEND4 (IMM4A);
6484 State.regs[dstreg2] += EXTEND4 (IMM4);
6485 State.regs[dstreg1] = result1;
6488 // 1111 0111 0010 0111 imm4 Rn1 Rm2 Rn2; mov_sub imm4, Rn1, Rm2, Rn2
6489 8.0xf7+8.0x27+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_sub
6493 int srcreg2, dstreg1, dstreg2;
6497 srcreg2 = translate_rreg (SD_, RM2);
6498 dstreg1 = translate_rreg (SD_, RN1);
6499 dstreg2 = translate_rreg (SD_, RN2);
6501 result1 = EXTEND4 (IMM4A);
6502 State.regs[dstreg2] -= State.regs[srcreg2];
6503 State.regs[dstreg1] = result1;
6506 // 1111 0111 0011 0111 imm4 Rn1 imm4 Rn2; mov_sub imm4, Rn1, imm4, Rn2
6507 8.0xf7+8.0x37+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_sub
6511 int dstreg1, dstreg2;
6515 dstreg1 = translate_rreg (SD_, RN1);
6516 dstreg2 = translate_rreg (SD_, RN2);
6518 result1 = EXTEND4 (IMM4A);
6519 State.regs[dstreg2] -= EXTEND4 (IMM4);
6520 State.regs[dstreg1] = result1;
6523 // 1111 0111 0100 0111 imm4 Rn1 Rm2 Rn2; mov_cmp imm4, Rn1, Rm2, Rn2
6524 8.0xf7+8.0x47+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_cmp
6528 int srcreg2, dstreg1, dstreg2;
6531 srcreg2 = translate_rreg (SD_, RM2);
6532 dstreg1 = translate_rreg (SD_, RN1);
6533 dstreg2 = translate_rreg (SD_, RN2);
6535 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
6536 State.regs[dstreg1] = EXTEND4 (IMM4A);
6539 // 1111 0111 0101 0111 imm4 Rn1 imm4 Rn2; mov_cmp imm4, Rn1, imm4, Rn2
6540 8.0xf7+8.0x57+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_cmp
6544 int dstreg1, dstreg2;
6547 dstreg1 = translate_rreg (SD_, RN1);
6548 dstreg2 = translate_rreg (SD_, RN2);
6550 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
6551 State.regs[dstreg1] = EXTEND4 (IMM4A);
6554 // 1111 0111 0110 0111 imm4 Rn1 Rm2 Rn2; mov_mov imm4, Rn1, Rm2, Rn2
6555 8.0xf7+8.0x67+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_mov
6559 int srcreg2, dstreg1, dstreg2;
6563 srcreg2 = translate_rreg (SD_, RM2);
6564 dstreg1 = translate_rreg (SD_, RN1);
6565 dstreg2 = translate_rreg (SD_, RN2);
6567 result1 = EXTEND4 (IMM4A);
6568 State.regs[dstreg2] = State.regs[srcreg2];
6569 State.regs[dstreg1] = result1;
6572 // 1111 0111 0111 0111 imm4 Rn1 imm4 Rn2; mov_mov imm4, Rn1, imm4, Rn2
6573 8.0xf7+8.0x77+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_mov
6577 int dstreg1, dstreg2;
6581 dstreg1 = translate_rreg (SD_, RN1);
6582 dstreg2 = translate_rreg (SD_, RN2);
6584 result1 = EXTEND4 (IMM4A);
6585 State.regs[dstreg2] = EXTEND4 (IMM4);
6586 State.regs[dstreg1] = result1;
6589 // 1111 0111 1000 0111 imm4 Rn1 Rm2 Rn2; mov_asr imm4, Rn1, Rm2, Rn2
6590 8.0xf7+8.0x87+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_asr
6594 int srcreg2, dstreg1, dstreg2;
6599 srcreg2 = translate_rreg (SD_, RM2);
6600 dstreg1 = translate_rreg (SD_, RN1);
6601 dstreg2 = translate_rreg (SD_, RN2);
6603 result1 = EXTEND4 (IMM4A);
6604 temp = State.regs[dstreg2];
6605 temp >>= State.regs[srcreg2];
6606 State.regs[dstreg2] = temp;
6607 State.regs[dstreg1] = result1;
6610 // 1111 0111 1001 0111 imm4 Rn1 imm4 Rn2; mov_asr imm4, Rn1, imm4, Rn2
6611 8.0xf7+8.0x97+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_asr
6615 int dstreg1, dstreg2;
6620 dstreg1 = translate_rreg (SD_, RN1);
6621 dstreg2 = translate_rreg (SD_, RN2);
6623 result1 = EXTEND4 (IMM4A);
6624 temp = State.regs[dstreg2];
6626 State.regs[dstreg2] = temp;
6627 State.regs[dstreg1] = result1;
6630 // 1111 0111 1010 0111 imm4 Rn1 Rm2 Rn2; mov_lsr imm4, Rn1, Rm2, Rn2
6631 8.0xf7+8.0xa7+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_lsr
6635 int srcreg2, dstreg1, dstreg2;
6639 srcreg2 = translate_rreg (SD_, RM2);
6640 dstreg1 = translate_rreg (SD_, RN1);
6641 dstreg2 = translate_rreg (SD_, RN2);
6643 result1 = EXTEND4 (IMM4A);
6644 State.regs[dstreg2] >>= State.regs[srcreg2];
6645 State.regs[dstreg1] = result1;
6648 // 1111 0111 1011 0111 imm4 Rn1 imm4 Rn2; mov_lsr imm4, Rn1, imm4, Rn2
6649 8.0xf7+8.0xb7+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_lsr
6653 int dstreg1, dstreg2;
6658 dstreg1 = translate_rreg (SD_, RN1);
6659 dstreg2 = translate_rreg (SD_, RN2);
6661 result1 = EXTEND4 (IMM4A);
6662 State.regs[dstreg2] >>= IMM4;
6663 State.regs[dstreg1] = result1;
6667 // 1111 0111 1100 0111 imm4 Rn1 Rm2 Rn2; mov_asl imm4, Rn1, Rm2, Rn2
6668 8.0xf7+8.0xc7+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_asl
6672 int srcreg2, dstreg1, dstreg2;
6676 srcreg2 = translate_rreg (SD_, RM2);
6677 dstreg1 = translate_rreg (SD_, RN1);
6678 dstreg2 = translate_rreg (SD_, RN2);
6680 result1 = EXTEND4 (IMM4A);
6681 State.regs[dstreg2] <<= State.regs[srcreg2];
6682 State.regs[dstreg1] = result1;
6685 // 1111 0111 1101 0111 imm4 Rn1 imm4 Rn2; mov_asl imm4, Rn1, imm4, Rn2
6686 8.0xf7+8.0xd7+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_asl
6690 int dstreg1, dstreg2;
6695 dstreg1 = translate_rreg (SD_, RN1);
6696 dstreg2 = translate_rreg (SD_, RN2);
6698 result1 = EXTEND4 (IMM4A);
6699 State.regs[dstreg2] <<= IMM4;
6700 State.regs[dstreg1] = result1;
6703 // 1111 0111 0000 1000 Rm1 Rn1 Rm2 Rn2; and_add Rm1, Rn1, Rm2, Rn2
6704 8.0xf7+8.0x08+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_add
6708 int srcreg1, srcreg2, dstreg1, dstreg2;
6712 srcreg1 = translate_rreg (SD_, RM1);
6713 srcreg2 = translate_rreg (SD_, RM2);
6714 dstreg1 = translate_rreg (SD_, RN1);
6715 dstreg2 = translate_rreg (SD_, RN2);
6717 result1 = State.regs[dstreg1] & State.regs[srcreg1];
6718 State.regs[dstreg2] += State.regs[srcreg2];
6719 State.regs[dstreg1] = result1;
6722 // 1111 0111 0001 1000 Rm1 Rn1 imm4 Rn2; and_add Rm1, Rn1, imm4, Rn2
6723 8.0xf7+8.0x18+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_add
6727 int srcreg1, dstreg1, dstreg2;
6731 srcreg1 = translate_rreg (SD_, RM1);
6732 dstreg1 = translate_rreg (SD_, RN1);
6733 dstreg2 = translate_rreg (SD_, RN2);
6735 result1 = State.regs[dstreg1] & State.regs[srcreg1];
6736 State.regs[dstreg2] += EXTEND4 (IMM4);
6737 State.regs[dstreg1] = result1;
6740 // 1111 0111 0010 1000 Rm1 Rn1 Rm2 Rn2; and_sub Rm1, Rn1, Rm2, Rn2
6741 8.0xf7+8.0x28+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_sub
6745 int srcreg1, srcreg2, dstreg1, dstreg2;
6749 srcreg1 = translate_rreg (SD_, RM1);
6750 srcreg2 = translate_rreg (SD_, RM2);
6751 dstreg1 = translate_rreg (SD_, RN1);
6752 dstreg2 = translate_rreg (SD_, RN2);
6754 result1 = State.regs[dstreg1] & State.regs[srcreg1];
6755 State.regs[dstreg2] -= State.regs[srcreg2];
6756 State.regs[dstreg1] = result1;
6759 // 1111 0111 0011 1000 Rm1 Rn1 imm4 Rn2; and_sub Rm1, Rn1, imm4, Rn2
6760 8.0xf7+8.0x38+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_sub
6764 int srcreg1, dstreg1, dstreg2;
6768 srcreg1 = translate_rreg (SD_, RM1);
6769 dstreg1 = translate_rreg (SD_, RN1);
6770 dstreg2 = translate_rreg (SD_, RN2);
6772 result1 = State.regs[dstreg1] & State.regs[srcreg1];
6773 State.regs[dstreg2] -= EXTEND4 (IMM4);
6774 State.regs[dstreg1] = result1;
6777 // 1111 0111 0100 1000 Rm1 Rn1 Rm2 Rn2; and_cmp Rm1, Rn1, Rm2, Rn2
6778 8.0xf7+8.0x48+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_cmp
6782 int srcreg1, srcreg2, dstreg1, dstreg2;
6785 srcreg1 = translate_rreg (SD_, RM1);
6786 srcreg2 = translate_rreg (SD_, RM2);
6787 dstreg1 = translate_rreg (SD_, RN1);
6788 dstreg2 = translate_rreg (SD_, RN2);
6790 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
6791 State.regs[dstreg1] &= State.regs[srcreg1];
6794 // 1111 0111 0101 1000 Rm1 Rn1 imm4 Rn2; and_cmp Rm1, Rn1, imm4, Rn2
6795 8.0xf7+8.0x58+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_cmp
6799 int srcreg1, dstreg1, dstreg2;
6802 srcreg1 = translate_rreg (SD_, RM1);
6803 dstreg1 = translate_rreg (SD_, RN1);
6804 dstreg2 = translate_rreg (SD_, RN2);
6806 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
6807 State.regs[dstreg1] &= State.regs[srcreg1];
6810 // 1111 0111 0110 1000 Rm1 Rn1 Rm2 Rn2; and_mov Rm1, Rn1, Rm2, Rn2
6811 8.0xf7+8.0x68+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_mov
6815 int srcreg1, srcreg2, dstreg1, dstreg2;
6819 srcreg1 = translate_rreg (SD_, RM1);
6820 srcreg2 = translate_rreg (SD_, RM2);
6821 dstreg1 = translate_rreg (SD_, RN1);
6822 dstreg2 = translate_rreg (SD_, RN2);
6824 result1 = State.regs[dstreg1] & State.regs[srcreg1];
6825 State.regs[dstreg2] = State.regs[srcreg2];
6826 State.regs[dstreg1] = result1;
6829 // 1111 0111 0111 1000 Rm1 Rn1 imm4 Rn2; and_mov Rm1, Rn1, imm4, Rn2
6830 8.0xf7+8.0x78+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_mov
6834 int srcreg1, dstreg1, dstreg2;
6838 srcreg1 = translate_rreg (SD_, RM1);
6839 dstreg1 = translate_rreg (SD_, RN1);
6840 dstreg2 = translate_rreg (SD_, RN2);
6842 result1 = State.regs[dstreg1] & State.regs[srcreg1];
6843 State.regs[dstreg2] = EXTEND4 (IMM4);
6844 State.regs[dstreg1] = result1;
6847 // 1111 0111 1000 1000 Rm1 Rn1 Rm2 Rn2; and_asr Rm1, Rn1, Rm2, Rn2
6848 8.0xf7+8.0x88+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_asr
6852 int srcreg1, srcreg2, dstreg1, dstreg2;
6857 srcreg1 = translate_rreg (SD_, RM1);
6858 srcreg2 = translate_rreg (SD_, RM2);
6859 dstreg1 = translate_rreg (SD_, RN1);
6860 dstreg2 = translate_rreg (SD_, RN2);
6862 result1 = State.regs[dstreg1] & State.regs[srcreg1];
6863 temp = State.regs[dstreg2];
6864 temp >>= State.regs[srcreg2];
6865 State.regs[dstreg2] = temp;
6866 State.regs[dstreg1] = result1;
6869 // 1111 0111 1001 1000 Rm1 Rn1 imm4 Rn2; and_asr Rm1, Rn1, imm4, Rn2
6870 8.0xf7+8.0x98+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_asr
6874 int srcreg1, dstreg1, dstreg2;
6879 srcreg1 = translate_rreg (SD_, RM1);
6880 dstreg1 = translate_rreg (SD_, RN1);
6881 dstreg2 = translate_rreg (SD_, RN2);
6883 result1 = State.regs[dstreg1] & State.regs[srcreg1];
6884 temp = State.regs[dstreg2];
6886 State.regs[dstreg2] = temp;
6887 State.regs[dstreg1] = result1;
6890 // 1111 0111 1010 1000 Rm1 Rn1 Rm2 Rn2; and_lsr Rm1, Rn1, Rm2, Rn2
6891 8.0xf7+8.0xa8+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_lsr
6895 int srcreg1, srcreg2, dstreg1, dstreg2;
6899 srcreg1 = translate_rreg (SD_, RM1);
6900 srcreg2 = translate_rreg (SD_, RM2);
6901 dstreg1 = translate_rreg (SD_, RN1);
6902 dstreg2 = translate_rreg (SD_, RN2);
6904 result1 = State.regs[dstreg1] & State.regs[srcreg1];
6905 State.regs[dstreg2] >>= State.regs[srcreg2];
6906 State.regs[dstreg1] = result1;
6909 // 1111 0111 1011 1000 Rm1 Rn1 imm4 Rn2; and_lsr Rm1, Rn1, imm4, Rn2
6910 8.0xf7+8.0xb8+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_lsr
6914 int srcreg1, dstreg1, dstreg2;
6919 srcreg1 = translate_rreg (SD_, RM1);
6920 dstreg1 = translate_rreg (SD_, RN1);
6921 dstreg2 = translate_rreg (SD_, RN2);
6923 result1 = State.regs[dstreg1] & State.regs[srcreg1];
6924 State.regs[dstreg2] >>= IMM4;
6925 State.regs[dstreg1] = result1;
6929 // 1111 0111 1100 1000 Rm1 Rn1 Rm2 Rn2; and_asl Rm1, Rn1, Rm2, Rn2
6930 8.0xf7+8.0xc8+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_asl
6934 int srcreg1, srcreg2, dstreg1, dstreg2;
6938 srcreg1 = translate_rreg (SD_, RM1);
6939 srcreg2 = translate_rreg (SD_, RM2);
6940 dstreg1 = translate_rreg (SD_, RN1);
6941 dstreg2 = translate_rreg (SD_, RN2);
6943 result1 = State.regs[dstreg1] & State.regs[srcreg1];
6944 State.regs[dstreg2] <<= State.regs[srcreg2];
6945 State.regs[dstreg1] = result1;
6948 // 1111 0111 1101 1000 Rm1 Rn1 imm4 Rn2; and_asl Rm1, Rn1, imm4, Rn2
6949 8.0xf7+8.0xd8+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_asl
6953 int srcreg1, dstreg1, dstreg2;
6958 srcreg1 = translate_rreg (SD_, RM1);
6959 dstreg1 = translate_rreg (SD_, RN1);
6960 dstreg2 = translate_rreg (SD_, RN2);
6962 result1 = State.regs[dstreg1] & State.regs[srcreg1];
6963 State.regs[dstreg2] <<= IMM4;
6964 State.regs[dstreg1] = result1;
6967 // 1111 0111 0000 1001 Rm1 Rn1 Rm2 Rn2; dmach_add Rm1, Rn1, Rm2, Rn2
6968 8.0xf7+8.0x09+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_add
6972 int srcreg1, srcreg2, dstreg1, dstreg2;
6973 long temp, temp2, sum;
6976 srcreg1 = translate_rreg (SD_, RM1);
6977 srcreg2 = translate_rreg (SD_, RM2);
6978 dstreg1 = translate_rreg (SD_, RN1);
6979 dstreg2 = translate_rreg (SD_, RN2);
6981 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
6982 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
6983 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
6984 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
6985 sum = temp + temp2 + State.regs[REG_MCRL];
6987 State.regs[dstreg2] += State.regs[srcreg2];
6988 State.regs[dstreg1] = sum;
6991 // 1111 0111 0001 1001 Rm1 Rn1 imm4 Rn2; dmach_add Rm1, Rn1, imm4, Rn2
6992 8.0xf7+8.0x19+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_add
6996 int srcreg1, dstreg1, dstreg2;
6997 long temp, temp2, sum;
7000 srcreg1 = translate_rreg (SD_, RM1);
7001 dstreg1 = translate_rreg (SD_, RN1);
7002 dstreg2 = translate_rreg (SD_, RN2);
7004 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7005 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7006 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7007 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7008 sum = temp + temp2 + State.regs[REG_MCRL];
7010 State.regs[dstreg2] += EXTEND4 (IMM4);
7011 State.regs[dstreg1] = sum;
7014 // 1111 0111 0010 1001 Rm1 Rn1 Rm2 Rn2; dmach_sub Rm1, Rn1, Rm2, Rn2
7015 8.0xf7+8.0x29+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_sub
7019 int srcreg1, srcreg2, dstreg1, dstreg2;
7020 long temp, temp2, sum;
7023 srcreg1 = translate_rreg (SD_, RM1);
7024 srcreg2 = translate_rreg (SD_, RM2);
7025 dstreg1 = translate_rreg (SD_, RN1);
7026 dstreg2 = translate_rreg (SD_, RN2);
7028 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7029 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7030 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7031 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7032 sum = temp + temp2 + State.regs[REG_MCRL];
7034 State.regs[dstreg2] -= State.regs[srcreg2];
7035 State.regs[dstreg1] = sum;
7038 // 1111 0111 0011 1001 Rm1 Rn1 imm4 Rn2; dmach_sub Rm1, Rn1, imm4, Rn2
7039 8.0xf7+8.0x39+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_sub
7043 int srcreg1, dstreg1, dstreg2;
7044 long temp, temp2, sum;
7047 srcreg1 = translate_rreg (SD_, RM1);
7048 dstreg1 = translate_rreg (SD_, RN1);
7049 dstreg2 = translate_rreg (SD_, RN2);
7051 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7052 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7053 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7054 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7055 sum = temp + temp2 + State.regs[REG_MCRL];
7057 State.regs[dstreg2] -= EXTEND4 (IMM4);
7058 State.regs[dstreg1] = sum;
7061 // 1111 0111 0100 1001 Rm1 Rn1 Rm2 Rn2; dmach_cmp Rm1, Rn1, Rm2, Rn2
7062 8.0xf7+8.0x49+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_cmp
7066 int srcreg1, srcreg2, dstreg1, dstreg2;
7067 long temp, temp2, sum;
7070 srcreg1 = translate_rreg (SD_, RM1);
7071 srcreg2 = translate_rreg (SD_, RM2);
7072 dstreg1 = translate_rreg (SD_, RN1);
7073 dstreg2 = translate_rreg (SD_, RN2);
7075 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7076 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7077 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7078 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7079 sum = temp + temp2 + State.regs[REG_MCRL];
7081 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
7082 State.regs[dstreg1] = sum;
7085 // 1111 0111 0101 1001 Rm1 Rn1 imm4 Rn2; dmach_cmp Rm1, Rn1, imm4, Rn2
7086 8.0xf7+8.0x59+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_cmp
7090 int srcreg1, dstreg1, dstreg2;
7091 long temp, temp2, sum;
7094 srcreg1 = translate_rreg (SD_, RM1);
7095 dstreg1 = translate_rreg (SD_, RN1);
7096 dstreg2 = translate_rreg (SD_, RN2);
7098 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7099 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7100 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7101 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7102 sum = temp + temp2 + State.regs[REG_MCRL];
7104 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
7105 State.regs[dstreg1] = sum;
7108 // 1111 0111 0110 1001 Rm1 Rn1 Rm2 Rn2; dmach_mov Rm1, Rn1, Rm2, Rn2
7109 8.0xf7+8.0x69+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_mov
7113 int srcreg1, srcreg2, dstreg1, dstreg2;
7114 long temp, temp2, sum;
7117 srcreg1 = translate_rreg (SD_, RM1);
7118 srcreg2 = translate_rreg (SD_, RM2);
7119 dstreg1 = translate_rreg (SD_, RN1);
7120 dstreg2 = translate_rreg (SD_, RN2);
7122 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7123 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7124 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7125 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7126 sum = temp + temp2 + State.regs[REG_MCRL];
7128 State.regs[dstreg2] = State.regs[srcreg2];
7129 State.regs[dstreg1] = sum;
7132 // 1111 0111 0111 1001 Rm1 Rn1 imm4 Rn2; dmach_mov Rm1, Rn1, imm4, Rn2
7133 8.0xf7+8.0x79+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_mov
7137 int srcreg1, dstreg1, dstreg2;
7138 long temp, temp2, sum;
7141 srcreg1 = translate_rreg (SD_, RM1);
7142 dstreg1 = translate_rreg (SD_, RN1);
7143 dstreg2 = translate_rreg (SD_, RN2);
7145 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7146 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7147 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7148 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7149 sum = temp + temp2 + State.regs[REG_MCRL];
7151 State.regs[dstreg2] = EXTEND4 (IMM4);
7152 State.regs[dstreg1] = sum;
7155 // 1111 0111 1000 1001 Rm1 Rn1 Rm2 Rn2; dmach_asr Rm1, Rn1, Rm2, Rn2
7156 8.0xf7+8.0x89+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_asr
7160 int srcreg1, srcreg2, dstreg1, dstreg2;
7161 long temp, temp2, sum;
7164 srcreg1 = translate_rreg (SD_, RM1);
7165 srcreg2 = translate_rreg (SD_, RM2);
7166 dstreg1 = translate_rreg (SD_, RN1);
7167 dstreg2 = translate_rreg (SD_, RN2);
7169 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7170 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7171 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7172 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7173 sum = temp + temp2 + State.regs[REG_MCRL];
7175 temp = State.regs[dstreg2];
7176 temp >>= State.regs[srcreg2];
7177 State.regs[dstreg2] = temp;
7178 State.regs[dstreg1] = sum;
7181 // 1111 0111 1001 1001 Rm1 Rn1 imm4 Rn2; dmach_asr Rm1, Rn1, imm4, Rn2
7182 8.0xf7+8.0x99+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_asr
7186 int srcreg1, dstreg1, dstreg2;
7187 long temp, temp2, sum;
7190 srcreg1 = translate_rreg (SD_, RM1);
7191 dstreg1 = translate_rreg (SD_, RN1);
7192 dstreg2 = translate_rreg (SD_, RN2);
7194 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7195 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7196 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7197 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7198 sum = temp + temp2 + State.regs[REG_MCRL];
7200 temp = State.regs[dstreg2];
7202 State.regs[dstreg2] = temp;
7203 State.regs[dstreg1] = sum;
7206 // 1111 0111 1010 1001 Rm1 Rn1 Rm2 Rn2; dmach_lsr Rm1, Rn1, Rm2, Rn2
7207 8.0xf7+8.0xa9+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_lsr
7211 int srcreg1, srcreg2, dstreg1, dstreg2;
7212 long temp, temp2, sum;
7215 srcreg1 = translate_rreg (SD_, RM1);
7216 srcreg2 = translate_rreg (SD_, RM2);
7217 dstreg1 = translate_rreg (SD_, RN1);
7218 dstreg2 = translate_rreg (SD_, RN2);
7220 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7221 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7222 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7223 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7224 sum = temp + temp2 + State.regs[REG_MCRL];
7226 State.regs[dstreg2] >>= State.regs[srcreg2];
7227 State.regs[dstreg1] = sum;
7230 // 1111 0111 1011 1001 Rm1 Rn1 imm4 Rn2; dmach_lsr Rm1, Rn1, imm4, Rn2
7231 8.0xf7+8.0xb9+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_lsr
7235 int srcreg1, dstreg1, dstreg2;
7236 long temp, temp2, sum;
7239 srcreg1 = translate_rreg (SD_, RM1);
7240 dstreg1 = translate_rreg (SD_, RN1);
7241 dstreg2 = translate_rreg (SD_, RN2);
7243 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7244 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7245 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7246 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7247 sum = temp + temp2 + State.regs[REG_MCRL];
7249 State.regs[dstreg2] >>= IMM4;
7250 State.regs[dstreg1] = sum;
7254 // 1111 0111 1100 1001 Rm1 Rn1 Rm2 Rn2; dmach_asl Rm1, Rn1, Rm2, Rn2
7255 8.0xf7+8.0xc9+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_asl
7259 int srcreg1, srcreg2, dstreg1, dstreg2;
7260 long temp, temp2, sum;
7263 srcreg1 = translate_rreg (SD_, RM1);
7264 srcreg2 = translate_rreg (SD_, RM2);
7265 dstreg1 = translate_rreg (SD_, RN1);
7266 dstreg2 = translate_rreg (SD_, RN2);
7268 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7269 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7270 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7271 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7272 sum = temp + temp2 + State.regs[REG_MCRL];
7274 State.regs[dstreg2] <<= State.regs[srcreg2];
7275 State.regs[dstreg1] = sum;
7278 // 1111 0111 1101 1001 Rm1 Rn1 imm4 Rn2; dmach_asl Rm1, Rn1, imm4, Rn2
7279 8.0xf7+8.0xd9+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_asl
7283 int srcreg1, dstreg1, dstreg2;
7284 long temp, temp2, sum;
7287 srcreg1 = translate_rreg (SD_, RM1);
7288 dstreg1 = translate_rreg (SD_, RN1);
7289 dstreg2 = translate_rreg (SD_, RN2);
7291 temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7292 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7293 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7294 * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7295 sum = temp + temp2 + State.regs[REG_MCRL];
7297 State.regs[dstreg2] <<= IMM4;
7298 State.regs[dstreg1] = sum;
7301 // 1111 0111 0000 1010 Rm1 Rn1 Rm2 Rn2; xor_add Rm1, Rn1, Rm2, Rn2
7302 8.0xf7+8.0x0a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_add
7306 int srcreg1, srcreg2, dstreg1, dstreg2;
7310 srcreg1 = translate_rreg (SD_, RM1);
7311 srcreg2 = translate_rreg (SD_, RM2);
7312 dstreg1 = translate_rreg (SD_, RN1);
7313 dstreg2 = translate_rreg (SD_, RN2);
7315 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7316 State.regs[dstreg2] += State.regs[srcreg2];
7317 State.regs[dstreg1] = result1;
7320 // 1111 0111 0001 1010 Rm1 Rn1 imm4 Rn2; xor_add Rm1, Rn1, imm4, Rn2
7321 8.0xf7+8.0x1a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_add
7325 int srcreg1, dstreg1, dstreg2;
7329 srcreg1 = translate_rreg (SD_, RM1);
7330 dstreg1 = translate_rreg (SD_, RN1);
7331 dstreg2 = translate_rreg (SD_, RN2);
7333 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7334 State.regs[dstreg2] += EXTEND4 (IMM4);
7335 State.regs[dstreg1] = result1;
7338 // 1111 0111 0010 1010 Rm1 Rn1 Rm2 Rn2; xor_sub Rm1, Rn1, Rm2, Rn2
7339 8.0xf7+8.0x2a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_sub
7343 int srcreg1, srcreg2, dstreg1, dstreg2;
7347 srcreg1 = translate_rreg (SD_, RM1);
7348 srcreg2 = translate_rreg (SD_, RM2);
7349 dstreg1 = translate_rreg (SD_, RN1);
7350 dstreg2 = translate_rreg (SD_, RN2);
7352 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7353 State.regs[dstreg2] -= State.regs[srcreg2];
7354 State.regs[dstreg1] = result1;
7357 // 1111 0111 0011 1010 Rm1 Rn1 imm4 Rn2; xor_sub Rm1, Rn1, imm4, Rn2
7358 8.0xf7+8.0x3a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_sub
7362 int srcreg1, dstreg1, dstreg2;
7366 srcreg1 = translate_rreg (SD_, RM1);
7367 dstreg1 = translate_rreg (SD_, RN1);
7368 dstreg2 = translate_rreg (SD_, RN2);
7370 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7371 State.regs[dstreg2] -= EXTEND4 (IMM4);
7372 State.regs[dstreg1] = result1;
7375 // 1111 0111 0100 1010 Rm1 Rn1 Rm2 Rn2; xor_cmp Rm1, Rn1, Rm2, Rn2
7376 8.0xf7+8.0x4a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_cmp
7380 int srcreg1, srcreg2, dstreg1, dstreg2;
7383 srcreg1 = translate_rreg (SD_, RM1);
7384 srcreg2 = translate_rreg (SD_, RM2);
7385 dstreg1 = translate_rreg (SD_, RN1);
7386 dstreg2 = translate_rreg (SD_, RN2);
7388 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
7389 State.regs[dstreg1] ^= State.regs[srcreg1];
7392 // 1111 0111 0101 1010 Rm1 Rn1 imm4 Rn2; xor_cmp Rm1, Rn1, imm4, Rn2
7393 8.0xf7+8.0x5a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_cmp
7397 int srcreg1, dstreg1, dstreg2;
7400 srcreg1 = translate_rreg (SD_, RM1);
7401 dstreg1 = translate_rreg (SD_, RN1);
7402 dstreg2 = translate_rreg (SD_, RN2);
7404 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
7405 State.regs[dstreg1] ^= State.regs[srcreg1];
7408 // 1111 0111 0110 1010 Rm1 Rn1 Rm2 Rn2; xor_mov Rm1, Rn1, Rm2, Rn2
7409 8.0xf7+8.0x6a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_mov
7413 int srcreg1, srcreg2, dstreg1, dstreg2;
7417 srcreg1 = translate_rreg (SD_, RM1);
7418 srcreg2 = translate_rreg (SD_, RM2);
7419 dstreg1 = translate_rreg (SD_, RN1);
7420 dstreg2 = translate_rreg (SD_, RN2);
7422 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7423 State.regs[dstreg2] = State.regs[srcreg2];
7424 State.regs[dstreg1] = result1;
7427 // 1111 0111 0111 1010 Rm1 Rn1 imm4 Rn2; xor_mov Rm1, Rn1, imm4, Rn2
7428 8.0xf7+8.0x7a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_mov
7432 int srcreg1, dstreg1, dstreg2;
7436 srcreg1 = translate_rreg (SD_, RM1);
7437 dstreg1 = translate_rreg (SD_, RN1);
7438 dstreg2 = translate_rreg (SD_, RN2);
7440 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7441 State.regs[dstreg2] = EXTEND4 (IMM4);
7442 State.regs[dstreg1] = result1;
7445 // 1111 0111 1000 1010 Rm1 Rn1 Rm2 Rn2; xor_asr Rm1, Rn1, Rm2, Rn2
7446 8.0xf7+8.0x8a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_asr
7450 int srcreg1, srcreg2, dstreg1, dstreg2;
7455 srcreg1 = translate_rreg (SD_, RM1);
7456 srcreg2 = translate_rreg (SD_, RM2);
7457 dstreg1 = translate_rreg (SD_, RN1);
7458 dstreg2 = translate_rreg (SD_, RN2);
7460 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7461 temp = State.regs[dstreg2];
7462 temp >>= State.regs[srcreg2];
7463 State.regs[dstreg2] = temp;
7464 State.regs[dstreg1] = result1;
7467 // 1111 0111 1001 1010 Rm1 Rn1 imm4 Rn2; xor_asr Rm1, Rn1, imm4, Rn2
7468 8.0xf7+8.0x9a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_asr
7472 int srcreg1, dstreg1, dstreg2;
7477 srcreg1 = translate_rreg (SD_, RM1);
7478 dstreg1 = translate_rreg (SD_, RN1);
7479 dstreg2 = translate_rreg (SD_, RN2);
7481 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7482 temp = State.regs[dstreg2];
7484 State.regs[dstreg2] = temp;
7485 State.regs[dstreg1] = result1;
7488 // 1111 0111 1010 1010 Rm1 Rn1 Rm2 Rn2; xor_lsr Rm1, Rn1, Rm2, Rn2
7489 8.0xf7+8.0xaa+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_lsr
7493 int srcreg1, srcreg2, dstreg1, dstreg2;
7497 srcreg1 = translate_rreg (SD_, RM1);
7498 srcreg2 = translate_rreg (SD_, RM2);
7499 dstreg1 = translate_rreg (SD_, RN1);
7500 dstreg2 = translate_rreg (SD_, RN2);
7502 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7503 State.regs[dstreg2] >>= State.regs[srcreg2];
7504 State.regs[dstreg1] = result1;
7507 // 1111 0111 1011 1010 Rm1 Rn1 imm4 Rn2; xor_lsr Rm1, Rn1, imm4, Rn2
7508 8.0xf7+8.0xba+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_lsr
7512 int srcreg1, dstreg1, dstreg2;
7517 srcreg1 = translate_rreg (SD_, RM1);
7518 dstreg1 = translate_rreg (SD_, RN1);
7519 dstreg2 = translate_rreg (SD_, RN2);
7521 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7522 State.regs[dstreg2] >>= IMM4;
7523 State.regs[dstreg1] = result1;
7527 // 1111 0111 1100 1010 Rm1 Rn1 Rm2 Rn2; xor_asl Rm1, Rn1, Rm2, Rn2
7528 8.0xf7+8.0xca+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_asl
7532 int srcreg1, srcreg2, dstreg1, dstreg2;
7536 srcreg1 = translate_rreg (SD_, RM1);
7537 srcreg2 = translate_rreg (SD_, RM2);
7538 dstreg1 = translate_rreg (SD_, RN1);
7539 dstreg2 = translate_rreg (SD_, RN2);
7541 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7542 State.regs[dstreg2] <<= State.regs[srcreg2];
7543 State.regs[dstreg1] = result1;
7546 // 1111 0111 1101 1010 Rm1 Rn1 imm4 Rn2; xor_asl Rm1, Rn1, imm4, Rn2
7547 8.0xf7+8.0xda+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_asl
7551 int srcreg1, dstreg1, dstreg2;
7556 srcreg1 = translate_rreg (SD_, RM1);
7557 dstreg1 = translate_rreg (SD_, RN1);
7558 dstreg2 = translate_rreg (SD_, RN2);
7560 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7561 State.regs[dstreg2] <<= IMM4;
7562 State.regs[dstreg1] = result1;
7565 // 1111 0111 0000 1011 Rm1 Rn1 Rm2 Rn2; swhw_add Rm1, Rn1, Rm2, Rn2
7566 8.0xf7+8.0x0b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_add
7570 int srcreg1, srcreg2, dstreg1, dstreg2;
7574 srcreg1 = translate_rreg (SD_, RM1);
7575 srcreg2 = translate_rreg (SD_, RM2);
7576 dstreg1 = translate_rreg (SD_, RN1);
7577 dstreg2 = translate_rreg (SD_, RN2);
7579 result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7580 State.regs[dstreg2] += State.regs[srcreg2];
7581 State.regs[dstreg1] = result1;
7584 // 1111 0111 0001 1011 Rm1 Rn1 imm4 Rn2; swhw_add Rm1, Rn1, imm4, Rn2
7585 8.0xf7+8.0x1b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_add
7589 int srcreg1, dstreg1, dstreg2;
7593 srcreg1 = translate_rreg (SD_, RM1);
7594 dstreg1 = translate_rreg (SD_, RN1);
7595 dstreg2 = translate_rreg (SD_, RN2);
7597 result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7598 | ((State.regs[srcreg1] >> 16) & 0xffff));
7599 State.regs[dstreg2] += EXTEND4 (IMM4);
7600 State.regs[dstreg1] = result1;
7603 // 1111 0111 0010 1011 Rm1 Rn1 Rm2 Rn2; swhw_sub Rm1, Rn1, Rm2, Rn2
7604 8.0xf7+8.0x2b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_sub
7608 int srcreg1, srcreg2, dstreg1, dstreg2;
7612 srcreg1 = translate_rreg (SD_, RM1);
7613 srcreg2 = translate_rreg (SD_, RM2);
7614 dstreg1 = translate_rreg (SD_, RN1);
7615 dstreg2 = translate_rreg (SD_, RN2);
7617 result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7618 | ((State.regs[srcreg1] >> 16) & 0xffff));
7619 State.regs[dstreg2] -= State.regs[srcreg2];
7620 State.regs[dstreg1] = result1;
7623 // 1111 0111 0011 1011 Rm1 Rn1 imm4 Rn2; swhw_sub Rm1, Rn1, imm4, Rn2
7624 8.0xf7+8.0x3b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_sub
7628 int srcreg1, dstreg1, dstreg2;
7632 srcreg1 = translate_rreg (SD_, RM1);
7633 dstreg1 = translate_rreg (SD_, RN1);
7634 dstreg2 = translate_rreg (SD_, RN2);
7636 result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7637 | ((State.regs[srcreg1] >> 16) & 0xffff));
7638 State.regs[dstreg2] -= EXTEND4 (IMM4);
7639 State.regs[dstreg1] = result1;
7642 // 1111 0111 0100 1011 Rm1 Rn1 Rm2 Rn2; swhw_cmp Rm1, Rn1, Rm2, Rn2
7643 8.0xf7+8.0x4b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_cmp
7647 int srcreg1, srcreg2, dstreg1, dstreg2;
7650 srcreg1 = translate_rreg (SD_, RM1);
7651 srcreg2 = translate_rreg (SD_, RM2);
7652 dstreg1 = translate_rreg (SD_, RN1);
7653 dstreg2 = translate_rreg (SD_, RN2);
7655 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
7656 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7657 | ((State.regs[srcreg1] >> 16) & 0xffff));
7660 // 1111 0111 0101 1011 Rm1 Rn1 imm4 Rn2; swhw_cmp Rm1, Rn1, imm4, Rn2
7661 8.0xf7+8.0x5b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_cmp
7665 int srcreg1, dstreg1, dstreg2;
7668 srcreg1 = translate_rreg (SD_, RM1);
7669 dstreg1 = translate_rreg (SD_, RN1);
7670 dstreg2 = translate_rreg (SD_, RN2);
7672 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
7673 State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7674 | ((State.regs[srcreg1] >> 16) & 0xffff));
7677 // 1111 0111 0110 1011 Rm1 Rn1 Rm2 Rn2; swhw_mov Rm1, Rn1, Rm2, Rn2
7678 8.0xf7+8.0x6b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_mov
7682 int srcreg1, srcreg2, dstreg1, dstreg2;
7686 srcreg1 = translate_rreg (SD_, RM1);
7687 srcreg2 = translate_rreg (SD_, RM2);
7688 dstreg1 = translate_rreg (SD_, RN1);
7689 dstreg2 = translate_rreg (SD_, RN2);
7691 result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7692 | ((State.regs[srcreg1] >> 16) & 0xffff));
7693 State.regs[dstreg2] = State.regs[srcreg2];
7694 State.regs[dstreg1] = result1;
7697 // 1111 0111 0111 1011 Rm1 Rn1 imm4 Rn2; swhw_mov Rm1, Rn1, imm4, Rn2
7698 8.0xf7+8.0x7b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_mov
7702 int srcreg1, dstreg1, dstreg2;
7706 srcreg1 = translate_rreg (SD_, RM1);
7707 dstreg1 = translate_rreg (SD_, RN1);
7708 dstreg2 = translate_rreg (SD_, RN2);
7710 result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7711 | ((State.regs[srcreg1] >> 16) & 0xffff));
7712 State.regs[dstreg2] = EXTEND4 (IMM4);
7713 State.regs[dstreg1] = result1;
7716 // 1111 0111 1000 1011 Rm1 Rn1 Rm2 Rn2; swhw_asr Rm1, Rn1, Rm2, Rn2
7717 8.0xf7+8.0x8b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_asr
7721 int srcreg1, srcreg2, dstreg1, dstreg2;
7726 srcreg1 = translate_rreg (SD_, RM1);
7727 srcreg2 = translate_rreg (SD_, RM2);
7728 dstreg1 = translate_rreg (SD_, RN1);
7729 dstreg2 = translate_rreg (SD_, RN2);
7731 result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7732 | ((State.regs[srcreg1] >> 16) & 0xffff));
7733 temp = State.regs[dstreg2];
7734 temp >>= State.regs[srcreg2];
7735 State.regs[dstreg2] = temp;
7736 State.regs[dstreg1] = result1;
7739 // 1111 0111 1001 1011 Rm1 Rn1 imm4 Rn2; swhw_asr Rm1, Rn1, imm4, Rn2
7740 8.0xf7+8.0x9b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_asr
7744 int srcreg1, dstreg1, dstreg2;
7749 srcreg1 = translate_rreg (SD_, RM1);
7750 dstreg1 = translate_rreg (SD_, RN1);
7751 dstreg2 = translate_rreg (SD_, RN2);
7753 result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7754 | ((State.regs[srcreg1] >> 16) & 0xffff));
7755 temp = State.regs[dstreg2];
7757 State.regs[dstreg2] = temp;
7758 State.regs[dstreg1] = result1;
7761 // 1111 0111 1010 1011 Rm1 Rn1 Rm2 Rn2; swhw_lsr Rm1, Rn1, Rm2, Rn2
7762 8.0xf7+8.0xab+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_lsr
7766 int srcreg1, srcreg2, dstreg1, dstreg2;
7770 srcreg1 = translate_rreg (SD_, RM1);
7771 srcreg2 = translate_rreg (SD_, RM2);
7772 dstreg1 = translate_rreg (SD_, RN1);
7773 dstreg2 = translate_rreg (SD_, RN2);
7775 result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7776 | ((State.regs[srcreg1] >> 16) & 0xffff));
7777 State.regs[dstreg2] >>= State.regs[srcreg2];
7778 State.regs[dstreg1] = result1;
7781 // 1111 0111 1011 1011 Rm1 Rn1 imm4 Rn2; swhw_lsr Rm1, Rn1, imm4, Rn2
7782 8.0xf7+8.0xbb+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_lsr
7786 int srcreg1, dstreg1, dstreg2;
7791 srcreg1 = translate_rreg (SD_, RM1);
7792 dstreg1 = translate_rreg (SD_, RN1);
7793 dstreg2 = translate_rreg (SD_, RN2);
7795 result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7796 | ((State.regs[srcreg1] >> 16) & 0xffff));
7797 State.regs[dstreg2] >>= IMM4;
7798 State.regs[dstreg1] = result1;
7802 // 1111 0111 1100 1011 Rm1 Rn1 Rm2 Rn2; swhw_asl Rm1, Rn1, Rm2, Rn2
7803 8.0xf7+8.0xcb+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_asl
7807 int srcreg1, srcreg2, dstreg1, dstreg2;
7811 srcreg1 = translate_rreg (SD_, RM1);
7812 srcreg2 = translate_rreg (SD_, RM2);
7813 dstreg1 = translate_rreg (SD_, RN1);
7814 dstreg2 = translate_rreg (SD_, RN2);
7816 result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7817 | ((State.regs[srcreg1] >> 16) & 0xffff));
7818 State.regs[dstreg2] <<= State.regs[srcreg2];
7819 State.regs[dstreg1] = result1;
7822 // 1111 0111 1101 1011 Rm1 Rn1 imm4 Rn2; swhw_asl Rm1, Rn1, imm4, Rn2
7823 8.0xf7+8.0xdb+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_asl
7827 int srcreg1, dstreg1, dstreg2;
7832 srcreg1 = translate_rreg (SD_, RM1);
7833 dstreg1 = translate_rreg (SD_, RN1);
7834 dstreg2 = translate_rreg (SD_, RN2);
7836 result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7837 | ((State.regs[srcreg1] >> 16) & 0xffff));
7838 State.regs[dstreg2] <<= IMM4;
7839 State.regs[dstreg1] = result1;
7842 // 1111 0111 0000 1100 Rm1 Rn1 Rm2 Rn2; or_add Rm1, Rn1, Rm2, Rn2
7843 8.0xf7+8.0x0c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_add
7847 int srcreg1, srcreg2, dstreg1, dstreg2;
7851 srcreg1 = translate_rreg (SD_, RM1);
7852 srcreg2 = translate_rreg (SD_, RM2);
7853 dstreg1 = translate_rreg (SD_, RN1);
7854 dstreg2 = translate_rreg (SD_, RN2);
7856 result1 = State.regs[dstreg1] | State.regs[srcreg1];
7857 State.regs[dstreg2] += State.regs[srcreg2];
7858 State.regs[dstreg1] = result1;
7861 // 1111 0111 0001 1100 Rm1 Rn1 imm4 Rn2; or_add Rm1, Rn1, imm4, Rn2
7862 8.0xf7+8.0x1c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_add
7866 int srcreg1, dstreg1, dstreg2;
7870 srcreg1 = translate_rreg (SD_, RM1);
7871 dstreg1 = translate_rreg (SD_, RN1);
7872 dstreg2 = translate_rreg (SD_, RN2);
7874 result1 = State.regs[dstreg1] | State.regs[srcreg1];
7875 State.regs[dstreg2] += EXTEND4 (IMM4);
7876 State.regs[dstreg1] = result1;
7879 // 1111 0111 0010 1100 Rm1 Rn1 Rm2 Rn2; or_sub Rm1, Rn1, Rm2, Rn2
7880 8.0xf7+8.0x2c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_sub
7884 int srcreg1, srcreg2, dstreg1, dstreg2;
7888 srcreg1 = translate_rreg (SD_, RM1);
7889 srcreg2 = translate_rreg (SD_, RM2);
7890 dstreg1 = translate_rreg (SD_, RN1);
7891 dstreg2 = translate_rreg (SD_, RN2);
7893 result1 = State.regs[dstreg1] | State.regs[srcreg1];
7894 State.regs[dstreg2] -= State.regs[srcreg2];
7895 State.regs[dstreg1] = result1;
7898 // 1111 0111 0011 1100 Rm1 Rn1 imm4 Rn2; or_sub Rm1, Rn1, imm4, Rn2
7899 8.0xf7+8.0x3c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_sub
7903 int srcreg1, dstreg1, dstreg2;
7907 srcreg1 = translate_rreg (SD_, RM1);
7908 dstreg1 = translate_rreg (SD_, RN1);
7909 dstreg2 = translate_rreg (SD_, RN2);
7911 result1 = State.regs[dstreg1] | State.regs[srcreg1];
7912 State.regs[dstreg2] -= EXTEND4 (IMM4);
7913 State.regs[dstreg1] = result1;
7916 // 1111 0111 0100 1100 Rm1 Rn1 Rm2 Rn2; or_cmp Rm1, Rn1, Rm2, Rn2
7917 8.0xf7+8.0x4c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_cmp
7921 int srcreg1, srcreg2, dstreg1, dstreg2;
7924 srcreg1 = translate_rreg (SD_, RM1);
7925 srcreg2 = translate_rreg (SD_, RM2);
7926 dstreg1 = translate_rreg (SD_, RN1);
7927 dstreg2 = translate_rreg (SD_, RN2);
7929 genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
7930 State.regs[dstreg1] |= State.regs[srcreg1];
7933 // 1111 0111 0101 1100 Rm1 Rn1 imm4 Rn2; or_cmp Rm1, Rn1, imm4, Rn2
7934 8.0xf7+8.0x5c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_cmp
7938 int srcreg1, dstreg1, dstreg2;
7941 srcreg1 = translate_rreg (SD_, RM1);
7942 dstreg1 = translate_rreg (SD_, RN1);
7943 dstreg2 = translate_rreg (SD_, RN2);
7945 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
7946 State.regs[dstreg1] |= State.regs[srcreg1];
7949 // 1111 0111 0110 1100 Rm1 Rn1 Rm2 Rn2; or_mov Rm1, Rn1, Rm2, Rn2
7950 8.0xf7+8.0x6c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_mov
7954 int srcreg1, srcreg2, dstreg1, dstreg2;
7958 srcreg1 = translate_rreg (SD_, RM1);
7959 srcreg2 = translate_rreg (SD_, RM2);
7960 dstreg1 = translate_rreg (SD_, RN1);
7961 dstreg2 = translate_rreg (SD_, RN2);
7963 result1 = State.regs[dstreg1] | State.regs[srcreg1];
7964 State.regs[dstreg2] = State.regs[srcreg2];
7965 State.regs[dstreg1] = result1;
7968 // 1111 0111 0111 1100 Rm1 Rn1 imm4 Rn2; or_mov Rm1, Rn1, imm4, Rn2
7969 8.0xf7+8.0x7c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_mov
7973 int srcreg1, dstreg1, dstreg2;
7977 srcreg1 = translate_rreg (SD_, RM1);
7978 dstreg1 = translate_rreg (SD_, RN1);
7979 dstreg2 = translate_rreg (SD_, RN2);
7981 result1 = State.regs[dstreg1] | State.regs[srcreg1];
7982 State.regs[dstreg2] = EXTEND4 (IMM4);
7983 State.regs[dstreg1] = result1;
7986 // 1111 0111 1000 1100 Rm1 Rn1 Rm2 Rn2; or_asr Rm1, Rn1, Rm2, Rn2
7987 8.0xf7+8.0x8c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_asr
7991 int srcreg1, srcreg2, dstreg1, dstreg2;
7996 srcreg1 = translate_rreg (SD_, RM1);
7997 srcreg2 = translate_rreg (SD_, RM2);
7998 dstreg1 = translate_rreg (SD_, RN1);
7999 dstreg2 = translate_rreg (SD_, RN2);
8001 result1 = State.regs[dstreg1] | State.regs[srcreg1];
8002 temp = State.regs[dstreg2];
8003 temp >>= State.regs[srcreg2];
8004 State.regs[dstreg2] = temp;
8005 State.regs[dstreg1] = result1;
8008 // 1111 0111 1001 1100 Rm1 Rn1 imm4 Rn2; or_asr Rm1, Rn1, imm4, Rn2
8009 8.0xf7+8.0x9c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_asr
8013 int srcreg1, dstreg1, dstreg2;
8018 srcreg1 = translate_rreg (SD_, RM1);
8019 dstreg1 = translate_rreg (SD_, RN1);
8020 dstreg2 = translate_rreg (SD_, RN2);
8022 result1 = State.regs[dstreg1] | State.regs[srcreg1];
8023 temp = State.regs[dstreg2];
8025 State.regs[dstreg2] = temp;
8026 State.regs[dstreg1] = result1;
8029 // 1111 0111 1010 1100 Rm1 Rn1 Rm2 Rn2; or_lsr Rm1, Rn1, Rm2, Rn2
8030 8.0xf7+8.0xac+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_lsr
8034 int srcreg1, srcreg2, dstreg1, dstreg2;
8038 srcreg1 = translate_rreg (SD_, RM1);
8039 srcreg2 = translate_rreg (SD_, RM2);
8040 dstreg1 = translate_rreg (SD_, RN1);
8041 dstreg2 = translate_rreg (SD_, RN2);
8043 result1 = State.regs[dstreg1] | State.regs[srcreg1];
8044 State.regs[dstreg2] >>= State.regs[srcreg2];
8045 State.regs[dstreg1] = result1;
8048 // 1111 0111 1011 1100 Rm1 Rn1 imm4 Rn2; or_lsr Rm1, Rn1, imm4, Rn2
8049 8.0xf7+8.0xbc+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_lsr
8053 int srcreg1, dstreg1, dstreg2;
8058 srcreg1 = translate_rreg (SD_, RM1);
8059 dstreg1 = translate_rreg (SD_, RN1);
8060 dstreg2 = translate_rreg (SD_, RN2);
8062 result1 = State.regs[dstreg1] | State.regs[srcreg1];
8063 State.regs[dstreg2] >>= IMM4;
8064 State.regs[dstreg1] = result1;
8068 // 1111 0111 1100 1100 Rm1 Rn1 Rm2 Rn2; or_asl Rm1, Rn1, Rm2, Rn2
8069 8.0xf7+8.0xcc+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_asl
8073 int srcreg1, srcreg2, dstreg1, dstreg2;
8077 srcreg1 = translate_rreg (SD_, RM1);
8078 srcreg2 = translate_rreg (SD_, RM2);
8079 dstreg1 = translate_rreg (SD_, RN1);
8080 dstreg2 = translate_rreg (SD_, RN2);
8082 result1 = State.regs[dstreg1] | State.regs[srcreg1];
8083 State.regs[dstreg2] <<= State.regs[srcreg2];
8084 State.regs[dstreg1] = result1;
8087 // 1111 0111 1101 1100 Rm1 Rn1 imm4 Rn2; or_asl Rm1, Rn1, imm4, Rn2
8088 8.0xf7+8.0xdc+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_asl
8092 int srcreg1, dstreg1, dstreg2;
8097 srcreg1 = translate_rreg (SD_, RM1);
8098 dstreg1 = translate_rreg (SD_, RN1);
8099 dstreg2 = translate_rreg (SD_, RN2);
8101 result1 = State.regs[dstreg1] | State.regs[srcreg1];
8102 State.regs[dstreg2] <<= IMM4;
8103 State.regs[dstreg1] = result1;
8106 // 1111 0111 0000 1101 Rm1 Rn1 Rm2 Rn2; sat16_add Rm1, Rn1, Rm2, Rn2
8107 8.0xf7+8.0x0d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_add
8111 int srcreg1, srcreg2, dstreg1, dstreg2;
8115 srcreg1 = translate_rreg (SD_, RM1);
8116 srcreg2 = translate_rreg (SD_, RM2);
8117 dstreg1 = translate_rreg (SD_, RN1);
8118 dstreg2 = translate_rreg (SD_, RN2);
8120 if (State.regs[srcreg1] >= 0x7fff)
8122 else if (State.regs[srcreg1] <= 0xffff8000)
8123 result1 = 0xffff8000;
8125 result1 = State.regs[srcreg1];
8127 State.regs[dstreg2] += State.regs[srcreg2];
8128 State.regs[dstreg1] = result1;
8131 // 1111 0111 0001 1101 Rm1 Rn1 imm4 Rn2; sat16_add Rm1, Rn1, imm4, Rn2
8132 8.0xf7+8.0x1d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_add
8136 int srcreg1, dstreg1, dstreg2;
8140 srcreg1 = translate_rreg (SD_, RM1);
8141 dstreg1 = translate_rreg (SD_, RN1);
8142 dstreg2 = translate_rreg (SD_, RN2);
8144 if (State.regs[srcreg1] >= 0x7fff)
8146 else if (State.regs[srcreg1] <= 0xffff8000)
8147 result1 = 0xffff8000;
8149 result1 = State.regs[srcreg1];
8151 State.regs[dstreg2] += EXTEND4 (IMM4);
8152 State.regs[dstreg1] = result1;
8155 // 1111 0111 0010 1101 Rm1 Rn1 Rm2 Rn2; sat16_sub Rm1, Rn1, Rm2, Rn2
8156 8.0xf7+8.0x2d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_sub
8160 int srcreg1, srcreg2, dstreg1, dstreg2;
8164 srcreg1 = translate_rreg (SD_, RM1);
8165 srcreg2 = translate_rreg (SD_, RM2);
8166 dstreg1 = translate_rreg (SD_, RN1);
8167 dstreg2 = translate_rreg (SD_, RN2);
8169 if (State.regs[srcreg1] >= 0x7fff)
8171 else if (State.regs[srcreg1] <= 0xffff8000)
8172 result1 = 0xffff8000;
8174 result1 = State.regs[srcreg1];
8176 State.regs[dstreg2] -= State.regs[srcreg2];
8177 State.regs[dstreg1] = result1;
8180 // 1111 0111 0011 1101 Rm1 Rn1 imm4 Rn2; sat16_sub Rm1, Rn1, imm4, Rn2
8181 8.0xf7+8.0x3d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_sub
8185 int srcreg1, dstreg1, dstreg2;
8189 srcreg1 = translate_rreg (SD_, RM1);
8190 dstreg1 = translate_rreg (SD_, RN1);
8191 dstreg2 = translate_rreg (SD_, RN2);
8193 if (State.regs[srcreg1] >= 0x7fff)
8195 else if (State.regs[srcreg1] <= 0xffff8000)
8196 result1 = 0xffff8000;
8198 result1 = State.regs[srcreg1];
8200 State.regs[dstreg2] -= EXTEND4 (IMM4);
8201 State.regs[dstreg1] = result1;
8204 // 1111 0111 0100 1101 Rm1 Rn1 Rm2 Rn2; sat16_cmp Rm1, Rn1, Rm2, Rn2
8205 8.0xf7+8.0x4d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_cmp
8209 int srcreg1, srcreg2, dstreg1, dstreg2;
8213 srcreg1 = translate_rreg (SD_, RM1);
8214 srcreg2 = translate_rreg (SD_, RM2);
8215 dstreg1 = translate_rreg (SD_, RN1);
8216 dstreg2 = translate_rreg (SD_, RN2);
8218 State.regs[dstreg1] = result1;
8219 if (State.regs[srcreg1] >= 0x7fff)
8220 State.regs[dstreg1] = 0x7fff;
8221 else if (State.regs[srcreg1] <= 0xffff8000)
8222 State.regs[dstreg1] = 0xffff8000;
8224 State.regs[dstreg1] = State.regs[srcreg1];
8227 // 1111 0111 0101 1101 Rm1 Rn1 imm4 Rn2; sat16_cmp Rm1, Rn1, imm4, Rn2
8228 8.0xf7+8.0x5d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_cmp
8232 int srcreg1, dstreg1, dstreg2;
8235 srcreg1 = translate_rreg (SD_, RM1);
8236 dstreg1 = translate_rreg (SD_, RN1);
8237 dstreg2 = translate_rreg (SD_, RN2);
8239 genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
8240 if (State.regs[srcreg1] >= 0x7fff)
8241 State.regs[dstreg1] = 0x7fff;
8242 else if (State.regs[srcreg1] <= 0xffff8000)
8243 State.regs[dstreg1] = 0xffff8000;
8245 State.regs[dstreg1] = State.regs[srcreg1];
8248 // 1111 0111 0110 1101 Rm1 Rn1 Rm2 Rn2; sat16_mov Rm1, Rn1, Rm2, Rn2
8249 8.0xf7+8.0x6d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_mov
8253 int srcreg1, srcreg2, dstreg1, dstreg2;
8257 srcreg1 = translate_rreg (SD_, RM1);
8258 srcreg2 = translate_rreg (SD_, RM2);
8259 dstreg1 = translate_rreg (SD_, RN1);
8260 dstreg2 = translate_rreg (SD_, RN2);
8262 if (State.regs[srcreg1] >= 0x7fff)
8264 else if (State.regs[srcreg1] <= 0xffff8000)
8265 result1 = 0xffff8000;
8267 result1 = State.regs[srcreg1];
8269 State.regs[dstreg2] = State.regs[srcreg2];
8270 State.regs[dstreg1] = result1;
8273 // 1111 0111 0111 1101 Rm1 Rn1 imm4 Rn2; sat16_mov Rm1, Rn1, imm4, Rn2
8274 8.0xf7+8.0x7d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_mov
8278 int srcreg1, dstreg1, dstreg2;
8282 srcreg1 = translate_rreg (SD_, RM1);
8283 dstreg1 = translate_rreg (SD_, RN1);
8284 dstreg2 = translate_rreg (SD_, RN2);
8286 if (State.regs[srcreg1] >= 0x7fff)
8288 else if (State.regs[srcreg1] <= 0xffff8000)
8289 result1 = 0xffff8000;
8291 result1 = State.regs[srcreg1];
8293 State.regs[dstreg2] = EXTEND4 (IMM4);
8294 State.regs[dstreg1] = result1;
8297 // 1111 0111 1000 1101 Rm1 Rn1 Rm2 Rn2; sat16_asr Rm1, Rn1, Rm2, Rn2
8298 8.0xf7+8.0x8d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_asr
8302 int srcreg1, srcreg2, dstreg1, dstreg2;
8307 srcreg1 = translate_rreg (SD_, RM1);
8308 srcreg2 = translate_rreg (SD_, RM2);
8309 dstreg1 = translate_rreg (SD_, RN1);
8310 dstreg2 = translate_rreg (SD_, RN2);
8312 if (State.regs[srcreg1] >= 0x7fff)
8314 else if (State.regs[srcreg1] <= 0xffff8000)
8315 result1 = 0xffff8000;
8317 result1 = State.regs[srcreg1];
8319 temp = State.regs[dstreg2];
8320 temp >>= State.regs[srcreg2];
8321 State.regs[dstreg2] = temp;
8322 State.regs[dstreg1] = result1;
8325 // 1111 0111 1001 1101 Rm1 Rn1 imm4 Rn2; sat16_asr Rm1, Rn1, imm4, Rn2
8326 8.0xf7+8.0x9d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_asr
8330 int srcreg1, dstreg1, dstreg2;
8335 srcreg1 = translate_rreg (SD_, RM1);
8336 dstreg1 = translate_rreg (SD_, RN1);
8337 dstreg2 = translate_rreg (SD_, RN2);
8339 if (State.regs[srcreg1] >= 0x7fff)
8341 else if (State.regs[srcreg1] <= 0xffff8000)
8342 result1 = 0xffff8000;
8344 result1 = State.regs[srcreg1];
8346 temp = State.regs[dstreg2];
8348 State.regs[dstreg2] = temp;
8349 State.regs[dstreg1] = result1;
8352 // 1111 0111 1010 1101 Rm1 Rn1 Rm2 Rn2; sat16_lsr Rm1, Rn1, Rm2, Rn2
8353 8.0xf7+8.0xad+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_lsr
8357 int srcreg1, srcreg2, dstreg1, dstreg2;
8361 srcreg1 = translate_rreg (SD_, RM1);
8362 srcreg2 = translate_rreg (SD_, RM2);
8363 dstreg1 = translate_rreg (SD_, RN1);
8364 dstreg2 = translate_rreg (SD_, RN2);
8366 if (State.regs[srcreg1] >= 0x7fff)
8368 else if (State.regs[srcreg1] <= 0xffff8000)
8369 result1 = 0xffff8000;
8371 result1 = State.regs[srcreg1];
8373 State.regs[dstreg2] >>= State.regs[srcreg2];
8374 State.regs[dstreg1] = result1;
8377 // 1111 0111 1011 1101 Rm1 Rn1 imm4 Rn2; sat16_lsr Rm1, Rn1, imm4, Rn2
8378 8.0xf7+8.0xbd+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_lsr
8382 int srcreg1, dstreg1, dstreg2;
8387 srcreg1 = translate_rreg (SD_, RM1);
8388 dstreg1 = translate_rreg (SD_, RN1);
8389 dstreg2 = translate_rreg (SD_, RN2);
8391 if (State.regs[srcreg1] >= 0x7fff)
8393 else if (State.regs[srcreg1] <= 0xffff8000)
8394 result1 = 0xffff8000;
8396 result1 = State.regs[srcreg1];
8398 State.regs[dstreg2] >>= IMM4;
8399 State.regs[dstreg1] = result1;
8403 // 1111 0111 1100 1101 Rm1 Rn1 Rm2 Rn2; sat16_asl Rm1, Rn1, Rm2, Rn2
8404 8.0xf7+8.0xcd+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_asl
8408 int srcreg1, srcreg2, dstreg1, dstreg2;
8412 srcreg1 = translate_rreg (SD_, RM1);
8413 srcreg2 = translate_rreg (SD_, RM2);
8414 dstreg1 = translate_rreg (SD_, RN1);
8415 dstreg2 = translate_rreg (SD_, RN2);
8417 if (State.regs[srcreg1] >= 0x7fff)
8419 else if (State.regs[srcreg1] <= 0xffff8000)
8420 result1 = 0xffff8000;
8422 result1 = State.regs[srcreg1];
8424 State.regs[dstreg2] <<= State.regs[srcreg2];
8425 State.regs[dstreg1] = result1;
8428 // 1111 0111 1101 1101 Rm1 Rn1 imm4 Rn2; sat16_asl Rm1, Rn1, imm4, Rn2
8429 8.0xf7+8.0xdd+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_asl
8433 int srcreg1, dstreg1, dstreg2;
8438 srcreg1 = translate_rreg (SD_, RM1);
8439 dstreg1 = translate_rreg (SD_, RN1);
8440 dstreg2 = translate_rreg (SD_, RN2);
8442 if (State.regs[srcreg1] >= 0x7fff)
8444 else if (State.regs[srcreg1] <= 0xffff8000)
8445 result1 = 0xffff8000;
8447 result1 = State.regs[srcreg1];
8449 State.regs[dstreg2] <<= IMM4;
8450 State.regs[dstreg1] = result1;
8453 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0000; mov_llt (Rm+,imm4),Rn
8454 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x0:D2:::mov_llt
8462 srcreg = translate_rreg (SD_, RM);
8463 dstreg = translate_rreg (SD_, RN);
8465 State.regs[dstreg] = load_word (State.regs[srcreg]);
8466 State.regs[srcreg] += EXTEND4 (IMM4);
8468 if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))
8470 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8473 State.regs[dstreg] = result1;
8476 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0001; mov_lgt (Rm+,imm4),Rn
8477 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x1:D2:::mov_lgt
8484 srcreg = translate_rreg (SD_, RM);
8485 dstreg = translate_rreg (SD_, RN);
8487 State.regs[dstreg] = load_word (State.regs[srcreg]);
8488 State.regs[srcreg] += EXTEND4 (IMM4);
8491 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))))
8493 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8498 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0010; mov_lge (Rm+,imm4),Rn
8499 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x2:D2:::mov_lge
8506 srcreg = translate_rreg (SD_, RM);
8507 dstreg = translate_rreg (SD_, RN);
8509 State.regs[dstreg] = load_word (State.regs[srcreg]);
8510 State.regs[srcreg] += EXTEND4 (IMM4);
8512 if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
8514 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8519 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0011; mov_lle (Rm+,imm4),Rn
8520 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x3:D2:::mov_lle
8527 srcreg = translate_rreg (SD_, RM);
8528 dstreg = translate_rreg (SD_, RN);
8530 State.regs[dstreg] = load_word (State.regs[srcreg]);
8531 State.regs[srcreg] += EXTEND4 (IMM4);
8534 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
8536 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8541 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0100; mov_lcs (Rm+,imm4),Rn
8542 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x4:D2:::mov_lcs
8549 srcreg = translate_rreg (SD_, RM);
8550 dstreg = translate_rreg (SD_, RN);
8552 State.regs[dstreg] = load_word (State.regs[srcreg]);
8553 State.regs[srcreg] += EXTEND4 (IMM4);
8557 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8562 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0101; mov_lhi (Rm+,imm4),Rn
8563 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x5:D2:::mov_lhi
8570 srcreg = translate_rreg (SD_, RM);
8571 dstreg = translate_rreg (SD_, RN);
8573 State.regs[dstreg] = load_word (State.regs[srcreg]);
8574 State.regs[srcreg] += EXTEND4 (IMM4);
8576 if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
8578 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8583 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0110; mov_lcc (Rm+,imm4),Rn
8584 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x6:D2:::mov_lcc
8591 srcreg = translate_rreg (SD_, RM);
8592 dstreg = translate_rreg (SD_, RN);
8594 State.regs[dstreg] = load_word (State.regs[srcreg]);
8595 State.regs[srcreg] += EXTEND4 (IMM4);
8599 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8604 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0111; mov_lls (Rm+,imm4),Rn
8605 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x7:D2:::mov_lls
8612 srcreg = translate_rreg (SD_, RM);
8613 dstreg = translate_rreg (SD_, RN);
8615 State.regs[dstreg] = load_word (State.regs[srcreg]);
8616 State.regs[srcreg] += EXTEND4 (IMM4);
8618 if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
8620 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8625 // 1111 0111 1110 0000 Rm1 Rn1 imm4 1000; mov_leq (Rm+,imm4),Rn
8626 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x8:D2:::mov_leq
8633 srcreg = translate_rreg (SD_, RM);
8634 dstreg = translate_rreg (SD_, RN);
8636 State.regs[dstreg] = load_word (State.regs[srcreg]);
8637 State.regs[srcreg] += EXTEND4 (IMM4);
8641 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8646 // 1111 0111 1110 0000 Rm1 Rn1 imm4 1001; mov_lne (Rm+,imm4),Rn
8647 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x9:D2:::mov_lne
8654 srcreg = translate_rreg (SD_, RM);
8655 dstreg = translate_rreg (SD_, RN);
8657 State.regs[dstreg] = load_word (State.regs[srcreg]);
8658 State.regs[srcreg] += EXTEND4 (IMM4);
8662 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8667 // 1111 0111 1110 0000 Rm1 Rn1 imm4 1010; mov_lra (Rm+,imm4),Rn
8668 8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0xa:D2:::mov_lra
8675 srcreg = translate_rreg (SD_, RM);
8676 dstreg = translate_rreg (SD_, RN);
8678 State.regs[dstreg] = load_word (State.regs[srcreg]);
8679 State.regs[srcreg] += EXTEND4 (IMM4);
8681 State.regs[REG_PC] = State.regs[REG_LAR] - 4;