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address range support
[deliverable/binutils-gdb.git] / sim / mn10300 / mn10300.igen
1 // -*- C -*-
2 :option:::insn-bit-size:8
3 :option:::insn-specifying-widths:true
4 :option:::hi-bit-nr:7
5 :model:::mn10300:mn10300:
6 :model:::am33:am33:
7
8 // What do we do with an illegal instruction?
9 :internal::::illegal:
10 {
11 sim_io_eprintf (SD, "Illegal instruction at address 0x%lx\n",
12 (unsigned long) cia);
13 sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
14 }
15
16 // 1000 DnDn imm8....; mov imm8,Dn (imm8 is sign extended)
17 4.0x8,2.DM1,2.DN0=DM1+8.IMM8:S0i:::mov
18 "mov"
19 *mn10300
20 // start-sanitize-am33
21 *am33
22 // end-sanitize-am33
23 {
24 /* OP_8000 (); */
25 signed32 immed = EXTEND8 (IMM8);
26 State.regs[REG_D0+DN0] = immed;
27 PC = cia;
28 }
29
30 // 1000 DmDn; mov Dm,Dn (Dm != Dn, see above when Dm == Dn)
31 4.0x8,2.DM1,2.DN0!DM1:S0:::mov
32 "mov"
33 *mn10300
34 // start-sanitize-am33
35 *am33
36 // end-sanitize-am33
37 {
38 PC = cia;
39 /* OP_80 (); */
40 State.regs[REG_D0+DN0] = State.regs[REG_D0+DM1];
41 }
42
43
44 // 1111 0001 1110 DmAn; mov Dm,An
45 8.0xf1+1110,2.DM1,2.AN0:D0:::mov
46 "mov"
47 *mn10300
48 // start-sanitize-am33
49 *am33
50 // end-sanitize-am33
51 {
52 /* OP_F1E0 (); */
53 PC = cia;
54 State.regs[REG_A0 + AN0] = State.regs[REG_D0 + DM1];
55 }
56
57
58 // 1111 0001 1101 AmDn; mov Am,Dn
59 8.0xf1+1101,2.AM1,2.DN0:D0a:::mov
60 "mov"
61 *mn10300
62 // start-sanitize-am33
63 *am33
64 // end-sanitize-am33
65 {
66 /* OP_F1D0 (); */
67 PC = cia;
68 State.regs[REG_D0 + DN0] = State.regs[REG_A0 + AM1];
69 }
70
71
72 // 1001 AnAn imm8....; mov imm8,An (imm8 is zero-extended)
73 4.0x9,2.AM1,2.AN0=AM1+8.IMM8:S0ai:::mov
74 "mov"
75 *mn10300
76 // start-sanitize-am33
77 *am33
78 // end-sanitize-am33
79 {
80 PC = cia;
81 /* OP_9000 (); */
82 State.regs[REG_A0+AN0] = IMM8;
83 }
84
85
86 // 1001 AmAn; mov Am,An (Am != An, save above when Am == An)
87 4.0x9,2.AM1,2.AN0!AM1:S0a:::mov
88 "mov"
89 *mn10300
90 // start-sanitize-am33
91 *am33
92 // end-sanitize-am33
93 {
94 PC = cia;
95 /* OP_90 (); */
96 State.regs[REG_A0+AN0] = State.regs[REG_A0+AM1];
97 }
98
99
100 // 0011 11An; mov SP,An
101 4.0x3,11,2.AN0:S0b:::mov
102 "mov"
103 *mn10300
104 // start-sanitize-am33
105 *am33
106 // end-sanitize-am33
107 {
108 /* OP_3C (); */
109 PC = cia;
110 State.regs[REG_A0 + AN0] = State.regs[REG_SP];
111 }
112
113
114 // 1111 0010 1111 Am00; mov Am,SP
115 8.0xf2+4.0xf,2.AM1,00:D0b:::mov
116 "mov"
117 *mn10300
118 // start-sanitize-am33
119 *am33
120 // end-sanitize-am33
121 {
122 /* OP_F2F0 (); */
123 PC = cia;
124 State.regs[REG_SP] = State.regs[REG_A0 + AM1];
125 }
126
127
128 // 1111 0010 1110 01Dn; mov PSW,Dn
129 8.0xf2+4.0xe,01,2.DN0:D0c:::mov
130 "mov"
131 *mn10300
132 // start-sanitize-am33
133 *am33
134 // end-sanitize-am33
135 {
136 /* OP_F2E4 (); */
137 PC = cia;
138 State.regs[REG_D0 + DN0] = PSW;
139 }
140
141
142 // 1111 0010 1111 Dm11; mov Dm,PSW
143 8.0xf2+4.0xf,2.DM1,11:D0d:::mov
144 "mov"
145 *mn10300
146 // start-sanitize-am33
147 *am33
148 // end-sanitize-am33
149 {
150 /* OP_F2F3 (); */
151 PC = cia;
152 PSW = State.regs[REG_D0 + DM1];
153 }
154
155
156 // 1111 0010 1110 00Dn; mov MDR,Dn
157 8.0xf2+4.0xe,00,2.DN0:D0e:::mov
158 "mov"
159 *mn10300
160 // start-sanitize-am33
161 *am33
162 // end-sanitize-am33
163 {
164 /* OP_F2E0 (); */
165 PC = cia;
166 State.regs[REG_D0 + DN0] = State.regs[REG_MDR];
167 }
168
169
170 // 1111 0010 1111 Dm10; mov Dm,MDR
171 8.0xf2+4.0xf,2.DM1,10:D0f:::mov
172 "mov"
173 *mn10300
174 // start-sanitize-am33
175 *am33
176 // end-sanitize-am33
177 {
178 /* OP_F2F2 (); */
179 PC = cia;
180 State.regs[REG_MDR] = State.regs[REG_D0 + DM1];
181 }
182
183
184 // 0111 DnAm; mov (Am),Dn
185 4.0x7,2.DN1,2.AM0:S0c:::mov
186 "mov"
187 *mn10300
188 // start-sanitize-am33
189 *am33
190 // end-sanitize-am33
191 {
192 /* OP_70 (); */
193 PC = cia;
194 State.regs[REG_D0 + DN1] = load_word (State.regs[REG_A0 + AM0]);
195 }
196
197
198 // 1111 1000 0000 DnAm d8......; mov (d8,Am),Dn (d8 is sign-extended)
199 8.0xf8+4.0x0,2.DN1,2.AM0+8.D8:D1:::mov
200 "mov"
201 *mn10300
202 // start-sanitize-am33
203 *am33
204 // end-sanitize-am33
205 {
206 /* OP_F80000 (); */
207 PC = cia;
208 State.regs[REG_D0 + DN1]
209 = load_word ((State.regs[REG_A0 + AM0] + EXTEND8 (D8)));
210 }
211
212
213 // 1111 1010 0000 DnAm d16.....; mov (d16,Am),Dn (d16 is sign-extended.)
214 8.0xfa+4.0x0,2.DN1,2.AM0+8.D16A+8.D16B:D2:::mov
215 "mov"
216 *mn10300
217 // start-sanitize-am33
218 *am33
219 // end-sanitize-am33
220 {
221 /* OP_FA000000 (); */
222 PC = cia;
223 State.regs[REG_D0 + DN1]
224 = load_word ((State.regs[REG_A0 + AM0] + EXTEND16 (FETCH16(D16A, D16B))));
225 }
226
227
228 // 1111 1100 0000 DnAm d32.....; mov (d32,Am),Dn
229 8.0xfc+4.0x0,2.DN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::mov
230 "mov"
231 *mn10300
232 // start-sanitize-am33
233 *am33
234 // end-sanitize-am33
235 {
236 /* OP_FC000000 (); */
237 PC = cia;
238 State.regs[REG_D0 + DN1]
239 = load_word ((State.regs[REG_A0 + AM0]
240 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
241 }
242
243
244 // 0101 10Dn d8......; mov (d8,SP),Dn (d8 is zero-extended)
245 4.0x5,10,2.DN0+8.D8:S1:::mov
246 "mov"
247 *mn10300
248 // start-sanitize-am33
249 *am33
250 // end-sanitize-am33
251 {
252 /* OP_5800 (); */
253 PC = cia;
254 State.regs[REG_D0 + DN0] = load_word (State.regs[REG_SP] + D8);
255 }
256
257
258 // 1111 1010 1011 01Dn d16.....; mov (d16,SP),Dn (d16 is zero-extended.)
259 8.0xfa+4.0xb,01,2.DN0+8.IMM16A+8.IMM16B:D2a:::mov
260 "mov"
261 *mn10300
262 // start-sanitize-am33
263 *am33
264 // end-sanitize-am33
265 {
266 /* OP_FAB40000 (); */
267 PC = cia;
268 State.regs[REG_D0 + DN0]
269 = load_word (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B));
270 }
271
272
273 // 1111 1010 1011 01Dn d32.....; mov (d32,SP),Dn
274 8.0xfc+4.0xb,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::mov
275 "mov"
276 *mn10300
277 // start-sanitize-am33
278 *am33
279 // end-sanitize-am33
280 {
281 /* OP_FCB40000 (); */
282 PC = cia;
283 State.regs[REG_D0 + DN0]
284 = load_word (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
285 }
286
287
288 // 1111 0011 00Dn DiAm; mov (Di,Am),Dn
289 8.0xf3+00,2.DN2,2.DI,2.AM0:D0g:::mov
290 "mov"
291 *mn10300
292 // start-sanitize-am33
293 *am33
294 // end-sanitize-am33
295 {
296 /* OP_F300 (); */
297 PC = cia;
298 State.regs[REG_D0 + DN2]
299 = load_word ((State.regs[REG_A0 + AM0] + State.regs[REG_D0 + DI]));
300 }
301
302
303 // 0011 00Dn abs16...; mov (abs16),Dn (abs16 is zero-extended)
304 4.0x3,00,2.DN0+8.IMM16A+8.IMM16B:S2:::mov
305 "mov"
306 *mn10300
307 // start-sanitize-am33
308 *am33
309 // end-sanitize-am33
310 {
311 /* OP_300000 (); */
312 PC = cia;
313 State.regs[REG_D0 + DN0] = load_word (FETCH16(IMM16A, IMM16B));
314 }
315
316 // 1111 1100 1010 01Dn abs32...; mov (abs32),Dn
317 8.0xfc+4.0xa,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::mov
318 "mov"
319 *mn10300
320 // start-sanitize-am33
321 *am33
322 // end-sanitize-am33
323 {
324 /* OP_FCA40000 (); */
325 PC = cia;
326 State.regs[REG_D0 + DN0] = load_word (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
327 }
328
329
330 // 1111 0000 0000 AnAm; mov (Am),An
331 8.0xf0+4.0x0,2.AN1,2.AM0:D0h:::mov
332 "mov"
333 *mn10300
334 // start-sanitize-am33
335 *am33
336 // end-sanitize-am33
337 {
338 /* OP_F000 (); */
339 PC = cia;
340 State.regs[REG_A0 + AN1] = load_word (State.regs[REG_A0 + AM0]);
341 }
342
343
344 // 1111 1000 0010 AnAm d8......; mov (d8,Am),An (d8 is sign-extended)
345 8.0xf8+4.0x2,2.AN1,2.AM0+8.D8:D1a:::mov
346 "mov"
347 *mn10300
348 // start-sanitize-am33
349 *am33
350 // end-sanitize-am33
351 {
352 /* OP_F82000 (); */
353 PC = cia;
354 State.regs[REG_A0 + AN1]
355 = load_word ((State.regs[REG_A0 + AM0] + EXTEND8 (D8)));
356 }
357
358
359 // 1111 1010 0010 AnAm d16.....; mov (d16,Am),An (d16 is sign-extended.)
360 8.0xfa+4.0x2,2.AN1,2.AM0+8.D16A+8.D16B:D2b:::mov
361 "mov"
362 *mn10300
363 // start-sanitize-am33
364 *am33
365 // end-sanitize-am33
366 {
367 /* OP_FA200000 (); */
368 PC = cia;
369 State.regs[REG_A0 + AN1]
370 = load_word ((State.regs[REG_A0 + AM0]
371 + EXTEND16 (FETCH16(D16A, D16B))));
372 }
373
374
375 // 1111 1100 0010 AnAm d32.....; mov (d32,Am),An
376 8.0xfc+4.0x2,2.AN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4c:::mov
377 "mov"
378 *mn10300
379 // start-sanitize-am33
380 *am33
381 // end-sanitize-am33
382 {
383 /* OP_FC200000 (); */
384 PC = cia;
385 State.regs[REG_A0 + AN1]
386 = load_word ((State.regs[REG_A0 + AM0]
387 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
388 }
389
390
391 // 0101 11An d8......; mov (d8,SP),An (d8 is zero-extended)
392 4.0x5,11,2.AN0+8.D8:S1a:::mov
393 "mov"
394 *mn10300
395 // start-sanitize-am33
396 *am33
397 // end-sanitize-am33
398 {
399 /* OP_5C00 (); */
400 PC = cia;
401 State.regs[REG_A0 + AN0]
402 = load_word (State.regs[REG_SP] + D8);
403 }
404
405
406 // 1111 1010 1011 00An d16.....; mov (d16,SP),An (d16 is zero-extended.)
407 8.0xfa+4.0xb,00,2.AN0+8.IMM16A+8.IMM16B:D2c:::mov
408 "mov"
409 *mn10300
410 // start-sanitize-am33
411 *am33
412 // end-sanitize-am33
413 {
414 /* OP_FAB00000 (); */
415 PC = cia;
416 State.regs[REG_A0 + AN0]
417 = load_word (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B));
418 }
419
420
421 // 1111 1100 1011 00An d32.....; mov (d32,SP),An
422 8.0xfc+4.0xb,00,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4d:::mov
423 "mov"
424 *mn10300
425 // start-sanitize-am33
426 *am33
427 // end-sanitize-am33
428 {
429 /* OP_FCB00000 (); */
430 PC = cia;
431 State.regs[REG_A0 + AN0]
432 = load_word (State.regs[REG_SP]
433 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
434 }
435
436
437 // 1111 0011 10An DiAm; mov (Di,Am),An
438 8.0xf3+10,2.AN2,2.DI,2.AM0:D0i:::mov
439 "mov"
440 *mn10300
441 // start-sanitize-am33
442 *am33
443 // end-sanitize-am33
444 {
445 /* OP_F380 (); */
446 PC = cia;
447 State.regs[REG_A0 + AN2]
448 = load_word ((State.regs[REG_A0 + AM0]
449 + State.regs[REG_D0 + DI]));
450 }
451
452
453 // 1111 1010 1010 00An abs16...; mov (abs16),An (abs16 is zero-extended)
454 8.0xfa+4.0xa,00,2.AN0+8.IMM16A+8.IMM16B:D2d:::mov
455 "mov"
456 *mn10300
457 // start-sanitize-am33
458 *am33
459 // end-sanitize-am33
460 {
461 /* OP_FAA00000 (); */
462 PC = cia;
463 State.regs[REG_A0 + AN0] = load_word (FETCH16(IMM16A, IMM16B));
464 }
465
466
467 // 1111 1100 1010 00An abs32...; mov (abs32),An
468 8.0xfc+4.0xa,00,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4e:::mov
469 "mov"
470 *mn10300
471 // start-sanitize-am33
472 *am33
473 // end-sanitize-am33
474 {
475 /* OP_FCA00000 (); */
476 PC = cia;
477 State.regs[REG_A0 + AN0]
478 = load_word (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
479 }
480
481
482 // 1111 1000 1111 00Am d8......; mov (d8,Am),SP (d8 is sign-extended)
483 8.0xf8+4.0xf,00,2.AM0+8.D8:D1b:::mov
484 "mov"
485 *mn10300
486 // start-sanitize-am33
487 *am33
488 // end-sanitize-am33
489 {
490 /* OP_F8F000 (); */
491 PC = cia;
492 State.regs[REG_SP]
493 = load_word ((State.regs[REG_A0 + AM0] + EXTEND8 (D8)));
494 }
495
496
497 // 0110 DmAn; mov Dm,(An)
498 4.0x6,2.DM1,2.AN0:S0d:::mov
499 "mov"
500 *mn10300
501 // start-sanitize-am33
502 *am33
503 // end-sanitize-am33
504 {
505 /* OP_60 (); */
506 PC = cia;
507 store_word (State.regs[REG_A0 + AN0], State.regs[REG_D0 + DM1]);
508 }
509
510
511 // 1111 1000 0001 DmAn d8......; mov Dm,(d8,An) (d8 is sign-extended)
512 8.0xf8+4.0x1,2.DM1,2.AN0+8.D8:D1c:::mov
513 "mov"
514 *mn10300
515 // start-sanitize-am33
516 *am33
517 // end-sanitize-am33
518 {
519 /* OP_F81000 (); */
520 PC = cia;
521 store_word ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)),
522 State.regs[REG_D0 + DM1]);
523 }
524
525
526 // 1111 1010 0001 DmAn d16.....; mov Dm,(d16,An) (d16 is sign-extended.)
527 8.0xfa+4.0x1,2.DM1,2.AN0+8.D16A+8.D16B:D2e:::mov
528 "mov"
529 *mn10300
530 // start-sanitize-am33
531 *am33
532 // end-sanitize-am33
533 {
534 /* OP_FA100000 (); */
535 PC = cia;
536 store_word ((State.regs[REG_A0 + AN0] + EXTEND16 (FETCH16(D16A, D16B))),
537 State.regs[REG_D0 + DM1]);
538 }
539
540
541 // 1111 1100 0001 DmAn d32.....; mov Dm,(d32,An)
542 8.0xfc+4.0x1,2.DM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4f:::mov
543 "mov"
544 *mn10300
545 // start-sanitize-am33
546 *am33
547 // end-sanitize-am33
548 {
549 /* OP_FC100000 (); */
550 PC = cia;
551 store_word ((State.regs[REG_A0 + AN0]
552 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)),
553 State.regs[REG_D0 + DM1]);
554 }
555
556
557 // 0100 Dm10 d8......; mov Dm,(d8,SP) (d8 is zero-extended)
558 4.0x4,2.DM1,10+8.D8:S1b:::mov
559 "mov"
560 *mn10300
561 // start-sanitize-am33
562 *am33
563 // end-sanitize-am33
564 {
565 /* OP_4200 (); */
566 PC = cia;
567 store_word (State.regs[REG_SP] + D8, State.regs[REG_D0 + DM1]);
568 }
569
570
571 // 1111 1010 1001 Dm01 d16.....; mov Dm,(d16,SP) (d16 is zero-extended.)
572 8.0xfa+4.0x9,2.DM1,01+8.IMM16A+8.IMM16B:D2f:::mov
573 "mov"
574 *mn10300
575 // start-sanitize-am33
576 *am33
577 // end-sanitize-am33
578 {
579 /* OP_FA910000 (); */
580 PC = cia;
581 store_word (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B),
582 State.regs[REG_D0 + DM1]);
583 }
584
585
586 // 1111 1100 1001 Dm01 d32.....; mov Dm,(d32,SP)
587 8.0xfc+4.0x9,2.DM1,01+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4g:::mov
588 "mov"
589 *mn10300
590 // start-sanitize-am33
591 *am33
592 // end-sanitize-am33
593 {
594 /* OP_FC910000 (); */
595 PC = cia;
596 store_word (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
597 State.regs[REG_D0 + DM1]);
598 }
599
600
601 // 1111 0011 01Dm DiAn; mov Dm,(Di,An)
602 8.0xf3+01,2.DM2,2.DI,2.AN0:D0j:::mov
603 "mov"
604 *mn10300
605 // start-sanitize-am33
606 *am33
607 // end-sanitize-am33
608 {
609 /* OP_F340 (); */
610 PC = cia;
611 store_word ((State.regs[REG_A0 + AN0] + State.regs[REG_D0 + DI]),
612 State.regs[REG_D0 + DM2]);
613 }
614
615
616 // 0000 Dm01 abs16..., mov Dm,(abs16) (abs16 is zero-extended).
617 4.0x0,2.DM1,01+8.IMM16A+8.IMM16B:S2a:::mov
618 "mov"
619 *mn10300
620 // start-sanitize-am33
621 *am33
622 // end-sanitize-am33
623 {
624 /* OP_10000 (); */
625 PC = cia;
626 store_word (FETCH16(IMM16A, IMM16B), State.regs[REG_D0 + DM1]);
627 }
628
629
630 // 1111 1100 1000 Dm01 abs32...; mov Dm,(abs32)
631 8.0xfc+4.0x8,2.DM1,01+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4h:::mov
632 "mov"
633 *mn10300
634 // start-sanitize-am33
635 *am33
636 // end-sanitize-am33
637 {
638 /* OP_FC810000 (); */
639 PC = cia;
640 store_word (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
641 State.regs[REG_D0 + DM1]);
642 }
643
644
645 // 1111 0000 0001 AmAn; mov Am,(An)
646 8.0xf0+4.0x1,2.AM1,2.AN0:D0k:::mov
647 "mov"
648 *mn10300
649 // start-sanitize-am33
650 *am33
651 // end-sanitize-am33
652 {
653 /* OP_F010 (); */
654 PC = cia;
655 store_word (State.regs[REG_A0 + AN0], State.regs[REG_A0 + AM1]);
656 }
657
658
659 // 1111 1000 0011 AmAn d8......; mov Am,(d8,An) (d8 is sign-extended)
660 8.0xf8+4.0x3,2.AM1,2.AN0+8.D8:D1d:::mov
661 "mov"
662 *mn10300
663 // start-sanitize-am33
664 *am33
665 // end-sanitize-am33
666 {
667 /* OP_F83000 (); */
668 PC = cia;
669 store_word ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)),
670 State.regs[REG_A0 + AM1]);
671 }
672
673
674 // 1111 1010 0011 AmAn d16.....; mov Am,(d16,An) (d16 is sign-extended.)
675 8.0xfa+4.0x3,2.AM1,2.AN0+8.D16A+8.D16B:D2g:::mov
676 "mov"
677 *mn10300
678 // start-sanitize-am33
679 *am33
680 // end-sanitize-am33
681 {
682 /* OP_FA300000 (); */
683 PC = cia;
684 store_word ((State.regs[REG_A0 + AN0] + EXTEND16 (FETCH16(D16A, D16B))),
685 State.regs[REG_A0 + AM1]);
686 }
687
688
689 // 1111 1100 0011 AmAn d32.....; mov Am,(d32,An)
690 8.0xfc+4.0x3,2.AM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4i:::mov
691 "mov"
692 *mn10300
693 // start-sanitize-am33
694 *am33
695 // end-sanitize-am33
696 {
697 /* OP_FC300000 (); */
698 PC = cia;
699 store_word ((State.regs[REG_A0 + AN0]
700 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)),
701 State.regs[REG_A0 + AM1]);
702 }
703
704
705 // 0100 Am11 d8......; mov Am,(d8,SP) (d8 is zero-extended)
706 4.0x4,2.AM1,11+8.D8:S1c:::mov
707 "mov"
708 *mn10300
709 // start-sanitize-am33
710 *am33
711 // end-sanitize-am33
712 {
713 /* OP_4300 (); */
714 PC = cia;
715 store_word (State.regs[REG_SP] + (D8), State.regs[REG_A0 + (AM1)]);
716 }
717
718
719 // 1111 1010 1001 Am00 d16.....; mov Am,(d16,SP) (d16 is zero-extended.)
720 8.0xfa+4.0x9,2.AM1,00+8.IMM16A+8.IMM16B:D2h:::mov
721 "mov"
722 *mn10300
723 // start-sanitize-am33
724 *am33
725 // end-sanitize-am33
726 {
727 /* OP_FA900000 (); */
728 PC = cia;
729 store_word (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B),
730 State.regs[REG_A0 + AM1]);
731 }
732
733
734 // 1111 1100 1001 Am00 d32.....; mov Am,(d32,SP)
735 8.0xfc+4.0x9,2.AM1,00+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4j:::mov
736 "mov"
737 *mn10300
738 // start-sanitize-am33
739 *am33
740 // end-sanitize-am33
741 {
742 /* OP_FC900000 (); */
743 PC = cia;
744 store_word (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
745 State.regs[REG_A0 + AM1]);
746 }
747
748
749 // 1111 0011 11Am DiAn; mov Am,(Di,An)
750 8.0xf3+11,2.AM2,2.DI,2.AN0:D0l:::mov
751 "mov"
752 *mn10300
753 // start-sanitize-am33
754 *am33
755 // end-sanitize-am33
756 {
757 /* OP_F3C0 (); */
758 PC = cia;
759 store_word ((State.regs[REG_A0 + AN0] + State.regs[REG_D0 + DI]),
760 State.regs[REG_A0 + AM2]);
761 }
762
763
764 // 1111 1010 1000 Am00 abs16...; mov Am,(abs16) (abs16 is zero-extended)
765 8.0xfa+4.0x8,2.AM1,00+8.IMM16A+8.IMM16B:D2i:::mov
766 "mov"
767 *mn10300
768 // start-sanitize-am33
769 *am33
770 // end-sanitize-am33
771 {
772 /* OP_FA800000 (); */
773 PC = cia;
774 store_word (FETCH16(IMM16A, IMM16B),
775 State.regs[REG_A0 + AM1]);
776 }
777
778
779 // 1111 1100 1000 Am00 abs32...; mov Am,(abs32)
780 8.0xfc+4.0x8,2.AM1,00+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4k:::mov
781 "mov"
782 *mn10300
783 // start-sanitize-am33
784 *am33
785 // end-sanitize-am33
786 {
787 /* OP_FC800000 (); */
788 PC = cia;
789 store_word (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
790 State.regs[REG_A0 + AM1]);
791 }
792
793
794 // 1111 1000 1111 01An d8......; mov SP,(d8,An) (d8 is sign-extended)
795 8.0xf8+4.0xf,01,2.AN0+8.D8:D1e:::mov
796 "mov"
797 *mn10300
798 // start-sanitize-am33
799 *am33
800 // end-sanitize-am33
801 {
802 /* OP_F8F400 (); */
803 PC = cia;
804 store_word (State.regs[REG_A0 + AN0] + EXTEND8 (D8),
805 State.regs[REG_SP]);
806 }
807
808
809 // 0010 11Dn imm16...; mov imm16,Dn (imm16 is sign-extended)
810 4.0x2,11,2.DN0+8.IMM16A+8.IMM16B:S2b:::mov
811 "mov"
812 *mn10300
813 // start-sanitize-am33
814 *am33
815 // end-sanitize-am33
816 {
817 /* OP_2C0000 (); */
818 unsigned long value;
819
820 PC = cia;
821 value = EXTEND16 (FETCH16(IMM16A, IMM16B));
822 State.regs[REG_D0 + DN0] = value;
823 }
824
825
826 // 1111 1100 1100 11Dn imm32...; mov imm32,Dn
827 8.0xfc+4.0xc,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4l:::mov
828 "mov"
829 *mn10300
830 // start-sanitize-am33
831 *am33
832 // end-sanitize-am33
833 {
834 /* OP_FCCC0000 (); */
835 unsigned long value;
836
837 PC = cia;
838 value = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
839 State.regs[REG_D0 + DN0] = value;
840 }
841
842
843 // 0010 01An imm16...; mov imm16,An (imm16 is zero-extended)
844 4.0x2,01,2.AN0+8.IMM16A+8.IMM16B:S2c:::mov
845 "mov"
846 *mn10300
847 // start-sanitize-am33
848 *am33
849 // end-sanitize-am33
850 {
851 /* OP_240000 (); */
852 unsigned long value;
853
854 PC = cia;
855 value = FETCH16(IMM16A, IMM16B);
856 State.regs[REG_A0 + AN0] = value;
857 }
858
859
860 // 1111 1100 1101 11An imm32...; mov imm32,An
861 8.0xfc+4.0xd,11,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4m:::mov
862 "mov"
863 *mn10300
864 // start-sanitize-am33
865 *am33
866 // end-sanitize-am33
867 {
868 /* OP_FCDC0000 (); */
869 PC = cia;
870 State.regs[REG_A0 + AN0] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
871 }
872
873
874 // 1111 0000 0100 DnAm; movbu (Am),Dn
875 8.0xf0+4.0x4,2.DN1,2.AM0:D0:::movbu
876 "movbu"
877 *mn10300
878 // start-sanitize-am33
879 *am33
880 // end-sanitize-am33
881 {
882 /* OP_F040 (); */
883 PC = cia;
884 State.regs[REG_D0 + DN1]
885 = load_byte (State.regs[REG_A0 + AM0]);
886 }
887
888
889 // 1111 1000 0100 DnAm d8......; movbu (d8,Am),Dn (d8 is sign-extended)
890 8.0xf8+4.0x4,2.DN1,2.AM0+8.D8:D1f:::movbu
891 "movbu"
892 *mn10300
893 // start-sanitize-am33
894 *am33
895 // end-sanitize-am33
896 {
897 /* OP_F84000 (); */
898 PC = cia;
899 State.regs[REG_D0 + DN1]
900 = load_byte ((State.regs[REG_A0 + AM0] + EXTEND8 (D8)));
901 }
902
903
904 // 1111 1010 0100 DnAm d16.....; movbu (d16,Am),Dn (d16 is sign-extended.)
905 8.0xfa+4.0x4,2.DN1,2.AM0+8.D16A+8.D16B:D2:::movbu
906 "movbu"
907 *mn10300
908 // start-sanitize-am33
909 *am33
910 // end-sanitize-am33
911 {
912 /* OP_FA400000 (); */
913 PC = cia;
914 State.regs[REG_D0 + DN1]
915 = load_byte ((State.regs[REG_A0 + AM0]
916 + EXTEND16 (FETCH16(D16A, D16B))));
917 }
918
919
920 // 1111 1100 0100 DnAm d32.....; movbu (d32,Am),Dn
921 8.0xfc+4.0x4,2.DN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::movbu
922 "movbu"
923 *mn10300
924 // start-sanitize-am33
925 *am33
926 // end-sanitize-am33
927 {
928 /* OP_FC400000 (); */
929 PC = cia;
930 State.regs[REG_D0 + DN1]
931 = load_byte ((State.regs[REG_A0 + AM0]
932 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
933 }
934
935
936 // 1111 1000 1011 10Dn d8......; movbu (d8,SP),Dn (d8 is zero-extended)
937 8.0xf8+4.0xb,10,2.DN0+8.D8:D1a:::movbu
938 "movbu"
939 *mn10300
940 // start-sanitize-am33
941 *am33
942 // end-sanitize-am33
943 {
944 /* OP_F8B800 (); */
945 PC = cia;
946 State.regs[REG_D0 + DN0]
947 = load_byte ((State.regs[REG_SP] + (D8)));
948 }
949
950
951 // 1111 1010 1011 10Dn d16.....; movbu (d16,SP),Dn (d16 is zero-extended.)
952 8.0xfa+4.0xb,10,2.DN0+8.IMM16A+8.IMM16B:D2a:::movbu
953 "movbu"
954 *mn10300
955 // start-sanitize-am33
956 *am33
957 // end-sanitize-am33
958 {
959 /* OP_FAB80000 (); */
960 PC = cia;
961 State.regs[REG_D0 + DN0]
962 = load_byte ((State.regs[REG_SP]
963 + FETCH16(IMM16A, IMM16B)));
964 }
965
966
967 // 1111 1100 1011 10Dn d32.....; movbu (d32,SP),Dn
968 8.0xfc+4.0xb,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::movbu
969 "movbu"
970 *mn10300
971 // start-sanitize-am33
972 *am33
973 // end-sanitize-am33
974 {
975 /* OP_FCB80000 (); */
976 PC = cia;
977 State.regs[REG_D0 + DN0]
978 = load_byte (State.regs[REG_SP]
979 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
980 }
981
982
983 // 1111 0100 00Dn DiAm; movbu (Di,Am),Dn
984 8.0xf4+00,2.DN2,2.DI,2.AM0:D0a:::movbu
985 "movbu"
986 *mn10300
987 // start-sanitize-am33
988 *am33
989 // end-sanitize-am33
990 {
991 /* OP_F400 (); */
992 PC = cia;
993 State.regs[REG_D0 + DN2]
994 = load_byte ((State.regs[REG_A0 + AM0]
995 + State.regs[REG_D0 + DI]));
996 }
997
998
999 // 0011 01Dn abs16...; movbu (abs16),Dn (abs16 is zero-extended)
1000 4.0x3,01,2.DN0+8.IMM16A+8.IMM16B:S2:::movbu
1001 "movbu"
1002 *mn10300
1003 // start-sanitize-am33
1004 *am33
1005 // end-sanitize-am33
1006 {
1007 /* OP_340000 (); */
1008 PC = cia;
1009 State.regs[REG_D0 + DN0] = load_byte (FETCH16(IMM16A, IMM16B));
1010 }
1011
1012
1013 // 1111 1100 1010 10Dn abs32...; movbu (abs32),Dn
1014 8.0xfc+4.0xa,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::movbu
1015 "movbu"
1016 *mn10300
1017 // start-sanitize-am33
1018 *am33
1019 // end-sanitize-am33
1020 {
1021 /* OP_FCA80000 (); */
1022 PC = cia;
1023 State.regs[REG_D0 + DN0]
1024 = load_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
1025 }
1026
1027
1028 // 1111 0000 0101 DmAn; movbu Dm,(An)
1029 8.0xf0+4.0x5,2.DM1,2.AN0:D0b:::movbu
1030 "movbu"
1031 *mn10300
1032 // start-sanitize-am33
1033 *am33
1034 // end-sanitize-am33
1035 {
1036 /* OP_F050 (); */
1037 PC = cia;
1038 store_byte (State.regs[REG_A0 + AN0], State.regs[REG_D0 + DM1]);
1039 }
1040
1041
1042 // 1111 1000 0101 DmAn d8......; movbu Dm,(d8,An) (d8 is sign-extended)
1043 8.0xf8+4.0x5,2.DM1,2.AN0+8.D8:D1b:::movbu
1044 "movbu"
1045 *mn10300
1046 // start-sanitize-am33
1047 *am33
1048 // end-sanitize-am33
1049 {
1050 /* OP_F85000 (); */
1051 PC = cia;
1052 store_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)),
1053 State.regs[REG_D0 + DM1]);
1054 }
1055
1056
1057 // 1111 1010 0101 DmAn d16.....; movbu Dm,(d16,An) (d16 is sign-extended.)
1058 8.0xfa+4.0x5,2.DM1,2.AN0+8.D16A+8.D16B:D2b:::movbu
1059 "movbu"
1060 *mn10300
1061 // start-sanitize-am33
1062 *am33
1063 // end-sanitize-am33
1064 {
1065 /* OP_FA500000 (); */
1066 PC = cia;
1067 store_byte ((State.regs[REG_A0 + AN0] + EXTEND16 (FETCH16(D16A, D16B))),
1068 State.regs[REG_D0 + DM1]);
1069 }
1070
1071
1072 // 1111 1100 0101 DmAn d32.....; movbu Dm,(d32,An)
1073 8.0xfc+4.0x5,2.DM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4c:::movbu
1074 "movbu"
1075 *mn10300
1076 // start-sanitize-am33
1077 *am33
1078 // end-sanitize-am33
1079 {
1080 /* OP_FC500000 (); */
1081 PC = cia;
1082 store_byte ((State.regs[REG_A0 + AN0]
1083 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)),
1084 State.regs[REG_D0 + DM1]);
1085 }
1086
1087
1088 // 1111 1000 1001 Dm10 d8......; movbu Dm,(d8,SP) (d8 is zero-extended)
1089 8.0xf8+4.0x9,2.DM1,10+8.D8:D1c:::movbu
1090 "movbu"
1091 *mn10300
1092 // start-sanitize-am33
1093 *am33
1094 // end-sanitize-am33
1095 {
1096 /* OP_F89200 (); */
1097 PC = cia;
1098 store_byte (State.regs[REG_SP] + (D8), State.regs[REG_D0 + DM1]);
1099 }
1100
1101
1102 // 1111 1010 1001 Dm10 d16.....; movbu Dm,(d16,SP) (d16 is zero-extended.)
1103 8.0xfa+4.0x9,2.DM1,10+8.IMM16A+8.IMM16B:D2c:::movbu
1104 "movbu"
1105 *mn10300
1106 // start-sanitize-am33
1107 *am33
1108 // end-sanitize-am33
1109 {
1110 /* OP_FA920000 (); */
1111 PC = cia;
1112 store_byte (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B),
1113 State.regs[REG_D0 + DM1]);
1114 }
1115
1116
1117 // 1111 1100 1001 Dm10 d32.....; movbu Dm,(d32,SP)
1118 8.0xfc+4.0x9,2.DM1,10+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4d:::movbu
1119 "movbu"
1120 *mn10300
1121 // start-sanitize-am33
1122 *am33
1123 // end-sanitize-am33
1124 {
1125 /* OP_FC920000 (); */
1126 PC = cia;
1127 store_byte (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
1128 State.regs[REG_D0 + DM1]);
1129 }
1130
1131
1132 // 1111 0100 01Dm DiAn; movbu Dm,(Di,An)
1133 8.0xf4+01,2.DM2,2.DI,2.AN0:D0c:::movbu
1134 "movbu"
1135 *mn10300
1136 // start-sanitize-am33
1137 *am33
1138 // end-sanitize-am33
1139 {
1140 /* OP_F440 (); */
1141 PC = cia;
1142 store_byte ((State.regs[REG_A0 + AN0] + State.regs[REG_D0 + DI]),
1143 State.regs[REG_D0 + DM2]);
1144 }
1145
1146
1147 // 0000 Dm10 abs16...; movbu Dm,(abs16) (abs16 is zero-extended)
1148 4.0x0,2.DM1,10+8.IMM16A+8.IMM16B:S2a:::movbu
1149 "movbu"
1150 *mn10300
1151 // start-sanitize-am33
1152 *am33
1153 // end-sanitize-am33
1154 {
1155 /* OP_20000 (); */
1156 PC = cia;
1157 store_byte (FETCH16(IMM16A, IMM16B),
1158 State.regs[REG_D0 + DM1]);
1159 }
1160
1161
1162 // 1111 1100 1000 Dm10 abs32...; movbu Dm,(abs32)
1163 8.0xfc+4.0x8,2.DM1,10+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4e:::movbu
1164 "movbu"
1165 *mn10300
1166 // start-sanitize-am33
1167 *am33
1168 // end-sanitize-am33
1169 {
1170 /* OP_FC820000 (); */
1171 PC = cia;
1172 store_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
1173 State.regs[REG_D0 + DM1]);
1174 }
1175
1176
1177 // 1111 0000 0110 DnAm; movhu (Am),Dn
1178 8.0xf0+4.0x6,2.DN1,2.AM0:D0:::movhu
1179 "movhu"
1180 *mn10300
1181 // start-sanitize-am33
1182 *am33
1183 // end-sanitize-am33
1184 {
1185 /* OP_F060 (); */
1186 PC = cia;
1187 State.regs[REG_D0 + DN1]
1188 = load_half (State.regs[REG_A0 + AM0]);
1189 }
1190
1191
1192 // 1111 1000 0110 DnAm d8......; movhu (d8,Am),Dn (d8 is sign-extended)
1193 8.0xf8+4.0x6,2.DN1,2.AM0+8.D8:D1d:::movhu
1194 "movhu"
1195 *mn10300
1196 // start-sanitize-am33
1197 *am33
1198 // end-sanitize-am33
1199 {
1200 /* OP_F86000 (); */
1201 PC = cia;
1202 State.regs[REG_D0 + DN1]
1203 = load_half ((State.regs[REG_A0 + AM0] + EXTEND8 (D8)));
1204 }
1205
1206
1207 // 1111 1010 0110 DnAm d16.....; movhu (d16,Am),Dn (d16 is sign-extended.)
1208 8.0xfa+4.0x6,2.DN1,2.AM0+8.D16A+8.D16B:D2:::movhu
1209 "movhu"
1210 *mn10300
1211 // start-sanitize-am33
1212 *am33
1213 // end-sanitize-am33
1214 {
1215 /* OP_FA600000 (); */
1216 PC = cia;
1217 State.regs[REG_D0 + DN1]
1218 = load_half ((State.regs[REG_A0 + AM0]
1219 + EXTEND16 (FETCH16(D16A, D16B))));
1220 }
1221
1222
1223 // 1111 1100 0110 DnAm d32.....; movhu (d32,Am),Dn
1224 8.0xfc+4.0x6,2.DN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::movhu
1225 "movhu"
1226 *mn10300
1227 // start-sanitize-am33
1228 *am33
1229 // end-sanitize-am33
1230 {
1231 /* OP_FC600000 (); */
1232 PC = cia;
1233 State.regs[REG_D0 + DN1]
1234 = load_half ((State.regs[REG_A0 + AM0]
1235 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
1236 }
1237
1238
1239 // 1111 1000 1011 11Dn d8.....; movhu (d8,SP),Dn (d8 is zero-extended)
1240 8.0xf8+4.0xb,11,2.DN0+8.D8:D1a:::movhu
1241 "movhu"
1242 *mn10300
1243 // start-sanitize-am33
1244 *am33
1245 // end-sanitize-am33
1246 {
1247 /* OP_F8BC00 (); */
1248 PC = cia;
1249 State.regs[REG_D0 + DN0]
1250 = load_half ((State.regs[REG_SP] + (D8)));
1251 }
1252
1253
1254 // 1111 1010 1011 11Dn d16.....; movhu (d16,SP),Dn (d16 is zero-extended.)
1255 8.0xfa+4.0xb,11,2.DN0+8.IMM16A+8.IMM16B:D2a:::movhu
1256 "movhu"
1257 *mn10300
1258 // start-sanitize-am33
1259 *am33
1260 // end-sanitize-am33
1261 {
1262 /* OP_FABC0000 (); */
1263 PC = cia;
1264 State.regs[REG_D0 + DN0]
1265 = load_half ((State.regs[REG_SP] + FETCH16(IMM16A, IMM16B)));
1266 }
1267
1268
1269 // 1111 1100 1011 11Dn d32.....; movhu (d32,SP),Dn
1270 8.0xfc+4.0xb,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::movhu
1271 "movhu"
1272 *mn10300
1273 // start-sanitize-am33
1274 *am33
1275 // end-sanitize-am33
1276 {
1277 /* OP_FCBC0000 (); */
1278 PC = cia;
1279 State.regs[REG_D0 + DN0]
1280 = load_half (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
1281 }
1282
1283
1284 // 1111 0100 10Dn DiAm; movhu (Di,Am),Dn
1285 8.0xf4+10,2.DN2,2.DI,2.AM0:D0a:::movhu
1286 "movhu"
1287 *mn10300
1288 // start-sanitize-am33
1289 *am33
1290 // end-sanitize-am33
1291 {
1292 /* OP_F480 (); */
1293 PC = cia;
1294 State.regs[REG_D0 + DN2]
1295 = load_half ((State.regs[REG_A0 + AM0] + State.regs[REG_D0 + DI]));
1296 }
1297
1298
1299 // 0011 10Dn abs16...; movhu (abs16),Dn (abs16 is zero-extended)
1300 4.0x3,10,2.DN0+8.IMM16A+8.IMM16B:S2:::movhu
1301 "movhu"
1302 *mn10300
1303 // start-sanitize-am33
1304 *am33
1305 // end-sanitize-am33
1306 {
1307 /* OP_380000 (); */
1308 PC = cia;
1309 State.regs[REG_D0 + DN0] = load_half (FETCH16(IMM16A, IMM16B));
1310 }
1311
1312
1313 // 1111 1100 1010 11Dn abs32...; movhu (abs32),Dn
1314 8.0xfc+4.0xa,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::movhu
1315 "movhu"
1316 *mn10300
1317 // start-sanitize-am33
1318 *am33
1319 // end-sanitize-am33
1320 {
1321 /* OP_FCAC0000 (); */
1322 PC = cia;
1323 State.regs[REG_D0 + DN0]
1324 = load_half (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
1325 }
1326
1327
1328 // 1111 0000 0111 DmAn; movhu Dm,(An)
1329 8.0xf0+4.0x7,2.DM1,2.AN0:D0b:::movhu
1330 "movhu"
1331 *mn10300
1332 // start-sanitize-am33
1333 *am33
1334 // end-sanitize-am33
1335 {
1336 /* OP_F070 (); */
1337 PC = cia;
1338 store_half (State.regs[REG_A0 + AN0],
1339 State.regs[REG_D0 + DM1]);
1340 }
1341
1342
1343 // 1111 1000 0111 DmAn d8......; movhu Dm,(d8,An) (d8 is sign-extended)
1344 8.0xf8+4.0x7,2.DM1,2.AN0+8.D8:D1b:::movhu
1345 "movhu"
1346 *mn10300
1347 // start-sanitize-am33
1348 *am33
1349 // end-sanitize-am33
1350 {
1351 /* OP_F87000 (); */
1352 PC = cia;
1353 store_half ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)),
1354 State.regs[REG_D0 + DM1]);
1355 }
1356
1357
1358 // 1111 1010 0111 DnAm d16.....; movhu Dm,(d16,An) (d16 is sign-extended.)
1359 8.0xfa+4.0x7,2.DM1,2.AN0+8.D16A+8.D16B:D2b:::movhu
1360 "movhu"
1361 *mn10300
1362 // start-sanitize-am33
1363 *am33
1364 // end-sanitize-am33
1365 {
1366 /* OP_FA700000 (); */
1367 PC = cia;
1368 store_half ((State.regs[REG_A0 + AN0] + EXTEND16 (FETCH16(D16A, D16B))),
1369 State.regs[REG_D0 + DM1]);
1370 }
1371
1372
1373 // 1111 1100 0111 DmAn d32.....; movhu Dm,(d32,An)
1374 8.0xfc+4.0x7,2.DM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4c:::movhu
1375 "movhu"
1376 *mn10300
1377 // start-sanitize-am33
1378 *am33
1379 // end-sanitize-am33
1380 {
1381 /* OP_FC700000 (); */
1382 PC = cia;
1383 store_half ((State.regs[REG_A0 + AN0]
1384 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)),
1385 State.regs[REG_D0 + DM1]);
1386 }
1387
1388
1389 // 1111 1000 1001 Dm11 d8....; movhu Dm,(d8,SP) (d8 is zero-extended)
1390 8.0xf8+4.0x9,2.DM1,11+8.D8:D1c:::movhu
1391 "movhu"
1392 *mn10300
1393 // start-sanitize-am33
1394 *am33
1395 // end-sanitize-am33
1396 {
1397 /* OP_F89300 (); */
1398 PC = cia;
1399 store_half (State.regs[REG_SP] + (D8),
1400 State.regs[REG_D0 + DM1]);
1401 }
1402
1403
1404 // 1111 1010 1001 Dm11 d16.....; movhu Dm,(d16,SP) (d16 is zero-extended.)
1405 8.0xfa+4.0x9,2.DM1,11+8.IMM16A+8.IMM16B:D2c:::movhu
1406 "movhu"
1407 *mn10300
1408 // start-sanitize-am33
1409 *am33
1410 // end-sanitize-am33
1411 {
1412 /* OP_FA930000 (); */
1413 PC = cia;
1414 store_half (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B),
1415 State.regs[REG_D0 + DM1]);
1416 }
1417
1418
1419 // 1111 1100 1001 Dm11 d32.....; movhu Dm,(d32,SP)
1420 8.0xfc+4.0x9,2.DM1,11+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4d:::movhu
1421 "movhu"
1422 *mn10300
1423 // start-sanitize-am33
1424 *am33
1425 // end-sanitize-am33
1426 {
1427 /* OP_FC930000 (); */
1428 PC = cia;
1429 store_half (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
1430 State.regs[REG_D0 + DM1]);
1431 }
1432
1433
1434 // 1111 0100 11Dm DiAn; movhu Dm,(Di,An)
1435 8.0xf4+11,2.DM2,2.DI,2.AN0:D0c:::movhu
1436 "movhu"
1437 *mn10300
1438 // start-sanitize-am33
1439 *am33
1440 // end-sanitize-am33
1441 {
1442 /* OP_F4C0 (); */
1443 PC = cia;
1444 store_half ((State.regs[REG_A0 + AN0] + State.regs[REG_D0 + DI]),
1445 State.regs[REG_D0 + DM2]);
1446 }
1447
1448
1449 // 0000 Dm11 abs16...; movhu Dm,(abs16) (abs16 is zero-extended)
1450 4.0x0,2.DM1,11+8.IMM16A+8.IMM16B:S2a:::movhu
1451 "movhu"
1452 *mn10300
1453 // start-sanitize-am33
1454 *am33
1455 // end-sanitize-am33
1456 {
1457 /* OP_30000 (); */
1458 PC = cia;
1459 store_half (FETCH16(IMM16A, IMM16B), State.regs[REG_D0 + DM1]);
1460 }
1461
1462
1463 // 1111 1100 1000 Dm11 abs32...; movhu Dm,(abs32)
1464 8.0xfc+4.0x8,2.DM1,11+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4e:::movhu
1465 "movhu"
1466 *mn10300
1467 // start-sanitize-am33
1468 *am33
1469 // end-sanitize-am33
1470 {
1471 /* OP_FC830000 (); */
1472 PC = cia;
1473 store_half (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
1474 State.regs[REG_D0 + DM1]);
1475 }
1476
1477
1478 // 1111 0010 1101 00Dn; ext Dn
1479 8.0xf2+4.0xd,00,2.DN0:D0:::ext
1480 "ext"
1481 *mn10300
1482 // start-sanitize-am33
1483 *am33
1484 // end-sanitize-am33
1485 {
1486 /* OP_F2D0 (); */
1487 PC = cia;
1488 if (State.regs[REG_D0 + DN0] & 0x80000000)
1489 State.regs[REG_MDR] = -1;
1490 else
1491 State.regs[REG_MDR] = 0;
1492 }
1493
1494
1495 // 0001 00Dn; extb Dn
1496 4.0x1,00,2.DN0:S0:::extb
1497 "extb"
1498 *mn10300
1499 // start-sanitize-am33
1500 *am33
1501 // end-sanitize-am33
1502 {
1503 /* OP_10 (); */
1504 PC = cia;
1505 State.regs[REG_D0 + DN0] = EXTEND8 (State.regs[REG_D0 + DN0]);
1506 }
1507
1508
1509 // 0001 01Dn; extbu Dn
1510 4.0x1,01,2.DN0:S0:::extbu
1511 "extbu"
1512 *mn10300
1513 // start-sanitize-am33
1514 *am33
1515 // end-sanitize-am33
1516 {
1517 /* OP_14 (); */
1518 PC = cia;
1519 State.regs[REG_D0 + DN0] &= 0xff;
1520 }
1521
1522
1523 // 0001 10Dn; exth Dn
1524 4.0x1,10,2.DN0:S0:::exth
1525 "exth"
1526 *mn10300
1527 // start-sanitize-am33
1528 *am33
1529 // end-sanitize-am33
1530 {
1531 /* OP_18 (); */
1532 PC = cia;
1533 State.regs[REG_D0 + DN0] = EXTEND16 (State.regs[REG_D0 + DN0]);
1534 }
1535
1536
1537 // 0001 11Dn; exthu Dn
1538 4.0x1,11,2.DN0:S0:::exthu
1539 "exthu"
1540 *mn10300
1541 // start-sanitize-am33
1542 *am33
1543 // end-sanitize-am33
1544 {
1545 /* OP_1C (); */
1546 PC = cia;
1547 State.regs[REG_D0 + DN0] &= 0xffff;
1548 }
1549
1550
1551 // 0000 Dn00; clr Dn
1552 4.0x0,2.DN1,00:S0:::clr
1553 "clr"
1554 *mn10300
1555 // start-sanitize-am33
1556 *am33
1557 // end-sanitize-am33
1558 {
1559 /* OP_0 (); */
1560 PC = cia;
1561 State.regs[REG_D0 + DN1] = 0;
1562
1563 PSW |= PSW_Z;
1564 PSW &= ~(PSW_V | PSW_C | PSW_N);
1565 }
1566
1567
1568 // 1110 DmDn; add Dm,Dn
1569 4.0xe,2.DM1,2.DN0:S0:::add
1570 "add"
1571 *mn10300
1572 // start-sanitize-am33
1573 *am33
1574 // end-sanitize-am33
1575 {
1576 /* OP_E0 (); */
1577 PC = cia;
1578 genericAdd(State.regs[REG_D0 + DM1], REG_D0 + DN0);
1579 }
1580
1581 // 1111 0001 0110 DmAn; add Dm,An
1582 8.0xf1+4.0x6,2.DM1,2.AN0:D0:::add
1583 "add"
1584 *mn10300
1585 // start-sanitize-am33
1586 *am33
1587 // end-sanitize-am33
1588 {
1589 /* OP_F160 (); */
1590 PC = cia;
1591 genericAdd(State.regs[REG_D0 + DM1], REG_A0 + AN0);
1592 }
1593
1594
1595 // 1111 0001 0101 AmDn; add Am,Dn
1596 8.0xf1+4.0x5,2.AM1,2.DN0:D0a:::add
1597 "add"
1598 *mn10300
1599 // start-sanitize-am33
1600 *am33
1601 // end-sanitize-am33
1602 {
1603 /* OP_F150 (); */
1604 PC = cia;
1605 genericAdd(State.regs[REG_A0 + AM1], REG_D0 + DN0);
1606 }
1607
1608
1609 // 1111 0001 0111 AmAn; add Am,An
1610 8.0xf1+4.0x7,2.AM1,2.AN0:D0b:::add
1611 "add"
1612 *mn10300
1613 // start-sanitize-am33
1614 *am33
1615 // end-sanitize-am33
1616 {
1617 /* OP_F170 (); */
1618 PC = cia;
1619 genericAdd(State.regs[REG_A0 + AM1], REG_A0 + AN0);
1620 }
1621
1622
1623 // 0010 10Dn imm8....; add imm8,Dn (imm8 is sign-extended)
1624 4.0x2,10,2.DN0+8.IMM8:S1:::add
1625 "add"
1626 *mn10300
1627 // start-sanitize-am33
1628 *am33
1629 // end-sanitize-am33
1630 {
1631 /* OP_2800 (); */
1632 PC = cia;
1633 genericAdd(EXTEND8(IMM8), REG_D0 + DN0);
1634 }
1635
1636
1637 // 1111 1010 1100 00Dn imm16...; add imm16,Dn
1638 8.0xfa+4.0xc,00,2.DN0+8.IMM16A+8.IMM16B:D2:::add
1639 "add"
1640 *mn10300
1641 // start-sanitize-am33
1642 *am33
1643 // end-sanitize-am33
1644 {
1645 /* OP_FAC00000 (); */
1646 PC = cia;
1647 genericAdd(EXTEND16(FETCH16(IMM16A, IMM16B)), REG_D0 + DN0);
1648 }
1649
1650
1651 // 1111 1100 1100 00Dn imm32...; add imm32,Dn
1652 8.0xfc+4.0xc,00,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::add
1653 "add"
1654 *mn10300
1655 // start-sanitize-am33
1656 *am33
1657 // end-sanitize-am33
1658 {
1659 /* OP_FCC00000 (); */
1660 PC = cia;
1661 genericAdd(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_D0 + DN0);
1662 }
1663
1664
1665 // 0010 00An imm8....; add imm8,An (imm8 is sign-extended)
1666 4.0x2,00,2.AN0+8.IMM8:S1a:::add
1667 "add"
1668 *mn10300
1669 // start-sanitize-am33
1670 *am33
1671 // end-sanitize-am33
1672 {
1673 /* OP_2000 (); */
1674 PC = cia;
1675 genericAdd(EXTEND8(IMM8), REG_A0 + AN0);
1676 }
1677
1678
1679 // 1111 1010 1101 00An imm16...; add imm16,An (imm16 is sign-extended.)
1680 8.0xfa+4.0xd,00,2.AN0+8.IMM16A+8.IMM16B:D2a:::add
1681 "add"
1682 *mn10300
1683 // start-sanitize-am33
1684 *am33
1685 // end-sanitize-am33
1686 {
1687 /* OP_FAD00000 (); */
1688 PC = cia;
1689 genericAdd(EXTEND16(FETCH16(IMM16A, IMM16B)), REG_A0 + AN0);
1690 }
1691
1692
1693 // 1111 1100 1101 00An imm32...; add imm32,An
1694 8.0xfc+4.0xd,00,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::add
1695 "add"
1696 *mn10300
1697 // start-sanitize-am33
1698 *am33
1699 // end-sanitize-am33
1700 {
1701 /* OP_FCD00000 (); */
1702 PC = cia;
1703 genericAdd(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_A0 + AN0);
1704 }
1705
1706
1707 // 1111 1000 1111 1110 imm8....; add imm8,SP (imm8 is sign-extended.)
1708 8.0xf8+8.0xfe+8.IMM8:D1:::add
1709 "add"
1710 *mn10300
1711 // start-sanitize-am33
1712 *am33
1713 // end-sanitize-am33
1714 {
1715 /* OP_F8FE00 (); */
1716 unsigned long imm;
1717
1718 /* Note: no PSW changes. */
1719 PC = cia;
1720 imm = EXTEND8 (IMM8);
1721 State.regs[REG_SP] += imm;
1722 }
1723
1724
1725 // 1111 1010 1111 1110 imm16...; add imm16,SP (imm16 is sign-extended.)
1726 8.0xfa+8.0xfe+8.IMM16A+8.IMM16B:D2b:::add
1727 "add"
1728 *mn10300
1729 // start-sanitize-am33
1730 *am33
1731 // end-sanitize-am33
1732 {
1733 /* OP_FAFE0000 (); */
1734 unsigned long imm;
1735
1736 /* Note: no PSW changes. */
1737 PC = cia;
1738 imm = EXTEND16 (FETCH16(IMM16A, IMM16B));
1739 State.regs[REG_SP] += imm;
1740 }
1741
1742
1743 // 1111 1100 1111 1110 imm32...; add imm32,SP
1744 8.0xfc+8.0xfe+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::add
1745 "add"
1746 *mn10300
1747 // start-sanitize-am33
1748 *am33
1749 // end-sanitize-am33
1750 {
1751 /* OP_FCFE0000 (); */
1752 unsigned long imm;
1753
1754 /* Note: no PSW changes. */
1755 PC = cia;
1756 imm = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
1757 State.regs[REG_SP] += imm;
1758 }
1759
1760
1761 // 1111 0001 0100 DmDn; addc Dm,Dn
1762 8.0xf1+4.0x4,2.DM1,2.DN0:D0:::addc
1763 "addc"
1764 *mn10300
1765 // start-sanitize-am33
1766 *am33
1767 // end-sanitize-am33
1768 {
1769 /* OP_F140 (); */
1770 int z, c, n, v;
1771 unsigned long reg1, reg2, sum;
1772
1773 PC = cia;
1774 reg1 = State.regs[REG_D0 + DM1];
1775 reg2 = State.regs[REG_D0 + DN0];
1776 sum = reg1 + reg2 + ((PSW & PSW_C) != 0);
1777 State.regs[REG_D0 + DN0] = sum;
1778
1779 z = ((PSW & PSW_Z) != 0) && (sum == 0);
1780 n = (sum & 0x80000000);
1781 c = (sum < reg1) || (sum < reg2);
1782 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
1783 && (reg2 & 0x80000000) != (sum & 0x80000000));
1784
1785 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1786 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1787 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1788 }
1789
1790
1791 // 1111 0001 0000 DmDn; sub Dm,Dn
1792 8.0xf1+4.0x0,2.DM1,2.DN0:D0:::sub
1793 "sub"
1794 *mn10300
1795 // start-sanitize-am33
1796 *am33
1797 // end-sanitize-am33
1798 {
1799 /* OP_F100 (); */
1800 PC = cia;
1801 genericSub(State.regs[REG_D0 + DM1], REG_D0 + DN0);
1802 }
1803
1804 // 1111 0001 0010 DmAn; sub DmAn
1805 8.0xf1+4.0x2,2.DM1,2.AN0:D0a:::sub
1806 "sub"
1807 *mn10300
1808 // start-sanitize-am33
1809 *am33
1810 // end-sanitize-am33
1811 {
1812 /* OP_F120 (); */
1813 PC = cia;
1814 genericSub(State.regs[REG_D0 + DM1], REG_A0 + AN0);
1815 }
1816
1817
1818 // 1111 0001 0001 AmDn; sub AmDn
1819 8.0xf1+4.0x1,2.AM1,2.DN0:D0b:::sub
1820 "sub"
1821 *mn10300
1822 // start-sanitize-am33
1823 *am33
1824 // end-sanitize-am33
1825 {
1826 /* OP_F110 (); */
1827 PC = cia;
1828 genericSub(State.regs[REG_A0 + AM1], REG_D0 + DN0);
1829 }
1830
1831
1832 // 1111 0001 0011 AmAn; sub Am,An
1833 8.0xf1+4.0x3,2.AM1,2.AN0:D0c:::sub
1834 "sub"
1835 *mn10300
1836 // start-sanitize-am33
1837 *am33
1838 // end-sanitize-am33
1839 {
1840 /* OP_F130 (); */
1841 PC = cia;
1842 genericSub(State.regs[REG_A0 + AM1], REG_A0 + AN0);
1843 }
1844
1845
1846 // 1111 1100 1100 01Dn imm32...; sub imm32,Dn
1847 8.0xfc+4.0xc,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::sub
1848 "sub"
1849 *mn10300
1850 // start-sanitize-am33
1851 *am33
1852 // end-sanitize-am33
1853 {
1854 /* OP_FCC40000 (); */
1855 PC = cia;
1856 genericSub(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_D0 + DN0);
1857 }
1858
1859
1860 // 1111 1100 1101 01An imm32...; sub imm32,An
1861 8.0xfc+4.0xd,01,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::sub
1862 "sub"
1863 *mn10300
1864 // start-sanitize-am33
1865 *am33
1866 // end-sanitize-am33
1867 {
1868 /* OP_FCD40000 (); */
1869 PC = cia;
1870 genericSub(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_A0 + AN0);
1871 }
1872
1873
1874 // 1111 0001 1000 DmDn; subc Dm,Dn
1875 8.0xf1+4.0x8,2.DM1,2.DN0:D0:::subc
1876 "subc"
1877 *mn10300
1878 // start-sanitize-am33
1879 *am33
1880 // end-sanitize-am33
1881 {
1882 /* OP_F180 (); */
1883 int z, c, n, v;
1884 unsigned long reg1, reg2, difference;
1885
1886 PC = cia;
1887 reg1 = State.regs[REG_D0 + DM1];
1888 reg2 = State.regs[REG_D0 + DN0];
1889 difference = reg2 - reg1 - ((PSW & PSW_C) != 0);
1890 State.regs[REG_D0 + DN0] = difference;
1891
1892 z = ((PSW & PSW_Z) != 0) && (difference == 0);
1893 n = (difference & 0x80000000);
1894 c = (reg1 > reg2);
1895 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1896 && (reg2 & 0x80000000) != (difference & 0x80000000));
1897
1898 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1899 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1900 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1901 }
1902
1903
1904 // 1111 0010 0100 DmDn; mul Dm,Dn
1905 8.0xf2+4.0x4,2.DM1,2.DN0:D0:::mul
1906 "mul"
1907 *mn10300
1908 // start-sanitize-am33
1909 *am33
1910 // end-sanitize-am33
1911 {
1912 /* OP_F240 (); */
1913 unsigned long long temp;
1914 int n, z;
1915
1916 PC = cia;
1917 temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
1918 * (signed64)(signed32)State.regs[REG_D0 + DM1]);
1919 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
1920 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
1921 z = (State.regs[REG_D0 + DN0] == 0);
1922 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
1923 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1924 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1925 }
1926
1927
1928 // 1111 0010 0101 DmDn; mulu Dm,Dn
1929 8.0xf2+4.0x5,2.DM1,2.DN0:D0:::mulu
1930 "mulu"
1931 *mn10300
1932 // start-sanitize-am33
1933 *am33
1934 // end-sanitize-am33
1935 {
1936 /* OP_F250 (); */
1937 unsigned long long temp;
1938 int n, z;
1939
1940 PC = cia;
1941 temp = ((unsigned64)State.regs[REG_D0 + DN0]
1942 * (unsigned64)State.regs[REG_D0 + DM1]);
1943 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
1944 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
1945 z = (State.regs[REG_D0 + DN0] == 0);
1946 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
1947 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1948 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1949 }
1950
1951
1952 // 1111 0010 0110 DmDn; div Dm,Dn
1953 8.0xf2+4.0x6,2.DM1,2.DN0:D0:::div
1954 "div"
1955 *mn10300
1956 // start-sanitize-am33
1957 *am33
1958 // end-sanitize-am33
1959 {
1960 /* OP_F260 (); */
1961 signed64 temp;
1962 signed32 denom;
1963 int n, z, v;
1964
1965 PC = cia;
1966 denom = (signed32)State.regs[REG_D0 + DM1];
1967
1968 temp = State.regs[REG_MDR];
1969 temp <<= 32;
1970 temp |= State.regs[REG_D0 + DN0];
1971 if ( !(v = (0 == denom)) )
1972 {
1973 State.regs[REG_MDR] = temp % (signed32)State.regs[REG_D0 + DM1];
1974 temp /= (signed32)State.regs[REG_D0 + DM1];
1975 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
1976 }
1977 else
1978 {
1979 State.regs[REG_MDR] = temp;
1980 State.regs[REG_D0 + DN0] = 0xff;
1981 }
1982 z = (State.regs[REG_D0 + DN0] == 0);
1983 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
1984 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1985 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (v ? PSW_V : 0));
1986 }
1987
1988
1989 // 1111 0010 0111 DmDn; divu Dm,Dn
1990 8.0xf2+4.0x7,2.DM1,2.DN0:D0:::divu
1991 "divu"
1992 *mn10300
1993 // start-sanitize-am33
1994 *am33
1995 // end-sanitize-am33
1996 {
1997 /* OP_F270 (); */
1998 unsigned64 temp;
1999 unsigned32 denom;
2000 int n, z, v;
2001
2002 PC = cia;
2003 denom = (unsigned32)State.regs[REG_D0 + DM1];
2004 temp = State.regs[REG_MDR];
2005 temp <<= 32;
2006 temp |= State.regs[REG_D0 + DN0];
2007 if ( !(v = (0 == denom)) )
2008 {
2009 State.regs[REG_MDR] = temp % State.regs[REG_D0 + DM1];
2010 temp /= State.regs[REG_D0 + DM1];
2011 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
2012 }
2013 else
2014 {
2015 State.regs[REG_MDR] = temp;
2016 State.regs[REG_D0 + DN0] = 0xff;
2017 }
2018 z = (State.regs[REG_D0 + DN0] == 0);
2019 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2020 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2021 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (v ? PSW_V : 0));
2022 }
2023
2024
2025 // 0100 Dn00; inc Dn
2026 4.0x4,2.DN1,00:S0:::inc
2027 "inc"
2028 *mn10300
2029 // start-sanitize-am33
2030 *am33
2031 // end-sanitize-am33
2032 {
2033 /* OP_40 (); */
2034 unsigned int imm;
2035
2036 PC = cia;
2037 imm = 1;
2038 genericAdd(imm, REG_D0 + DN1);
2039 }
2040
2041
2042 // 0100 An01
2043 4.0x4,2.AN1,01:S0a:::inc
2044 "inc"
2045 *mn10300
2046 // start-sanitize-am33
2047 *am33
2048 // end-sanitize-am33
2049 {
2050 /* OP_41 (); */
2051 PC = cia;
2052 State.regs[REG_A0 + AN1] += 1;
2053 }
2054
2055
2056 // 0101 00An; inc4 An
2057 4.0x5,00,2.AN0:S0:::inc4
2058 "inc4"
2059 *mn10300
2060 // start-sanitize-am33
2061 *am33
2062 // end-sanitize-am33
2063 {
2064 /* OP_50 (); */
2065 PC = cia;
2066 State.regs[REG_A0 + AN0] += 4;
2067 }
2068
2069
2070 // 1010 DnDn imm8....; cmp imm8,Dn (imm8 is sign-extended.)
2071 4.0xa,2.DM1,2.DN0=DM1+IMM8:S0i:::cmp
2072 "cmp"
2073 *mn10300
2074 // start-sanitize-am33
2075 *am33
2076 // end-sanitize-am33
2077 {
2078 PC = cia;
2079 /* OP_A000 (); */
2080 genericCmp(EXTEND8 (IMM8), State.regs[REG_D0 + DN0]);
2081 }
2082
2083
2084 // 1010 DmDn; cmp Dm,Dn (Dm != Dn, see above when Dm == Dn)
2085 4.0xa,2.DM1,2.DN0!DM1:S0:::cmp
2086 "cmp"
2087 *mn10300
2088 // start-sanitize-am33
2089 *am33
2090 // end-sanitize-am33
2091 {
2092 PC = cia;
2093 /* OP_A0 (); */
2094 genericCmp(State.regs[REG_D0 + DM1], State.regs[REG_D0 + DN0]);
2095 }
2096
2097
2098 // 1111 0001 1010 DmAn; cmp Dm,An
2099 8.0xf1+4.0xa,2.DM1,2.AN0:D0:::cmp
2100 "cmp"
2101 *mn10300
2102 // start-sanitize-am33
2103 *am33
2104 // end-sanitize-am33
2105 {
2106 /* OP_F1A0 (); */
2107 PC = cia;
2108 genericCmp(State.regs[REG_D0 + DM1], State.regs[REG_A0 + AN0]);
2109 }
2110
2111
2112 // 1111 0001 1001 AmDn; cmp Am,Dn
2113 8.0xf1+4.0x9,2.AM1,2.DN0:D0a:::cmp
2114 "cmp"
2115 *mn10300
2116 // start-sanitize-am33
2117 *am33
2118 // end-sanitize-am33
2119 {
2120 /* OP_F190 (); */
2121 PC = cia;
2122 genericCmp(State.regs[REG_A0 + AM1], State.regs[REG_D0 + DN0]);
2123 }
2124
2125
2126 // 1011 AnAn imm8....; cmp imm8,An (imm8 is zero-extended.)
2127 4.0xb,2.AM1,2.AN0=AM1+IMM8:S0ai:::cmp
2128 "cmp"
2129 *mn10300
2130 // start-sanitize-am33
2131 *am33
2132 // end-sanitize-am33
2133 {
2134 PC = cia;
2135 /* OP_B000 (); */
2136 genericCmp(IMM8,
2137 State.regs[REG_A0 + AN0]);
2138 }
2139
2140
2141 // 1011 AmAn; cmp Am,An (Dm != Dn, see above when Dm == Dn)
2142 4.0xb,2.AM1,2.AN0!AM1:S0a:::cmp
2143 "cmp"
2144 *mn10300
2145 // start-sanitize-am33
2146 *am33
2147 // end-sanitize-am33
2148 {
2149 PC = cia;
2150 /* OP_B0 (); */
2151 genericCmp(State.regs[REG_A0 + AM1], State.regs[REG_A0 + AN0]);
2152 }
2153
2154
2155 // 1111 1010 1100 10Dn imm16...; cmp imm16,Dn (imm16 is sign-extended.)
2156 8.0xfa+4.0xc,10,2.DN0+8.IMM16A+8.IMM16B:D2:::cmp
2157 "cmp"
2158 *mn10300
2159 // start-sanitize-am33
2160 *am33
2161 // end-sanitize-am33
2162 {
2163 /* OP_FAC80000 (); */
2164 PC = cia;
2165 genericCmp(EXTEND16(FETCH16(IMM16A, IMM16B)),
2166 State.regs[REG_D0 + DN0]);
2167 }
2168
2169
2170 // 1111 1100 1100 10Dn imm32...; cmp imm32,Dn
2171 8.0xfc+4.0xc,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::cmp
2172 "cmp"
2173 *mn10300
2174 // start-sanitize-am33
2175 *am33
2176 // end-sanitize-am33
2177 {
2178 /* OP_FCC80000 (); */
2179 PC = cia;
2180 genericCmp(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
2181 State.regs[REG_D0 + DN0]);
2182 }
2183
2184
2185 // 1111 1010 1101 10An imm16...; cmp imm16,An (imm16 is zero-extended.)
2186 8.0xfa+4.0xd,10,2.AN0+8.IMM16A+8.IMM16B:D2a:::cmp
2187 "cmp"
2188 *mn10300
2189 // start-sanitize-am33
2190 *am33
2191 // end-sanitize-am33
2192 {
2193 /* OP_FAD80000 (); */
2194 PC = cia;
2195 genericCmp(FETCH16(IMM16A, IMM16B),
2196 State.regs[REG_A0 + AN0]);
2197 }
2198
2199
2200 // 1111 1100 1101 10An imm32...; cmp imm32,An
2201 8.0xfc+4.0xd,10,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::cmp
2202 "cmp"
2203 *mn10300
2204 // start-sanitize-am33
2205 *am33
2206 // end-sanitize-am33
2207 {
2208 /* OP_FCD80000 (); */
2209 PC = cia;
2210 genericCmp(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
2211 State.regs[REG_A0 + AN0]);
2212 }
2213
2214
2215 // 1111 0010 0000 DmDn; and Dm,Dn
2216 8.0xf2+4.0x0,2.DM1,2.DN0:D0:::and
2217 "and"
2218 *mn10300
2219 // start-sanitize-am33
2220 *am33
2221 // end-sanitize-am33
2222 {
2223 /* OP_F200 (); */
2224 int n, z;
2225
2226 PC = cia;
2227 State.regs[REG_D0 + DN0] &= State.regs[REG_D0 + DM1];
2228 z = (State.regs[REG_D0 + DN0] == 0);
2229 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2230 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2231 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2232 }
2233
2234
2235 // 1111 1000 1110 00Dn imm8....; and imm8,Dn (imm8 is zero-extended.)
2236 8.0xf8+4.0xe,00,2.DN0+8.IMM8:D1:::and
2237 "and"
2238 *mn10300
2239 // start-sanitize-am33
2240 *am33
2241 // end-sanitize-am33
2242 {
2243 /* OP_F8E000 (); */
2244 int n, z;
2245
2246 PC = cia;
2247 State.regs[REG_D0 + DN0] &= IMM8;
2248 z = (State.regs[REG_D0 + DN0] == 0);
2249 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2250 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2251 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2252 }
2253
2254
2255 // 1111 1010 1110 00Dn imm16...; and imm16,Dn (imm16 is zero-extended.)
2256 8.0xfa+4.0xe,00,2.DN0+8.IMM16A+8.IMM16B:D2:::and
2257 "and"
2258 *mn10300
2259 // start-sanitize-am33
2260 *am33
2261 // end-sanitize-am33
2262 {
2263 /* OP_FAE00000 (); */
2264 int n, z;
2265
2266 PC = cia;
2267 State.regs[REG_D0 + DN0] &= FETCH16(IMM16A, IMM16B);
2268 z = (State.regs[REG_D0 + DN0] == 0);
2269 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2270 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2271 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2272 }
2273
2274
2275 // 1111 1100 1110 00Dn imm32...; and imm32,Dn
2276 8.0xfc+4.0xe,00,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::and
2277 "and"
2278 *mn10300
2279 // start-sanitize-am33
2280 *am33
2281 // end-sanitize-am33
2282 {
2283 /* OP_FCE00000 (); */
2284 int n, z;
2285
2286 PC = cia;
2287 State.regs[REG_D0 + DN0]
2288 &= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
2289 z = (State.regs[REG_D0 + DN0] == 0);
2290 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2291 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2292 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2293 }
2294
2295
2296 // 1111 1010 1111 1100 imm16...; and imm16,PSW (imm16 is zero-extended.)
2297 8.0xfa+8.0xfc+8.IMM16A+8.IMM16B:D2a:::and
2298 "and"
2299 *mn10300
2300 // start-sanitize-am33
2301 *am33
2302 // end-sanitize-am33
2303 {
2304 /* OP_FAFC0000 (); */
2305 PC = cia;
2306 PSW &= FETCH16(IMM16A, IMM16B);
2307 }
2308
2309
2310
2311 // 1111 0010 0001 DmDn; or DmDn
2312 8.0xf2+4.0x1,2.DM1,2.DN0:D0:::or
2313 "or"
2314 *mn10300
2315 // start-sanitize-am33
2316 *am33
2317 // end-sanitize-am33
2318 {
2319 /* OP_F210 (); */
2320 PC = cia;
2321 genericOr(State.regs[REG_D0 + DM1], REG_D0 + DN0);
2322 }
2323
2324
2325 // 1111 1000 1110 01Dn imm8....; or imm8,Dn (imm8 is zero-extended.)n
2326 8.0xf8+4.0xe,01,2.DN0+8.IMM8:D1:::or
2327 "or"
2328 *mn10300
2329 // start-sanitize-am33
2330 *am33
2331 // end-sanitize-am33
2332 {
2333 /* OP_F8E400 (); */
2334 PC = cia;
2335 genericOr(IMM8, REG_D0 + DN0);
2336 }
2337
2338
2339 // 1111 1010 1110 01Dn imm16...; or imm16,DN (imm16 is zero-extended.)
2340 8.0xfa+4.0xe,01,2.DN0+8.IMM16A+8.IMM16B:D2:::or
2341 "or"
2342 *mn10300
2343 // start-sanitize-am33
2344 *am33
2345 // end-sanitize-am33
2346 {
2347 /* OP_FAE40000 (); */
2348 PC = cia;
2349 genericOr(FETCH16(IMM16A, IMM16B), REG_D0 + DN0);
2350 }
2351
2352
2353 // 1111 1100 1110 01Dn imm32...; or imm32,Dn
2354 8.0xfc+4.0xe,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::or
2355 "or"
2356 *mn10300
2357 // start-sanitize-am33
2358 *am33
2359 // end-sanitize-am33
2360 {
2361 /* OP_FCE40000 (); */
2362 PC = cia;
2363 genericOr(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_D0 + DN0);
2364 }
2365
2366
2367 // 1111 1010 1111 1101 imm16...; or imm16,PSW (imm16 is zero-extended.)
2368 8.0xfa+8.0xfd+8.IMM16A+8.IMM16B:D2a:::or
2369 "or"
2370 *mn10300
2371 // start-sanitize-am33
2372 *am33
2373 // end-sanitize-am33
2374 {
2375 /* OP_FAFD0000 (); */
2376 PC = cia;
2377 PSW |= FETCH16(IMM16A, IMM16B);
2378 }
2379
2380
2381 // 1111 0010 0010 DmDn; xor Dm,Dn
2382 8.0xf2+4.0x2,2.DM1,2.DN0:D0:::xor
2383 "xor"
2384 *mn10300
2385 // start-sanitize-am33
2386 *am33
2387 // end-sanitize-am33
2388 {
2389 /* OP_F220 (); */
2390 PC = cia;
2391 genericXor(State.regs[REG_D0 + DM1], REG_D0 + DN0);
2392 }
2393
2394
2395 // 1111 1010 1110 10Dn imm16...; xor imm16,Dn (imm16 is zero-extended.)
2396 8.0xfa+4.0xe,10,2.DN0+8.IMM16A+8.IMM16B:D2:::xor
2397 "xor"
2398 *mn10300
2399 // start-sanitize-am33
2400 *am33
2401 // end-sanitize-am33
2402 {
2403 /* OP_FAE80000 (); */
2404 PC = cia;
2405 genericXor(FETCH16(IMM16A, IMM16B), REG_D0 + DN0);
2406 }
2407
2408
2409 // 1111 1100 1110 10Dn imm32...; xor imm32,Dn
2410 8.0xfc+4.0xe,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::xor
2411 "xor"
2412 *mn10300
2413 // start-sanitize-am33
2414 *am33
2415 // end-sanitize-am33
2416 {
2417 /* OP_FCE80000 (); */
2418 PC = cia;
2419 genericXor(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_D0 + DN0);
2420 }
2421
2422
2423 // 1111 0010 0011 00Dn; not Dn
2424 8.0xf2+4.0x3,00,2.DN0:D0:::not
2425 "not"
2426 *mn10300
2427 // start-sanitize-am33
2428 *am33
2429 // end-sanitize-am33
2430 {
2431 /* OP_F230 (); */
2432 int n, z;
2433
2434 PC = cia;
2435 State.regs[REG_D0 + DN0] = ~State.regs[REG_D0 + DN0];
2436 z = (State.regs[REG_D0 + DN0] == 0);
2437 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2438 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2439 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2440 }
2441
2442
2443 // 1111 1000 1110 11Dn imm8....; btst imm8,Dn (imm8 is zero-extended.)
2444 8.0xf8+4.0xe,11,2.DN0+8.IMM8:D1:::btst
2445 "btst"
2446 *mn10300
2447 // start-sanitize-am33
2448 *am33
2449 // end-sanitize-am33
2450 {
2451 /* OP_F8EC00 (); */
2452 PC = cia;
2453 genericBtst(IMM8, State.regs[REG_D0 + DN0]);
2454 }
2455
2456
2457 // 1111 1010 1110 11Dn imm16.....; btst imm16,Dn (imm16 is zero-extended.)
2458 8.0xfa+4.0xe,11,2.DN0+8.IMM16A+8.IMM16B:D2:::btst
2459 "btst"
2460 *mn10300
2461 // start-sanitize-am33
2462 *am33
2463 // end-sanitize-am33
2464 {
2465 /* OP_FAEC0000 (); */
2466 PC = cia;
2467 genericBtst(FETCH16(IMM16A, IMM16B), State.regs[REG_D0 + DN0]);
2468 }
2469
2470
2471 // 1111 1100 1110 11Dn imm32...; btst imm32,Dn
2472 8.0xfc+4.0xe,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::btst
2473 "btst"
2474 *mn10300
2475 // start-sanitize-am33
2476 *am33
2477 // end-sanitize-am33
2478 {
2479 /* OP_FCEC0000 (); */
2480 PC = cia;
2481 genericBtst(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
2482 State.regs[REG_D0 + DN0]);
2483 }
2484
2485
2486 // 1111 1110 0000 0010 abs32... imm8....; btst imm8,(abs32) (imm8 is zero-extended., processing unit: byte)
2487 8.0xfe+8.0x02+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D+8.IMM8:D5:::btst
2488 "btst"
2489 *mn10300
2490 // start-sanitize-am33
2491 *am33
2492 // end-sanitize-am33
2493 {
2494 /* OP_FE020000 (); */
2495 PC = cia;
2496 genericBtst(IMM8,
2497 load_byte(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
2498 }
2499
2500
2501 // 1111 1010 1111 10An d8...... imm8....;
2502 // btst imm8,(d8,An) (d8 is sign-extended,imm8 is zero-extended., processing unit: byte)
2503 8.0xfa+4.0xf,10,2.AN0+8.D8+8.IMM8:D2a:::btst
2504 "btst"
2505 *mn10300
2506 // start-sanitize-am33
2507 *am33
2508 // end-sanitize-am33
2509 {
2510 /* OP_FAF80000 (); */
2511 PC = cia;
2512 genericBtst(IMM8,
2513 load_byte(State.regs[REG_A0 + AN0] + EXTEND8(D8)));
2514 }
2515
2516
2517 // 1111 0000 1000 DmAn; bset Dm,(An) (Processing unit byte)
2518 8.0xf0+4.8,2.DM1,2.AN0:D0:::bset
2519 "bset"
2520 *mn10300
2521 // start-sanitize-am33
2522 *am33
2523 // end-sanitize-am33
2524 {
2525 /* OP_F080 (); */
2526 unsigned long temp;
2527 int z;
2528
2529 PC = cia;
2530 temp = load_byte (State.regs[REG_A0 + AN0]);
2531 z = (temp & State.regs[REG_D0 + DM1]) == 0;
2532 temp |= State.regs[REG_D0 + DM1];
2533 store_byte (State.regs[REG_A0 + AN0], temp);
2534 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2535 PSW |= (z ? PSW_Z : 0);
2536 }
2537
2538
2539 // 1111 1110 0000 0000 abs32... imm8....;
2540 // bset imm8,(abs32) (imm8 is zero-extended., processing unit: byte)
2541 8.0xfe+8.0x00+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D+8.IMM8:D5:::bset
2542 "bset"
2543 *mn10300
2544 // start-sanitize-am33
2545 *am33
2546 // end-sanitize-am33
2547 {
2548 /* OP_FE000000 (); */
2549 unsigned long temp;
2550 int z;
2551
2552 PC = cia;
2553 temp = load_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
2554 z = (temp & IMM8) == 0;
2555 temp |= IMM8;
2556 store_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), temp);
2557 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2558 PSW |= (z ? PSW_Z : 0);
2559 }
2560
2561
2562 // 1111 1010 1111 00AnAn d8...... imm8....;
2563 // bset imm8,(d8,An) (d8 is sign-extended, imm8 is zero-extended., processing unit: byte)
2564 8.0xfa+4.0xf,00,2.AN0+8.D8+8.IMM8:D2:::bset
2565 "bset"
2566 *mn10300
2567 // start-sanitize-am33
2568 *am33
2569 // end-sanitize-am33
2570 {
2571 /* OP_FAF00000 (); */
2572 unsigned long temp;
2573 int z;
2574
2575 PC = cia;
2576 temp = load_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)));
2577 z = (temp & (IMM8)) == 0;
2578 temp |= (IMM8);
2579 store_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)), temp);
2580 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2581 PSW |= (z ? PSW_Z : 0);
2582 }
2583
2584
2585 // 1111 0000 1001 DmAn; bclr Dm,(An) (Processing unit byte)
2586 8.0xf0+4.0x9,2.DM1,2.AN0:D0:::bclr
2587 "bclr"
2588 *mn10300
2589 // start-sanitize-am33
2590 *am33
2591 // end-sanitize-am33
2592 {
2593 /* OP_F090 (); */
2594 unsigned long temp;
2595 int z;
2596
2597 PC = cia;
2598 temp = load_byte (State.regs[REG_A0 + AN0]);
2599 z = (temp & State.regs[REG_D0 + DM1]) == 0;
2600 temp = temp & ~State.regs[REG_D0 + DM1];
2601 store_byte (State.regs[REG_A0 + AN0], temp);
2602 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2603 PSW |= (z ? PSW_Z : 0);
2604 }
2605
2606
2607 // 1111 1110 0000 0001 abs32... imm8....;
2608 // bclr imm8,(abs32) (imm8 is zero-extended., processing unit: byte)
2609 8.0xfe+8.0x01+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D+8.IMM8:D5:::bclr
2610 "bclr"
2611 *mn10300
2612 // start-sanitize-am33
2613 *am33
2614 // end-sanitize-am33
2615 {
2616 /* OP_FE010000 (); */
2617 unsigned long temp;
2618 int z;
2619
2620 PC = cia;
2621 temp = load_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
2622 z = (temp & IMM8) == 0;
2623 temp = temp & ~(IMM8);
2624 store_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), temp);
2625 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2626 PSW |= (z ? PSW_Z : 0);
2627 }
2628
2629
2630 // 1111 1010 1111 01An d8...... imm8....;
2631 // bclr imm8,(d8,An) (d8 is sign-extended, imm8 is zero-extended., processing unit: byte)
2632 8.0xfa+4.0xf,01,2.AN0+8.D8+8.IMM8:D2:::bclr
2633 "bclr"
2634 *mn10300
2635 // start-sanitize-am33
2636 *am33
2637 // end-sanitize-am33
2638 {
2639 /* OP_FAF40000 (); */
2640 unsigned long temp;
2641 int z;
2642
2643 PC = cia;
2644 temp = load_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)));
2645 z = (temp & (IMM8)) == 0;
2646 temp = temp & ~(IMM8);
2647 store_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)), temp);
2648 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2649 PSW |= (z ? PSW_Z : 0);
2650 }
2651
2652
2653 // 1111 0010 1011 DmDn; asr Dm,Dn
2654 8.0xf2+4.0xb,2.DM1,2.DN0:D0:::asr
2655 "asr"
2656 *mn10300
2657 // start-sanitize-am33
2658 *am33
2659 // end-sanitize-am33
2660 {
2661 /* OP_F2B0 (); */
2662 long temp;
2663 int z, n, c;
2664
2665 PC = cia;
2666 temp = State.regs[REG_D0 + DN0];
2667 c = temp & 1;
2668 temp >>= State.regs[REG_D0 + DM1];
2669 State.regs[REG_D0 + DN0] = temp;
2670 z = (State.regs[REG_D0 + DN0] == 0);
2671 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2672 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2673 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2674 }
2675
2676
2677 // 1111 1000 1100 10Dn imm8...; asr imm8,Dn (imm8 is zero-extended.)
2678 8.0xf8+4.0xc,10,2.DN0+8.IMM8:D1:::asr
2679 "asr"
2680 *mn10300
2681 // start-sanitize-am33
2682 *am33
2683 // end-sanitize-am33
2684 {
2685 /* OP_F8C800 (); */
2686 long temp;
2687 int z, n, c;
2688
2689 PC = cia;
2690 temp = State.regs[REG_D0 + DN0];
2691 c = temp & 1;
2692 temp >>= IMM8;
2693 State.regs[REG_D0 + DN0] = temp;
2694 z = (State.regs[REG_D0 + DN0] == 0);
2695 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2696 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2697 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2698 }
2699
2700
2701 // 1111 0010 1010 DmDn; lsr Dm,Dn
2702 8.0xf2+4.0xa,2.DM1,2.DN0:D0:::lsr
2703 "lsr"
2704 *mn10300
2705 // start-sanitize-am33
2706 *am33
2707 // end-sanitize-am33
2708 {
2709 /* OP_F2A0 (); */
2710 int z, n, c;
2711
2712 PC = cia;
2713 c = State.regs[REG_D0 + DN0] & 1;
2714 State.regs[REG_D0 + DN0]
2715 >>= State.regs[REG_D0 + DM1];
2716 z = (State.regs[REG_D0 + DN0] == 0);
2717 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2718 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2719 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2720 }
2721
2722
2723 // 1111 1000 1100 01Dn imm8...; lsr imm8,Dn (imm8 is zero-extended.)
2724 8.0xf8+4.0xc,01,2.DN0+8.IMM8:D1:::lsr
2725 "lsr"
2726 *mn10300
2727 // start-sanitize-am33
2728 *am33
2729 // end-sanitize-am33
2730 {
2731 /* OP_F8C400 (); */
2732 int z, n, c;
2733
2734 PC = cia;
2735 c = State.regs[REG_D0 + DN0] & 1;
2736 State.regs[REG_D0 + DN0] >>= IMM8;
2737 z = (State.regs[REG_D0 + DN0] == 0);
2738 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2739 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2740 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2741 }
2742
2743
2744 // 1111 0010 1001 DmDn; asl Dm,Dn
2745 8.0xf2+4.0x9,2.DM1,2.DN0:D0:::asl
2746 "asl"
2747 *mn10300
2748 // start-sanitize-am33
2749 *am33
2750 // end-sanitize-am33
2751 {
2752 /* OP_F290 (); */
2753 int n, z;
2754
2755 PC = cia;
2756 State.regs[REG_D0 + DN0]
2757 <<= State.regs[REG_D0 + DM1];
2758 z = (State.regs[REG_D0 + DN0] == 0);
2759 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2760 PSW &= ~(PSW_Z | PSW_N);
2761 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2762 }
2763
2764
2765 // 1111 1000 1100 00Dn imm8...; asl imm8,Dn (imm8 is zero-extended.)
2766 8.0xf8+4.0xc,00,2.DN0+8.IMM8:D1:::asl
2767 "asl"
2768 *mn10300
2769 // start-sanitize-am33
2770 *am33
2771 // end-sanitize-am33
2772 {
2773 /* OP_F8C000 (); */
2774 int n, z;
2775
2776 PC = cia;
2777 State.regs[REG_D0 + DN0] <<= IMM8;
2778 z = (State.regs[REG_D0 + DN0] == 0);
2779 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2780 PSW &= ~(PSW_Z | PSW_N);
2781 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2782 }
2783
2784
2785 // 0101 01Dn; als2 Dn
2786 4.0x5,01,2.DN0:S0:::asl2
2787 "asl2"
2788 *mn10300
2789 // start-sanitize-am33
2790 *am33
2791 // end-sanitize-am33
2792 {
2793 /* OP_54 (); */
2794 int n, z;
2795 PC = cia;
2796
2797 State.regs[REG_D0 + DN0] <<= 2;
2798 z = (State.regs[REG_D0 + DN0] == 0);
2799 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2800 PSW &= ~(PSW_Z | PSW_N);
2801 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2802 }
2803
2804
2805 // 1111 0010 1000 01Dn; ror Dn
2806 8.0xf2+4.0x8,01,2.DN0:D0:::ror
2807 "ror"
2808 *mn10300
2809 // start-sanitize-am33
2810 *am33
2811 // end-sanitize-am33
2812 {
2813 /* OP_F284 (); */
2814 unsigned long value;
2815 int c,n,z;
2816
2817 PC = cia;
2818 value = State.regs[REG_D0 + DN0];
2819 c = (value & 0x1);
2820
2821 value >>= 1;
2822 value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0;
2823 State.regs[REG_D0 + DN0] = value;
2824 z = (value == 0);
2825 n = (value & 0x80000000) != 0;
2826 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2827 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2828 }
2829
2830
2831 // 1111 0010 1000 00Dn; rol Dn
2832 8.0xf2+4.0x8,00,2.DN0:D0:::rol
2833 "rol"
2834 *mn10300
2835 // start-sanitize-am33
2836 *am33
2837 // end-sanitize-am33
2838 {
2839 /* OP_F280 (); */
2840 unsigned long value;
2841 int c,n,z;
2842
2843 PC = cia;
2844 value = State.regs[REG_D0 + DN0];
2845 c = (value & 0x80000000) ? 1 : 0;
2846
2847 value <<= 1;
2848 value |= ((PSW & PSW_C) != 0);
2849 State.regs[REG_D0 + DN0] = value;
2850 z = (value == 0);
2851 n = (value & 0x80000000) != 0;
2852 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2853 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2854 }
2855
2856
2857 // 1100 1000 d8......; beq (d8,PC) (d8 is sign-extended)
2858 8.0xc8+8.D8:S1:::beq
2859 "beq"
2860 *mn10300
2861 // start-sanitize-am33
2862 *am33
2863 // end-sanitize-am33
2864 {
2865 /* OP_C800 (); */
2866 PC = cia;
2867 if ((PSW & PSW_Z))
2868 {
2869 State.regs[REG_PC] += EXTEND8 (D8);
2870 nia = PC;
2871 }
2872 }
2873
2874
2875 // 1100 1001 d8......; bne (d8,PC) (d8 is sign-extended)
2876 8.0xc9+8.D8:S1:::bne
2877 "bne"
2878 *mn10300
2879 // start-sanitize-am33
2880 *am33
2881 // end-sanitize-am33
2882 {
2883 /* OP_C900 (); */
2884 PC = cia;
2885 if (!(PSW & PSW_Z))
2886 {
2887 State.regs[REG_PC] += EXTEND8 (D8);
2888 nia = PC;
2889 }
2890 }
2891
2892
2893 // 1100 0001 d8......; bgt (d8,PC) (d8 is sign-extended)
2894 8.0xc1+8.D8:S1:::bgt
2895 "bgt"
2896 *mn10300
2897 // start-sanitize-am33
2898 *am33
2899 // end-sanitize-am33
2900 {
2901 /* OP_C100 (); */
2902 PC = cia;
2903 if (!((PSW & PSW_Z)
2904 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))))
2905 {
2906 State.regs[REG_PC] += EXTEND8 (D8);
2907 nia = PC;
2908 }
2909 }
2910
2911
2912 // 1100 0010 d8......; bge (d8,PC) (d8 is sign-extended)
2913 8.0xc2+8.D8:S1:::bge
2914 "bge"
2915 *mn10300
2916 // start-sanitize-am33
2917 *am33
2918 // end-sanitize-am33
2919 {
2920 /* OP_C200 (); */
2921 PC = cia;
2922 if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
2923 {
2924 State.regs[REG_PC] += EXTEND8 (D8);
2925 nia = PC;
2926 }
2927 }
2928
2929
2930 // 1100 0011 d8......; ble (d8,PC) (d8 is sign-extended)
2931 8.0xc3+8.D8:S1:::ble
2932 "ble"
2933 *mn10300
2934 // start-sanitize-am33
2935 *am33
2936 // end-sanitize-am33
2937 {
2938 /* OP_C300 (); */
2939 PC = cia;
2940 if ((PSW & PSW_Z)
2941 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
2942 {
2943 State.regs[REG_PC] += EXTEND8 (D8);
2944 nia = PC;
2945 }
2946 }
2947
2948
2949 // 1100 0000 d8......; blt (d8,PC) (d8 is sign-extended)
2950 8.0xc0+8.D8:S1:::blt
2951 "blt"
2952 *mn10300
2953 // start-sanitize-am33
2954 *am33
2955 // end-sanitize-am33
2956 {
2957 /* OP_C000 (); */
2958 PC = cia;
2959 if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))
2960 {
2961 State.regs[REG_PC] += EXTEND8 (D8);
2962 nia = PC;
2963 }
2964 }
2965
2966
2967 // 1100 0101 d8......; bhi (d8,PC) (d8 is sign-extended)
2968 8.0xc5+8.D8:S1:::bhi
2969 "bhi"
2970 *mn10300
2971 // start-sanitize-am33
2972 *am33
2973 // end-sanitize-am33
2974 {
2975 /* OP_C500 (); */
2976 PC = cia;
2977 if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
2978 {
2979 State.regs[REG_PC] += EXTEND8 (D8);
2980 nia = PC;
2981 }
2982 }
2983
2984
2985 // 1100 0110 d8......; bcc (d8,PC) (d8 is sign-extended)
2986 8.0xc6+8.D8:S1:::bcc
2987 "bcc"
2988 *mn10300
2989 // start-sanitize-am33
2990 *am33
2991 // end-sanitize-am33
2992 {
2993 /* OP_C600 (); */
2994 PC = cia;
2995 if (!(PSW & PSW_C))
2996 {
2997 State.regs[REG_PC] += EXTEND8 (D8);
2998 nia = PC;
2999 }
3000 }
3001
3002
3003 // 1100 0101 d8......; bls (d8,PC) (d8 is sign-extended)
3004 8.0xc7+8.D8:S1:::bls
3005 "bls"
3006 *mn10300
3007 // start-sanitize-am33
3008 *am33
3009 // end-sanitize-am33
3010 {
3011 /* OP_C700 (); */
3012 PC = cia;
3013 if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
3014 {
3015 State.regs[REG_PC] += EXTEND8 (D8);
3016 nia = PC;
3017 }
3018 }
3019
3020
3021 // 1100 0100 d8......; bcs (d8,PC) (d8 is sign-extended)
3022 8.0xc4+8.D8:S1:::bcs
3023 "bcs"
3024 *mn10300
3025 // start-sanitize-am33
3026 *am33
3027 // end-sanitize-am33
3028 {
3029 /* OP_C400 (); */
3030 PC = cia;
3031 if (PSW & PSW_C)
3032 {
3033 State.regs[REG_PC] += EXTEND8 (D8);
3034 nia = PC;
3035 }
3036 }
3037
3038
3039 // 1111 1000 1110 1000 d8......; bvc (d8,PC) (d8 is sign-extended)
3040 8.0xf8+8.0xe8+8.D8:D1:::bvc
3041 "bvc"
3042 *mn10300
3043 // start-sanitize-am33
3044 *am33
3045 // end-sanitize-am33
3046 {
3047 /* OP_F8E800 (); */
3048 PC = cia;
3049 if (!(PSW & PSW_V))
3050 {
3051 State.regs[REG_PC] += EXTEND8 (D8);
3052 nia = PC;
3053 }
3054 }
3055
3056
3057 // 1111 1000 1110 1001 d8......; bvs (d8,PC) (d8 is sign-extended)
3058 8.0xf8+8.0xe9+8.D8:D1:::bvs
3059 "bvs"
3060 *mn10300
3061 // start-sanitize-am33
3062 *am33
3063 // end-sanitize-am33
3064 {
3065 /* OP_F8E900 (); */
3066 PC = cia;
3067 if (PSW & PSW_V)
3068 {
3069 State.regs[REG_PC] += EXTEND8 (D8);
3070 nia = PC;
3071 }
3072 }
3073
3074
3075 // 1111 1000 1110 1010 d8......; bnc (d8,PC) (d8 is sign-extended)
3076 8.0xf8+8.0xea+8.D8:D1:::bnc
3077 "bnc"
3078 *mn10300
3079 // start-sanitize-am33
3080 *am33
3081 // end-sanitize-am33
3082 {
3083 /* OP_F8EA00 (); */
3084 PC = cia;
3085 if (!(PSW & PSW_N))
3086 {
3087 State.regs[REG_PC] += EXTEND8 (D8);
3088 nia = PC;
3089 }
3090 }
3091
3092
3093 // 1111 1000 1110 1010 d8......; bns (d8,PC) (d8 is sign-extended)
3094 8.0xf8+8.0xeb+8.D8:D1:::bns
3095 "bns"
3096 *mn10300
3097 // start-sanitize-am33
3098 *am33
3099 // end-sanitize-am33
3100 {
3101 /* OP_F8EB00 (); */
3102 PC = cia;
3103 if (PSW & PSW_N)
3104 {
3105 State.regs[REG_PC] += EXTEND8 (D8);
3106 nia = PC;
3107 }
3108 }
3109
3110
3111 // 1100 1010 d8......; bra (d8,PC) (d8 is sign-extended)
3112 8.0xca+8.D8:S1:::bra
3113 "bra"
3114 *mn10300
3115 // start-sanitize-am33
3116 *am33
3117 // end-sanitize-am33
3118 {
3119 /* OP_CA00 (); */
3120 PC = cia;
3121 State.regs[REG_PC] += EXTEND8 (D8);
3122 nia = PC;
3123 }
3124
3125
3126 // 1101 1000; leq
3127 8.0xd8:S0:::leq
3128 "leq"
3129 *mn10300
3130 // start-sanitize-am33
3131 *am33
3132 // end-sanitize-am33
3133 {
3134 /* OP_D8 (); */
3135 PC = cia;
3136 if (PSW & PSW_Z)
3137 {
3138 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3139 nia = PC;
3140 }
3141 }
3142
3143
3144 // 1101 1001; lne
3145 8.0xd9:S0:::lne
3146 "lne"
3147 *mn10300
3148 // start-sanitize-am33
3149 *am33
3150 // end-sanitize-am33
3151 {
3152 /* OP_D9 (); */
3153 PC = cia;
3154 if (!(PSW & PSW_Z))
3155 {
3156 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3157 nia = PC;
3158 }
3159 }
3160
3161
3162 // 1101 0001; lgt
3163 8.0xd1:S0:::lgt
3164 "lgt"
3165 *mn10300
3166 // start-sanitize-am33
3167 *am33
3168 // end-sanitize-am33
3169 {
3170 /* OP_D1 (); */
3171 PC = cia;
3172 if (!((PSW & PSW_Z)
3173 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))))
3174 {
3175 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3176 nia = PC;
3177 }
3178 }
3179
3180
3181 // 1101 0010; lge
3182 8.0xd2:S0:::lge
3183 "lge"
3184 *mn10300
3185 // start-sanitize-am33
3186 *am33
3187 // end-sanitize-am33
3188 {
3189 /* OP_D2 (); */
3190 PC = cia;
3191 if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
3192 {
3193 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3194 nia = PC;
3195 }
3196 }
3197
3198
3199 // 1101 0011; lle
3200 8.0xd3:S0:::lle
3201 "lle"
3202 *mn10300
3203 // start-sanitize-am33
3204 *am33
3205 // end-sanitize-am33
3206 {
3207 /* OP_D3 (); */
3208 PC = cia;
3209 if ((PSW & PSW_Z)
3210 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
3211 {
3212 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3213 nia = PC;
3214 }
3215 }
3216
3217
3218 // 1101 0000; llt
3219 8.0xd0:S0:::llt
3220 "llt"
3221 *mn10300
3222 // start-sanitize-am33
3223 *am33
3224 // end-sanitize-am33
3225 {
3226 /* OP_D0 (); */
3227 PC = cia;
3228 if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))
3229 {
3230 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3231 nia = PC;
3232 }
3233 }
3234
3235
3236 // 1101 0101; lhi
3237 8.0xd5:S0:::lhi
3238 "lhi"
3239 *mn10300
3240 // start-sanitize-am33
3241 *am33
3242 // end-sanitize-am33
3243 {
3244 /* OP_D5 (); */
3245 PC = cia;
3246 if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
3247 {
3248 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3249 nia = PC;
3250 }
3251 }
3252
3253
3254 // 1101 0110; lcc
3255 8.0xd6:S0:::lcc
3256 "lcc"
3257 *mn10300
3258 // start-sanitize-am33
3259 *am33
3260 // end-sanitize-am33
3261 {
3262 /* OP_D6 (); */
3263 PC = cia;
3264 if (!(PSW & PSW_C))
3265 {
3266 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3267 nia = PC;
3268 }
3269 }
3270
3271
3272 // 1101 0111; lls
3273 8.0xd7:S0:::lls
3274 "lls"
3275 *mn10300
3276 // start-sanitize-am33
3277 *am33
3278 // end-sanitize-am33
3279 {
3280 /* OP_D7 (); */
3281 PC = cia;
3282 if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
3283 {
3284 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3285 nia = PC;
3286 }
3287 }
3288
3289
3290 // 1101 0100; lcs
3291 8.0xd4:S0:::lcs
3292 "lcs"
3293 *mn10300
3294 // start-sanitize-am33
3295 *am33
3296 // end-sanitize-am33
3297 {
3298 /* OP_D4 (); */
3299 PC = cia;
3300 if (PSW & PSW_C)
3301 {
3302 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3303 nia = PC;
3304 }
3305 }
3306
3307
3308 // 1101 1010; lra
3309 8.0xda:S0:::lra
3310 "lra"
3311 *mn10300
3312 // start-sanitize-am33
3313 *am33
3314 // end-sanitize-am33
3315 {
3316 /* OP_DA (); */
3317 PC = cia;
3318 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
3319 nia = PC;
3320 }
3321
3322
3323 // 1101 1010; setlb
3324 8.0xdb:S0:::setlb
3325 "setlb"
3326 *mn10300
3327 // start-sanitize-am33
3328 *am33
3329 // end-sanitize-am33
3330 {
3331 /* OP_DB (); */
3332 PC = cia;
3333 State.regs[REG_LIR] = load_word (State.regs[REG_PC] + 1);
3334 State.regs[REG_LAR] = State.regs[REG_PC] + 5;
3335 }
3336
3337
3338 // 1111 0000 1111 01An; jmp (An)
3339 8.0xf0+4.0xf,01,2.AN0:D0:::jmp
3340 "jmp"
3341 *mn10300
3342 // start-sanitize-am33
3343 *am33
3344 // end-sanitize-am33
3345 {
3346 /* OP_F0F4 (); */
3347 PC = State.regs[REG_A0 + AN0];
3348 nia = PC;
3349 }
3350
3351
3352 // 1100 1100 d16.....; jmp (d16,PC) (d16 is sign-extended.)
3353 8.0xcc+8.D16A+8.D16B:S2:::jmp
3354 "jmp"
3355 *mn10300
3356 // start-sanitize-am33
3357 *am33
3358 // end-sanitize-am33
3359 {
3360 /* OP_CC0000 (); */
3361 PC = cia + EXTEND16(FETCH16(D16A, D16B));
3362 nia = PC;
3363 }
3364
3365
3366 // 1101 1100 d32........; jmp (d32, PC)
3367 8.0xdc+8.D32A+8.D32B+8.D32C+8.D32D:S4:::jmp
3368 "jmp"
3369 *mn10300
3370 // start-sanitize-am33
3371 *am33
3372 // end-sanitize-am33
3373 {
3374 /* OP_DC000000 (); */
3375 PC = cia + FETCH32(D32A, D32B, D32C, D32D);
3376 nia = PC;
3377 }
3378
3379
3380 // 1111 0000 1111 00An; calls (An)
3381 8.0xf0+4.0xf,00,2.AN0:D0:::calls
3382 "calls"
3383 *mn10300
3384 // start-sanitize-am33
3385 *am33
3386 // end-sanitize-am33
3387 {
3388 /* OP_F0F0 (); */
3389 unsigned int next_pc, sp;
3390
3391 PC = cia;
3392 sp = State.regs[REG_SP];
3393 next_pc = State.regs[REG_PC] + 2;
3394 store_word(sp, next_pc);
3395 State.regs[REG_MDR] = next_pc;
3396 State.regs[REG_PC] = State.regs[REG_A0 + AN0];
3397 nia = PC;
3398 }
3399
3400
3401 // 1111 1010 1111 1111 d16.....; calls (d16,PC) (d16 is sign-extended.)
3402 8.0xfa+8.0xff+8.D16A+8.D16B:D2:::calls
3403 "calls"
3404 *mn10300
3405 // start-sanitize-am33
3406 *am33
3407 // end-sanitize-am33
3408 {
3409 /* OP_FAFF0000 (); */
3410 unsigned int next_pc, sp;
3411
3412 PC = cia;
3413 sp = State.regs[REG_SP];
3414 next_pc = State.regs[REG_PC] + 4;
3415 store_word(sp, next_pc);
3416 State.regs[REG_MDR] = next_pc;
3417 State.regs[REG_PC] += EXTEND16 (FETCH16(D16A, D16B));
3418 nia = PC;
3419 }
3420
3421
3422 // 1111 1100 1111 1111 d32.....; calls (d32,PC)
3423 8.0xfc+8.0xff+8.D32A+8.D32B+8.D32C+8.D32D:D4:::calls
3424 "calls"
3425 *mn10300
3426 // start-sanitize-am33
3427 *am33
3428 // end-sanitize-am33
3429 {
3430 /* OP_FCFF0000 (); */
3431 unsigned int next_pc, sp;
3432
3433 PC = cia;
3434 sp = State.regs[REG_SP];
3435 next_pc = State.regs[REG_PC] + 6;
3436 store_word(sp, next_pc);
3437 State.regs[REG_MDR] = next_pc;
3438 State.regs[REG_PC] += FETCH32(D32A, D32B, D32C, D32D);
3439 nia = PC;
3440 }
3441
3442
3443 // 1111 0000 1111 1100; rets
3444 8.0xf0+8.0xfc:D0:::rets
3445 "rets"
3446 *mn10300
3447 // start-sanitize-am33
3448 *am33
3449 // end-sanitize-am33
3450 {
3451 /* OP_F0FC (); */
3452 unsigned int sp;
3453
3454 sp = State.regs[REG_SP];
3455 State.regs[REG_PC] = load_word(sp);
3456 nia = PC;
3457 }
3458
3459
3460 // 1111 0000 1111 1101; rti
3461 8.0xf0+8.0xfd:D0:::rti
3462 "rti"
3463 *mn10300
3464 // start-sanitize-am33
3465 *am33
3466 // end-sanitize-am33
3467 {
3468 /* OP_F0FD (); */
3469 unsigned int sp;
3470
3471 sp = State.regs[REG_SP];
3472 PSW = load_half(sp);
3473 State.regs[REG_PC] = load_word(sp+4);
3474 State.regs[REG_SP] +=8;
3475 nia = PC;
3476 }
3477
3478
3479 // 1111 0000 1111 1110; trap
3480 8.0xf0+8.0xfe:D0:::trap
3481 "trap"
3482 *mn10300
3483 // start-sanitize-am33
3484 *am33
3485 // end-sanitize-am33
3486 {
3487 /* OP_F0FE (); */
3488 unsigned int sp, next_pc;
3489
3490 PC = cia;
3491 sp = State.regs[REG_SP];
3492 next_pc = State.regs[REG_PC] + 2;
3493 store_word(sp, next_pc);
3494 nia = PC;
3495 }
3496
3497
3498 // 1111 0000 1111 1111; rtm
3499 8.0xf0+8.0xff:D0:::rtm
3500 "rtm"
3501 *mn10300
3502 // start-sanitize-am33
3503 *am33
3504 // end-sanitize-am33
3505 {
3506 /* OP_F0FF (); */
3507 PC = cia;
3508 abort ();
3509 }
3510
3511
3512 // 1100 1011; nop
3513 8.0xcb:S0:::nop
3514 "nop"
3515 *mn10300
3516 // start-sanitize-am33
3517 *am33
3518 // end-sanitize-am33
3519 {
3520 /* OP_CB (); */
3521 PC = cia;
3522 }
3523
3524
3525 // 1111 0101 0000 DmDn; udf20 Dm,Dn
3526 8.0xf5+4.0x0,2.DM1,2.DN0:D0:::putx
3527 "putx"
3528 *mn10300
3529 {
3530 /* OP_F500 (); */
3531 PC = cia;
3532 State.regs[REG_MDRQ] = State.regs[REG_D0 + DN0];
3533 }
3534
3535
3536 // 1111 0110 1111 DmDn; udf15 Dm,Dn
3537 8.0xf6+4.0xf,2.DM1,2.DN0:D0:::getx
3538 "getx"
3539 *mn10300
3540 // start-sanitize-am33
3541 *am33
3542 // end-sanitize-am33
3543 {
3544 /* OP_F6F0 (); */
3545 int z, n;
3546
3547 PC = cia;
3548 z = (State.regs[REG_MDRQ] == 0);
3549 n = ((State.regs[REG_MDRQ] & 0x80000000) != 0);
3550 State.regs[REG_D0 + DN0] = State.regs[REG_MDRQ];
3551
3552 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3553 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
3554 }
3555
3556
3557 // 1111 0110 0000 DmDn; udf00 Dm,Dn
3558 8.0xf6+4.0x0,2.DM1,2.DN0:D0:::mulq
3559 "mulq"
3560 *mn10300
3561 // start-sanitize-am33
3562 *am33
3563 // end-sanitize-am33
3564 {
3565 /* OP_F600 (); */
3566 unsigned long long temp;
3567 int n, z;
3568
3569 PC = cia;
3570 temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
3571 * (signed64)(signed32)State.regs[REG_D0 + DM1]);
3572 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3573 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3574 z = (State.regs[REG_D0 + DN0] == 0);
3575 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3576 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3577 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3578 }
3579
3580
3581 // 1111 1001 0000 00Dn imm8....; udf00 imm8,Dn (imm8 is sign-extended.)
3582 8.0xf9+4.0x,00,2.DN0+8.IMM8:D1:::mulq
3583 "mulq"
3584 *mn10300
3585 // start-sanitize-am33
3586 *am33
3587 // end-sanitize-am33
3588 {
3589 /* OP_F90000 (); */
3590 unsigned long long temp;
3591 int n, z;
3592
3593 PC = cia;
3594 temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
3595 * (signed64)(signed32)EXTEND8 (IMM8));
3596 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3597 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3598 z = (State.regs[REG_D0 + DN0] == 0);
3599 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3600 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3601 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3602 }
3603
3604
3605 // 1111 1011 0000 00Dn imm16...; udf00 imm16,Dn (imm16 is sign-extended.)
3606 8.0xfb+4.0x0,00,2.DN0+8.IMM16A+8.IMM16B:D2:::mulq
3607 "mulq"
3608 *mn10300
3609 // start-sanitize-am33
3610 *am33
3611 // end-sanitize-am33
3612 {
3613 /* OP_FB000000 (); */
3614 unsigned long long temp;
3615 int n, z;
3616
3617 PC = cia;
3618 temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
3619 * (signed64)(signed32)EXTEND16 (FETCH16(IMM16A, IMM16B)));
3620 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3621 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3622 z = (State.regs[REG_D0 + DN0] == 0);
3623 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3624 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3625 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3626 }
3627
3628
3629 // 1111 1101 0000 00Dn imm32...; udf00 imm32,Dn
3630 8.0xfd+4.0x0,00,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::mulq
3631 "mulq"
3632 *mn10300
3633 // start-sanitize-am33
3634 *am33
3635 // end-sanitize-am33
3636 {
3637 /* OP_FD000000 (); */
3638 unsigned long long temp;
3639 int n, z;
3640
3641 PC = cia;
3642 temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
3643 * (signed64)(signed32)(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
3644 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3645 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3646 z = (State.regs[REG_D0 + DN0] == 0);
3647 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3648 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3649 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3650 }
3651
3652
3653 // 1111 0110 0001 DmDn; udf01 Dm,Dn
3654 8.0xf6+4.0x1,2.DM1,2.DN0:D0:::mulqu
3655 "mulqu"
3656 *mn10300
3657 // start-sanitize-am33
3658 *am33
3659 // end-sanitize-am33
3660 {
3661 /* OP_F610 (); */
3662 unsigned long long temp;
3663 int n, z;
3664
3665 PC = cia;
3666 temp = ((unsigned64) State.regs[REG_D0 + DN0]
3667 * (unsigned64) State.regs[REG_D0 + DM1]);
3668 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3669 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3670 z = (State.regs[REG_D0 + DN0] == 0);
3671 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3672 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3673 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3674 }
3675
3676
3677 // 1111 1001 0001 01Dn imm8....; udfu01 imm8,Dn (imm8 is zero-extended.)
3678 8.0xf9+4.0x1,01,2.DN0+8.IMM8:D1:::mulqu
3679 "mulqu"
3680 *mn10300
3681 // start-sanitize-am33
3682 *am33
3683 // end-sanitize-am33
3684 {
3685 /* OP_F91400 (); */
3686 unsigned long long temp;
3687 int n, z;
3688
3689 PC = cia;
3690 temp = ((unsigned64)State.regs[REG_D0 + DN0]
3691 * (unsigned64)EXTEND8 (IMM8));
3692 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3693 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3694 z = (State.regs[REG_D0 + DN0] == 0);
3695 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3696 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3697 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3698 }
3699
3700
3701 // 1111 1011 0001 01Dn imm16...; udfu01 imm16,Dn (imm16 is zero-extended.)
3702 8.0xfb+4.0x1,01,2.DN0+8.IMM16A+8.IMM16B:D2:::mulqu
3703 "mulqu"
3704 *mn10300
3705 // start-sanitize-am33
3706 *am33
3707 // end-sanitize-am33
3708 {
3709 /* OP_FB140000 (); */
3710 unsigned long long temp;
3711 int n, z;
3712
3713 PC = cia;
3714 temp = ((unsigned64)State.regs[REG_D0 + DN0]
3715 * (unsigned64) EXTEND16 (FETCH16(IMM16A, IMM16B)));
3716 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3717 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3718 z = (State.regs[REG_D0 + DN0] == 0);
3719 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3720 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3721 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3722 }
3723
3724
3725 // 1111 1101 0001 01Dn imm32...; udfu01 imm32,Dn
3726 8.0xfd+4.0x1,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::mulqu
3727 "mulqu"
3728 *mn10300
3729 // start-sanitize-am33
3730 *am33
3731 // end-sanitize-am33
3732 {
3733 /* OP_FD140000 (); */
3734 unsigned long long temp;
3735 int n, z;
3736
3737 PC = cia;
3738 temp = ((unsigned64)State.regs[REG_D0 + DN0]
3739 * (unsigned64)(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
3740 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3741 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3742 z = (State.regs[REG_D0 + DN0] == 0);
3743 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3744 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3745 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3746 }
3747
3748
3749 // 1111 0110 0100 DmDn; udf04 Dm,Dn
3750 8.0xf6+4.0x4,2.DM1,2.DN0:D0:::sat16
3751 "sat16"
3752 *mn10300
3753 // start-sanitize-am33
3754 *am33
3755 // end-sanitize-am33
3756 {
3757 /* OP_F640 (); */
3758 int temp;
3759
3760 PC = cia;
3761 temp = State.regs[REG_D0 + DM1];
3762 temp = (temp > 0x7fff ? 0x7fff : temp);
3763 temp = (temp < -0x8000 ? -0x8000 : temp);
3764 State.regs[REG_D0 + DN0] = temp;
3765 }
3766
3767
3768 // 1111 0110 0101 DmDn; udf05 Dm,Dn
3769 8.0xf6+4.0x5,2.DM1,2.DN0:D0:::sat24
3770 "sat24"
3771 *mn10300
3772 // start-sanitize-am33
3773 *am33
3774 // end-sanitize-am33
3775 {
3776 /* OP_F650 (); */
3777 int temp;
3778
3779 PC = cia;
3780 temp = State.regs[REG_D0 + DM1];
3781 temp = (temp > 0x7fffff ? 0x7fffff : temp);
3782 temp = (temp < -0x800000 ? -0x800000 : temp);
3783 State.regs[REG_D0 + DN0] = temp;
3784 }
3785
3786
3787 // 1111 0110 0111 DmDn; udf07 Dm,Dn
3788 8.0xf6+4.0x7,2.DM1,2.DN0:D0:::bsch
3789 "bsch"
3790 *mn10300
3791 // start-sanitize-am33
3792 *am33
3793 // end-sanitize-am33
3794 {
3795 /* OP_F670 (); */
3796 int temp, c;
3797
3798 PC = cia;
3799 temp = State.regs[REG_D0 + DM1];
3800 temp <<= (State.regs[REG_D0 + DN0] & 0x1f);
3801 c = (temp != 0 ? 1 : 0);
3802 PSW &= ~(PSW_C);
3803 PSW |= (c ? PSW_C : 0);
3804 }
3805
3806
3807 // 1111 0000 1100 0000; syscall
3808 8.0xf0+8.0xc0:D0:::syscall
3809 "syscall"
3810 *mn10300
3811 // start-sanitize-am33
3812 *am33
3813 // end-sanitize-am33
3814 {
3815 /* OP_F0C0 (); */
3816 PC = cia;
3817 do_syscall ();
3818 }
3819
3820
3821 // 1111 1111; break
3822 8.0xff:S0:::break
3823 "break"
3824 *mn10300
3825 // start-sanitize-am33
3826 *am33
3827 // end-sanitize-am33
3828 {
3829 /* OP_FF (); */
3830 PC = cia;
3831 sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
3832 PC -= 1;
3833 }
3834
3835 // 1100 1110 regs....; movm (SP),regs
3836 8.0xce+8.REGS:S1:::movm
3837 "movm"
3838 *mn10300
3839 // start-sanitize-am33
3840 *am33
3841 // end-sanitize-am33
3842 {
3843 /* OP_CE00 (); */
3844 unsigned long sp = State.regs[REG_SP];
3845 unsigned long mask;
3846
3847 PC = cia;
3848 mask = REGS;
3849
3850 if (mask & 0x8)
3851 {
3852 sp += 4;
3853 State.regs[REG_LAR] = load_word (sp);
3854 sp += 4;
3855 State.regs[REG_LIR] = load_word (sp);
3856 sp += 4;
3857 State.regs[REG_MDR] = load_word (sp);
3858 sp += 4;
3859 State.regs[REG_A0 + 1] = load_word (sp);
3860 sp += 4;
3861 State.regs[REG_A0] = load_word (sp);
3862 sp += 4;
3863 State.regs[REG_D0 + 1] = load_word (sp);
3864 sp += 4;
3865 State.regs[REG_D0] = load_word (sp);
3866 sp += 4;
3867 }
3868
3869 if (mask & 0x10)
3870 {
3871 State.regs[REG_A0 + 3] = load_word (sp);
3872 sp += 4;
3873 }
3874
3875 if (mask & 0x20)
3876 {
3877 State.regs[REG_A0 + 2] = load_word (sp);
3878 sp += 4;
3879 }
3880
3881 if (mask & 0x40)
3882 {
3883 State.regs[REG_D0 + 3] = load_word (sp);
3884 sp += 4;
3885 }
3886
3887 if (mask & 0x80)
3888 {
3889 State.regs[REG_D0 + 2] = load_word (sp);
3890 sp += 4;
3891 }
3892
3893 /* start-sanitize-am33 */
3894 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
3895 {
3896 if (mask & 0x1)
3897 {
3898 /* Need to restore MDQR, MCRH, MCRL, and MCVF */
3899 sp += 16;
3900 State.regs[REG_E0 + 1] = load_word (sp);
3901 sp += 4;
3902 State.regs[REG_E0 + 0] = load_word (sp);
3903 sp += 4;
3904 }
3905
3906 if (mask & 0x2)
3907 {
3908 State.regs[REG_E0 + 7] = load_word (sp);
3909 sp += 4;
3910 State.regs[REG_E0 + 6] = load_word (sp);
3911 sp += 4;
3912 State.regs[REG_E0 + 5] = load_word (sp);
3913 sp += 4;
3914 State.regs[REG_E0 + 4] = load_word (sp);
3915 sp += 4;
3916 }
3917
3918 if (mask & 0x4)
3919 {
3920 State.regs[REG_E0 + 3] = load_word (sp);
3921 sp += 4;
3922 State.regs[REG_E0 + 2] = load_word (sp);
3923 sp += 4;
3924 }
3925 }
3926 /* end-sanitize-am33 */
3927
3928 /* And make sure to update the stack pointer. */
3929 State.regs[REG_SP] = sp;
3930 }
3931
3932
3933 // 1100 1111 regs....; movm regs,(SP)
3934 8.0xcf+8.REGS:S1a:::movm
3935 "movm"
3936 *mn10300
3937 // start-sanitize-am33
3938 *am33
3939 // end-sanitize-am33
3940 {
3941 /* OP_CF00 (); */
3942 unsigned long sp = State.regs[REG_SP];
3943 unsigned long mask;
3944
3945 PC = cia;
3946 mask = REGS;
3947
3948 /* start-sanitize-am33 */
3949 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
3950 {
3951 if (mask & 0x4)
3952 {
3953 sp -= 4;
3954 store_word (sp, State.regs[REG_E0 + 2]);
3955 sp -= 4;
3956 store_word (sp, State.regs[REG_E0 + 3]);
3957 }
3958
3959 if (mask & 0x2)
3960 {
3961 sp -= 4;
3962 store_word (sp, State.regs[REG_E0 + 4]);
3963 sp -= 4;
3964 store_word (sp, State.regs[REG_E0 + 5]);
3965 sp -= 4;
3966 store_word (sp, State.regs[REG_E0 + 6]);
3967 sp -= 4;
3968 store_word (sp, State.regs[REG_E0 + 7]);
3969 }
3970
3971 if (mask & 0x1)
3972 {
3973 sp -= 4;
3974 store_word (sp, State.regs[REG_E0 + 0]);
3975 sp -= 4;
3976 store_word (sp, State.regs[REG_E0 + 1]);
3977 sp -= 16;
3978 /* Need to save MDQR, MCRH, MCRL, and MCVF */
3979 }
3980 }
3981 /* end-sanitize-am33 */
3982
3983 if (mask & 0x80)
3984 {
3985 sp -= 4;
3986 store_word (sp, State.regs[REG_D0 + 2]);
3987 }
3988
3989 if (mask & 0x40)
3990 {
3991 sp -= 4;
3992 store_word (sp, State.regs[REG_D0 + 3]);
3993 }
3994
3995 if (mask & 0x20)
3996 {
3997 sp -= 4;
3998 store_word (sp, State.regs[REG_A0 + 2]);
3999 }
4000
4001 if (mask & 0x10)
4002 {
4003 sp -= 4;
4004 store_word (sp, State.regs[REG_A0 + 3]);
4005 }
4006
4007 if (mask & 0x8)
4008 {
4009 sp -= 4;
4010 store_word (sp, State.regs[REG_D0]);
4011 sp -= 4;
4012 store_word (sp, State.regs[REG_D0 + 1]);
4013 sp -= 4;
4014 store_word (sp, State.regs[REG_A0]);
4015 sp -= 4;
4016 store_word (sp, State.regs[REG_A0 + 1]);
4017 sp -= 4;
4018 store_word (sp, State.regs[REG_MDR]);
4019 sp -= 4;
4020 store_word (sp, State.regs[REG_LIR]);
4021 sp -= 4;
4022 store_word (sp, State.regs[REG_LAR]);
4023 sp -= 4;
4024 }
4025
4026 /* And make sure to update the stack pointer. */
4027 State.regs[REG_SP] = sp;
4028 }
4029
4030 // 1100 1101 d16..... regs.... imm8....;
4031 // call (d16,PC),regs,imm8 (d16 is sign-extended., imm8 is zero-extended.)
4032 8.0xcd+8.D16A+8.D16B+8.REGS+8.IMM8:S4:::call
4033 "call"
4034 *mn10300
4035 // start-sanitize-am33
4036 *am33
4037 // end-sanitize-am33
4038 {
4039 /* OP_CD000000 (); */
4040 unsigned int next_pc, sp;
4041 unsigned long mask;
4042
4043 PC = cia;
4044 sp = State.regs[REG_SP];
4045 next_pc = PC + 5;
4046 store_word(sp, next_pc);
4047
4048 mask = REGS;
4049
4050 /* start-sanitize-am33 */
4051 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
4052 {
4053 if (mask & 0x4)
4054 {
4055 sp -= 4;
4056 store_word (sp, State.regs[REG_E0 + 2]);
4057 sp -= 4;
4058 store_word (sp, State.regs[REG_E0 + 3]);
4059 }
4060
4061 if (mask & 0x2)
4062 {
4063 sp -= 4;
4064 store_word (sp, State.regs[REG_E0 + 4]);
4065 sp -= 4;
4066 store_word (sp, State.regs[REG_E0 + 5]);
4067 sp -= 4;
4068 store_word (sp, State.regs[REG_E0 + 6]);
4069 sp -= 4;
4070 store_word (sp, State.regs[REG_E0 + 7]);
4071 }
4072
4073 if (mask & 0x1)
4074 {
4075 sp -= 4;
4076 store_word (sp, State.regs[REG_E0 + 0]);
4077 sp -= 4;
4078 store_word (sp, State.regs[REG_E0 + 1]);
4079 sp -= 16;
4080 /* Need to save MDQR, MCRH, MCRL, and MCVF */
4081 }
4082 }
4083 /* end-sanitize-am33 */
4084
4085 if (mask & 0x80)
4086 {
4087 sp -= 4;
4088 store_word (sp, State.regs[REG_D0 + 2]);
4089 }
4090
4091 if (mask & 0x40)
4092 {
4093 sp -= 4;
4094 store_word (sp, State.regs[REG_D0 + 3]);
4095 }
4096
4097 if (mask & 0x20)
4098 {
4099 sp -= 4;
4100 store_word (sp, State.regs[REG_A0 + 2]);
4101 }
4102
4103 if (mask & 0x10)
4104 {
4105 sp -= 4;
4106 store_word (sp, State.regs[REG_A0 + 3]);
4107 }
4108
4109 if (mask & 0x8)
4110 {
4111 sp -= 4;
4112 store_word (sp, State.regs[REG_D0]);
4113 sp -= 4;
4114 store_word (sp, State.regs[REG_D0 + 1]);
4115 sp -= 4;
4116 store_word (sp, State.regs[REG_A0]);
4117 sp -= 4;
4118 store_word (sp, State.regs[REG_A0 + 1]);
4119 sp -= 4;
4120 store_word (sp, State.regs[REG_MDR]);
4121 sp -= 4;
4122 store_word (sp, State.regs[REG_LIR]);
4123 sp -= 4;
4124 store_word (sp, State.regs[REG_LAR]);
4125 sp -= 4;
4126 }
4127
4128 /* Update the stack pointer, note that the register saves to do not
4129 modify SP. The SP adjustment is derived totally from the imm8
4130 field. */
4131 State.regs[REG_SP] -= IMM8;
4132 State.regs[REG_MDR] = next_pc;
4133 State.regs[REG_PC] += EXTEND16 (FETCH16(D16A, D16B));
4134 nia = PC;
4135 }
4136
4137
4138 // 1101 1101 d32..... regs.... imm8....;
4139 // call (d32,PC),regs,imm8 (imm8 is zero-extended.)
4140 8.0xdd+8.D32A+8.D32B+8.D32C+8.D32D+8.REGS+8.IMM8:S6:::call
4141 "call"
4142 *mn10300
4143 // start-sanitize-am33
4144 *am33
4145 // end-sanitize-am33
4146 {
4147 /* OP_DD000000 (); */
4148 unsigned int next_pc, sp;
4149 unsigned long mask;
4150
4151 PC = cia;
4152 sp = State.regs[REG_SP];
4153 next_pc = State.regs[REG_PC] + 7;
4154 /* could assert that nia == next_pc here */
4155 store_word(sp, next_pc);
4156
4157 mask = REGS;
4158
4159 /* start-sanitize-am33 */
4160 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
4161 {
4162 if (mask & 0x4)
4163 {
4164 sp -= 4;
4165 store_word (sp, State.regs[REG_E0 + 2]);
4166 sp -= 4;
4167 store_word (sp, State.regs[REG_E0 + 3]);
4168 }
4169
4170 if (mask & 0x2)
4171 {
4172 sp -= 4;
4173 store_word (sp, State.regs[REG_E0 + 4]);
4174 sp -= 4;
4175 store_word (sp, State.regs[REG_E0 + 5]);
4176 sp -= 4;
4177 store_word (sp, State.regs[REG_E0 + 6]);
4178 sp -= 4;
4179 store_word (sp, State.regs[REG_E0 + 7]);
4180 }
4181
4182 if (mask & 0x1)
4183 {
4184 sp -= 4;
4185 store_word (sp, State.regs[REG_E0 + 0]);
4186 sp -= 4;
4187 store_word (sp, State.regs[REG_E0 + 1]);
4188 sp -= 16;
4189 /* Need to save MDQR, MCRH, MCRL, and MCVF */
4190 }
4191 }
4192 /* end-sanitize-am33 */
4193
4194 if (mask & 0x80)
4195 {
4196 sp -= 4;
4197 store_word (sp, State.regs[REG_D0 + 2]);
4198 }
4199
4200 if (mask & 0x40)
4201 {
4202 sp -= 4;
4203 store_word (sp, State.regs[REG_D0 + 3]);
4204 }
4205
4206 if (mask & 0x20)
4207 {
4208 sp -= 4;
4209 store_word (sp, State.regs[REG_A0 + 2]);
4210 }
4211
4212 if (mask & 0x10)
4213 {
4214 sp -= 4;
4215 store_word (sp, State.regs[REG_A0 + 3]);
4216 }
4217
4218 if (mask & 0x8)
4219 {
4220 sp -= 4;
4221 store_word (sp, State.regs[REG_D0]);
4222 sp -= 4;
4223 store_word (sp, State.regs[REG_D0 + 1]);
4224 sp -= 4;
4225 store_word (sp, State.regs[REG_A0]);
4226 sp -= 4;
4227 store_word (sp, State.regs[REG_A0 + 1]);
4228 sp -= 4;
4229 store_word (sp, State.regs[REG_MDR]);
4230 sp -= 4;
4231 store_word (sp, State.regs[REG_LIR]);
4232 sp -= 4;
4233 store_word (sp, State.regs[REG_LAR]);
4234 sp -= 4;
4235 }
4236
4237 /* Update the stack pointer, note that the register saves to do not
4238 modify SP. The SP adjustment is derived totally from the imm8
4239 field. */
4240 State.regs[REG_SP] -= IMM8;
4241 State.regs[REG_MDR] = next_pc;
4242 State.regs[REG_PC] += FETCH32(D32A, D32B, D32C, D32D);
4243 nia = PC;
4244 }
4245
4246
4247 // 1101 1111 regs.... imm8....; ret regs,imm8 (imm8 is zero-extended.)
4248 8.0xdf+8.REGS+8.IMM8:S2:::ret
4249 "ret"
4250 *mn10300
4251 // start-sanitize-am33
4252 *am33
4253 // end-sanitize-am33
4254 {
4255 /* OP_DF0000 (); */
4256 unsigned int sp, offset;
4257 unsigned long mask;
4258
4259 PC = cia;
4260 State.regs[REG_SP] += IMM8;
4261 sp = State.regs[REG_SP];
4262
4263 offset = -4;
4264 mask = REGS;
4265
4266 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
4267 {
4268
4269 if (mask & 0x4)
4270 {
4271 State.regs[REG_E0 + 2] = load_word (sp + offset);
4272 offset -= 4;
4273 State.regs[REG_E0 + 3] = load_word (sp + offset);
4274 offset -= 4;
4275 }
4276
4277 if (mask & 0x2)
4278 {
4279 State.regs[REG_E0 + 4] = load_word (sp + offset);
4280 offset -= 4;
4281 State.regs[REG_E0 + 5] = load_word (sp + offset);
4282 offset -= 4;
4283 State.regs[REG_E0 + 6] = load_word (sp + offset);
4284 offset -= 4;
4285 State.regs[REG_E0 + 7] = load_word (sp + offset);
4286 offset -= 4;
4287 }
4288
4289 if (mask & 0x1)
4290 {
4291 /* Need to restore MDQR, MCRH, MCRL, and MCVF */
4292 offset -= 16;
4293 State.regs[REG_E0 + 0] = load_word (sp + offset);
4294 offset -= 4;
4295 State.regs[REG_E0 + 1] = load_word (sp + offset);
4296 offset -= 4;
4297 }
4298
4299 }
4300
4301 if (mask & 0x80)
4302 {
4303 State.regs[REG_D0 + 2] = load_word (sp + offset);
4304 offset -= 4;
4305 }
4306
4307 if (mask & 0x40)
4308 {
4309 State.regs[REG_D0 + 3] = load_word (sp + offset);
4310 offset -= 4;
4311 }
4312
4313 if (mask & 0x20)
4314 {
4315 State.regs[REG_A0 + 2] = load_word (sp + offset);
4316 offset -= 4;
4317 }
4318
4319 if (mask & 0x10)
4320 {
4321 State.regs[REG_A0 + 3] = load_word (sp + offset);
4322 offset -= 4;
4323 }
4324
4325 if (mask & 0x8)
4326 {
4327 State.regs[REG_D0] = load_word (sp + offset);
4328 offset -= 4;
4329 State.regs[REG_D0 + 1] = load_word (sp + offset);
4330 offset -= 4;
4331 State.regs[REG_A0] = load_word (sp + offset);
4332 offset -= 4;
4333 State.regs[REG_A0 + 1] = load_word (sp + offset);
4334 offset -= 4;
4335 State.regs[REG_MDR] = load_word (sp + offset);
4336 offset -= 4;
4337 State.regs[REG_LIR] = load_word (sp + offset);
4338 offset -= 4;
4339 State.regs[REG_LAR] = load_word (sp + offset);
4340 offset -= 4;
4341 }
4342
4343 /* Restore the PC value. */
4344 State.regs[REG_PC] = load_word(sp);
4345 nia = PC;
4346 }
4347
4348
4349 // 1101 1110 regs.... imm8....; retf regs,imm8 (imm8 is zero-extended.)
4350 8.0xde+8.REGS+8.IMM8:S2:::retf
4351 "retf"
4352 *mn10300
4353 // start-sanitize-am33
4354 *am33
4355 // end-sanitize-am33
4356 {
4357 /* OP_DE0000 (); */
4358 unsigned int sp, offset;
4359 unsigned long mask;
4360
4361 PC = cia;
4362 State.regs[REG_SP] += IMM8;
4363 sp = State.regs[REG_SP];
4364 State.regs[REG_PC] = State.regs[REG_MDR] - 3;
4365
4366 offset = -4;
4367 mask = REGS;
4368
4369 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
4370 {
4371
4372 if (mask & 0x4)
4373 {
4374 State.regs[REG_E0 + 2] = load_word (sp + offset);
4375 offset -= 4;
4376 State.regs[REG_E0 + 3] = load_word (sp + offset);
4377 offset -= 4;
4378 }
4379
4380 if (mask & 0x2)
4381 {
4382 State.regs[REG_E0 + 4] = load_word (sp + offset);
4383 offset -= 4;
4384 State.regs[REG_E0 + 5] = load_word (sp + offset);
4385 offset -= 4;
4386 State.regs[REG_E0 + 6] = load_word (sp + offset);
4387 offset -= 4;
4388 State.regs[REG_E0 + 7] = load_word (sp + offset);
4389 offset -= 4;
4390 }
4391
4392 if (mask & 0x1)
4393 {
4394 /* Need to restore MDQR, MCRH, MCRL, and MCVF */
4395 offset -= 16;
4396 State.regs[REG_E0 + 0] = load_word (sp + offset);
4397 offset -= 4;
4398 State.regs[REG_E0 + 1] = load_word (sp + offset);
4399 offset -= 4;
4400 }
4401
4402 }
4403
4404 if (mask & 0x80)
4405 {
4406 State.regs[REG_D0 + 2] = load_word (sp + offset);
4407 offset -= 4;
4408 }
4409
4410 if (mask & 0x40)
4411 {
4412 State.regs[REG_D0 + 3] = load_word (sp + offset);
4413 offset -= 4;
4414 }
4415
4416 if (mask & 0x20)
4417 {
4418 State.regs[REG_A0 + 2] = load_word (sp + offset);
4419 offset -= 4;
4420 }
4421
4422 if (mask & 0x10)
4423 {
4424 State.regs[REG_A0 + 3] = load_word (sp + offset);
4425 offset -= 4;
4426 }
4427
4428 if (mask & 0x8)
4429 {
4430 State.regs[REG_D0] = load_word (sp + offset);
4431 offset -= 4;
4432 State.regs[REG_D0 + 1] = load_word (sp + offset);
4433 offset -= 4;
4434 State.regs[REG_A0] = load_word (sp + offset);
4435 offset -= 4;
4436 State.regs[REG_A0 + 1] = load_word (sp + offset);
4437 offset -= 4;
4438 State.regs[REG_MDR] = load_word (sp + offset);
4439 offset -= 4;
4440 State.regs[REG_LIR] = load_word (sp + offset);
4441 offset -= 4;
4442 State.regs[REG_LAR] = load_word (sp + offset);
4443 offset -= 4;
4444 }
4445 }
4446
4447 // start-sanitize-am33
4448 :include::am33:am33.igen
4449 // end-sanitize-am33
GDB Binutils - Deliverables
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