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IGEN input files for mn10300 simulator.
[deliverable/binutils-gdb.git] / sim / mn10300 / mn10300.igen
1 :option:::insn-bit-size:8
2 :option:::insn-specifying-widths:true
3 :option:::hi-bit-nr:7
4 :model:::mn10300:mn10300:
5
6 // What do we do with an illegal instruction?
7 :internal::::illegal:
8 {
9 sim_io_eprintf (SD, "Illegal instruction at address 0x%lx\n",
10 (unsigned long) cia);
11 sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
12 }
13
14 // 1000 DnDn imm8....; mov imm8,Dn (imm8 is sign extended)
15 // 1000 DmDn; mov Dm,Dn (Dm != Dn, see above when Dm == Dn)
16 4.0x8,2.DM1,2.DN0:S0:::mov
17 "mov"
18 *mn10300
19 {
20 PC = cia;
21 if ( DM1 == DN0 )
22 {
23 // OP_8000 ();
24 signed32 immed = EXTEND8 (IMEM8_IMMED (cia, 1));
25 nia = cia + 2;
26 State.regs[REG_D0+DN0] = immed;
27 }
28 else
29 {
30 // OP_80 ();
31 State.regs[REG_D0+DN0] = State.regs[REG_D0+DM1];
32 }
33 }
34
35
36 // 1111 0001 1110 DmAn; mov Dm,An
37 8.0xf1+1110,2.DM1,2.AN0:D0:::mov
38 "mov"
39 *mn10300
40 {
41 // OP_F1E0 ();
42 PC = cia;
43 State.regs[REG_A0 + AN0] = State.regs[REG_D0 + DM1];
44 }
45
46
47 // 1111 0001 1101 AmDn; mov Am,Dn
48 8.0xf1+1101,2.AM1,2.DN0:D0a:::mov
49 "mov"
50 *mn10300
51 {
52 // OP_F1D0 ();
53 PC = cia;
54 State.regs[REG_D0 + DN0] = State.regs[REG_A0 + AM1];
55 }
56
57
58 // 1001 AnAn imm8....; mov imm8,An (imm8 is zero-extended)
59 // 1001 AmAn; mov Am,An (Am != An, save above when Am == An)
60 4.0x9,2.AM1,2.AN0:S0a:::mov
61 "mov"
62 *mn10300
63 {
64 PC = cia;
65 if ( AM1 == AN0 )
66 {
67 // OP_9000 ();
68 unsigned long immed = IMEM8_IMMED (cia, 1);
69 nia = cia + 2;
70 State.regs[REG_A0+AN0] = immed;
71 }
72 else
73 {
74 // OP_90 ();
75 State.regs[REG_A0+AN0] = State.regs[REG_A0+AM1];
76 }
77 }
78
79
80 // 0011 11An; mov SP,An
81 4.0x3,11,2.AN0:S0b:::mov
82 "mov"
83 *mn10300
84 {
85 // OP_3C ();
86 PC = cia;
87 State.regs[REG_A0 + AN0] = State.regs[REG_SP];
88 }
89
90
91 // 1111 0010 1111 Am00; mov Am,SP
92 8.0xf2+4.0xf,2.AM1,00:D0b:::mov
93 "mov"
94 *mn10300
95 {
96 // OP_F2F0 ();
97 PC = cia;
98 State.regs[REG_SP] = State.regs[REG_A0 + AM1];
99 }
100
101
102 // 1111 0010 1110 01Dn; mov PSW,Dn
103 8.0xf2+4.0xe,01,2.DN0:D0c:::mov
104 "mov"
105 *mn10300
106 {
107 // OP_F2E4 ();
108 PC = cia;
109 State.regs[REG_D0 + DN0] = PSW;
110 }
111
112
113 // 1111 0010 1111 Dm11; mov Dm,PSW
114 8.0xf2+4.0xf,2.DM1,11:D0d:::mov
115 "mov"
116 *mn10300
117 {
118 // OP_F2F3 ();
119 PC = cia;
120 PSW = State.regs[REG_D0 + DM1];
121 }
122
123
124 // 1111 0010 1110 00Dn; mov MDR,Dn
125 8.0xf2+4.0xe,00,2.DN0:D0e:::mov
126 "mov"
127 *mn10300
128 {
129 // OP_F2E0 ();
130 PC = cia;
131 State.regs[REG_D0 + DN0] = State.regs[REG_MDR];
132 }
133
134
135 // 1111 0010 1111 Dm10; mov Dm,MDR
136 8.0xf2+4.0xf,2.DM1,10:D0f:::mov
137 "mov"
138 *mn10300
139 {
140 // OP_F2F2 ();
141 PC = cia;
142 State.regs[REG_MDR] = State.regs[REG_D0 + DM1];
143 }
144
145
146 // 0111 DnAm; mov (Am),Dn
147 4.0x7,2.DN1,2.AM0:S0c:::mov
148 "mov"
149 *mn10300
150 {
151 // OP_70 ();
152 PC = cia;
153 State.regs[REG_D0 + DN1] = load_word (State.regs[REG_A0 + AM0]);
154 }
155
156
157 // 1111 1000 0000 DnAm d8......; mov (d8,Am),Dn (d8 is sign-extended)
158 8.0xf8+4.0x0,2.DN1,2.AM0+8.D8:D1:::mov
159 "mov"
160 *mn10300
161 {
162 // OP_F80000 ();
163 PC = cia;
164 State.regs[REG_D0 + DN1]
165 = load_word ((State.regs[REG_A0 + AM0] + EXTEND8 (D8)));
166 }
167
168
169 // 1111 1010 0000 DnAm d16.....; mov (d16,Am),Dn (d16 is sign-extended.)
170 8.0xfa+4.0x0,2.DN1,2.AM0+8.D16A+8.D16B:D2:::mov
171 "mov"
172 *mn10300
173 {
174 // OP_FA000000 ();
175 PC = cia;
176 State.regs[REG_D0 + DN1]
177 = load_word ((State.regs[REG_A0 + AM0] + EXTEND16 (FETCH16(D16A, D16B))));
178 }
179
180
181 // 1111 1100 0000 DnAm d32.....; mov (d32,Am),Dn
182 8.0xfc+4.0x0,2.DN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::mov
183 "mov"
184 *mn10300
185 {
186 // OP_FC000000 ();
187 PC = cia;
188 State.regs[REG_D0 + DN1]
189 = load_word ((State.regs[REG_A0 + AM0]
190 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
191 }
192
193
194 // 0101 10Dn d8......; mov (d8,SP),Dn (d8 is zero-extended)
195 4.0x5,10,2.DN0+8.D8:S1:::mov
196 "mov"
197 *mn10300
198 {
199 // OP_5800 ();
200 PC = cia;
201 State.regs[REG_D0 + DN0] = load_word (State.regs[REG_SP] + D8);
202 }
203
204
205 // 1111 1010 1011 01Dn d16.....; mov (d16,SP),Dn (d16 is zero-extended.)
206 8.0xfa+4.0xb,01,2.DN0+8.IMM16A+8.IMM16B:D2a:::mov
207 "mov"
208 *mn10300
209 {
210 // OP_FAB40000 ();
211 PC = cia;
212 State.regs[REG_D0 + DN0]
213 = load_word (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B));
214 }
215
216
217 // 1111 1010 1011 01Dn d32.....; mov (d32,SP),Dn
218 8.0xfc+4.0xb,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::mov
219 "mov"
220 *mn10300
221 {
222 // OP_FCB40000 ();
223 PC = cia;
224 State.regs[REG_D0 + DN0]
225 = load_word (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
226 }
227
228
229 // 1111 0011 00Dn DiAm; mov (Di,Am),Dn
230 8.0xf3+00,2.DI,2.AM0,2.DN2:D0g:::mov
231 "mov"
232 *mn10300
233 {
234 // OP_F300 ();
235 PC = cia;
236 State.regs[REG_D0 + DN2]
237 = load_word ((State.regs[REG_A0 + AM0] + State.regs[REG_D0 + DI]));
238 }
239
240
241 // 0011 00Dn abs16...; mov (abs16),Dn (abs16 is zero-extended)
242 4.0x3,00,2.DN0+8.IMM16A+8.IMM16B:S2:::mov
243 "mov"
244 *mn10300
245 {
246 // OP_300000 ();
247 PC = cia;
248 State.regs[REG_D0 + DN0] = load_word (FETCH16(IMM16A, IMM16B));
249 }
250
251 // 1111 1100 1010 01Dn abs32...; mov (abs32),Dn
252 8.0xfc+4.0xa,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::mov
253 "mov"
254 *mn10300
255 {
256 // OP_FCA40000 ();
257 PC = cia;
258 State.regs[REG_D0 + DN0] = load_word (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
259 }
260
261
262 // 1111 0000 0000 AnAm; mov (Am),An
263 8.0xf0+4.0x0,2.AN1,2.AM0:D0h:::mov
264 "mov"
265 *mn10300
266 {
267 // OP_F000 ();
268 PC = cia;
269 State.regs[REG_A0 + AN1] = load_word (State.regs[REG_A0 + AM0]);
270 }
271
272
273 // 1111 1000 0010 AnAm d8......; mov (d8,Am),An (d8 is sign-extended)
274 8.0xf8+4.0x2,2.AN1,2.AM0+8.D8:D1a:::mov
275 "mov"
276 *mn10300
277 {
278 // OP_F82000 ();
279 PC = cia;
280 State.regs[REG_A0 + AN1]
281 = load_word ((State.regs[REG_A0 + AM0] + EXTEND8 (D8)));
282 }
283
284
285 // 1111 1010 0010 AnAm d16.....; mov (d16,Am),An (d16 is sign-extended.)
286 8.0xfa+4.0x2,2.AN1,2.AM0+8.D16A+8.D16B:D2b:::mov
287 "mov"
288 *mn10300
289 {
290 // OP_FA200000 ();
291 PC = cia;
292 State.regs[REG_A0 + AN1]
293 = load_word ((State.regs[REG_A0 + AM0]
294 + EXTEND16 (FETCH16(D16A, D16B))));
295 }
296
297
298 // 1111 1100 0010 AnAm d32.....; mov (d32,Am),An
299 8.0xfc+4.0x2,2.AN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4c:::mov
300 "mov"
301 *mn10300
302 {
303 // OP_FC200000 ();
304 PC = cia;
305 State.regs[REG_A0 + AN1]
306 = load_word ((State.regs[REG_A0 + AM0]
307 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
308 }
309
310
311 // 0101 11An d8......; mov (d8,SP),An (d8 is zero-extended)
312 4.0x5,11,2.AN0+8.D8:S1a:::mov
313 "mov"
314 *mn10300
315 {
316 // OP_5C00 ();
317 PC = cia;
318 State.regs[REG_A0 + AN0]
319 = load_word (State.regs[REG_SP] + D8);
320 }
321
322
323 // 1111 1010 1011 00An d16.....; mov (d16,SP),An (d16 is zero-extended.)
324 8.0xfa+4.0xb,00,2.AN0+8.IMM16A+8.IMM16B:D2c:::mov
325 "mov"
326 *mn10300
327 {
328 // OP_FAB00000 ();
329 PC = cia;
330 State.regs[REG_A0 + AN0]
331 = load_word (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B));
332 }
333
334
335 // 1111 1100 1011 00An d32.....; mov (d32,SP),An
336 8.0xfc+4.0xb,00,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4d:::mov
337 "mov"
338 *mn10300
339 {
340 // OP_FCB00000 ();
341 PC = cia;
342 State.regs[REG_A0 + AN0]
343 = load_word (State.regs[REG_SP]
344 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
345 }
346
347
348 // 1111 0011 10An DiAm; mov (Di,Am),An
349 8.0xf3+10,2.AN2,2.DI,2.AM0:D0i:::mov
350 "mov"
351 *mn10300
352 {
353 // OP_F380 ();
354 PC = cia;
355 State.regs[REG_A0 + AN2]
356 = load_word ((State.regs[REG_A0 + AM0]
357 + State.regs[REG_D0 + DI]));
358 }
359
360
361 // 1111 1010 1010 00An abs16...; mov (abs16),An (abs16 is zero-extended)
362 8.0xfa+4.0xa,00,2.AN0+8.IMM16A+8.IMM16B:D2d:::mov
363 "mov"
364 *mn10300
365 {
366 // OP_FAA00000 ();
367 PC = cia;
368 State.regs[REG_A0 + AN0] = load_word (FETCH16(IMM16A, IMM16B));
369 }
370
371
372 // 1111 1100 1010 00An abs32...; mov (abs32),An
373 8.0xfc+4.0xa,00,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4e:::mov
374 "mov"
375 *mn10300
376 {
377 // OP_FCA00000 ();
378 PC = cia;
379 State.regs[REG_A0 + AN0]
380 = load_word (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
381 }
382
383
384 // 1111 1000 1111 00Am d8......; mov (d8,Am),SP (d8 is sign-extended)
385 8.0xf8+4.0xf,00,2.AM0+8.D8:D1b:::mov
386 "mov"
387 *mn10300
388 {
389 // OP_F8F000 ();
390 PC = cia;
391 State.regs[REG_SP]
392 = load_word ((State.regs[REG_A0 + AM0] + EXTEND8 (D8)));
393 }
394
395
396 // 0110 DmAn; mov Dm,(An)
397 4.0x6,2.DM1,2.AN0:S0d:::mov
398 "mov"
399 *mn10300
400 {
401 // OP_60 ();
402 PC = cia;
403 store_word (State.regs[REG_A0 + AN0], State.regs[REG_D0 + DM1]);
404 }
405
406
407 // 1111 1000 0001 DmAn d8......; mov Dm,(d8,An) (d8 is sign-extended)
408 8.0xf8+4.0x1,2.DM1,2.AN0+8.D8:D1c:::mov
409 "mov"
410 *mn10300
411 {
412 // OP_F81000 ();
413 PC = cia;
414 store_word ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)),
415 State.regs[REG_D0 + DM1]);
416 }
417
418
419 // 1111 1010 0001 DmAn d16.....; mov Dm,(d16,An) (d16 is sign-extended.)
420 8.0xfa+4.0x1,2.DM1,2.AN0+8.D16A+8.D16B:D2e:::mov
421 "mov"
422 *mn10300
423 {
424 // OP_FA100000 ();
425 PC = cia;
426 store_word ((State.regs[REG_A0 + AN0] + EXTEND16 (FETCH16(D16A, D16B))),
427 State.regs[REG_D0 + DM1]);
428 }
429
430
431 // 1111 1100 0001 DmAn d32.....; mov Dm,(d32,An)
432 8.0xfc+4.0x1,2.DM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4f:::mov
433 "mov"
434 *mn10300
435 {
436 // OP_FC100000 ();
437 PC = cia;
438 store_word ((State.regs[REG_A0 + AN0]
439 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)),
440 State.regs[REG_D0 + DM1]);
441 }
442
443
444 // 0100 Dm10 d8......; mov Dm,(d8,SP) (d8 is zero-extended)
445 4.0x4,2.DM1,10+8.D8:S1b:::mov
446 "mov"
447 *mn10300
448 {
449 // OP_4200 ();
450 PC = cia;
451 store_word (State.regs[REG_SP] + D8, State.regs[REG_D0 + DM1]);
452 }
453
454
455 // 1111 1010 1001 Dm01 d16.....; mov Dm,(d16,SP) (d16 is zero-extended.)
456 8.0xfa+4.0x9,2.DM1,01+8.IMM16A+8.IMM16B:D2f:::mov
457 "mov"
458 *mn10300
459 {
460 // OP_FA910000 ();
461 PC = cia;
462 store_word (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B),
463 State.regs[REG_D0 + DM1]);
464 }
465
466
467 // 1111 1100 1001 Dm01 d32.....; mov Dm,(d32,SP)
468 8.0xfc+4.0x9,2.DM1,01+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4g:::mov
469 "mov"
470 *mn10300
471 {
472 // OP_FC910000 ();
473 PC = cia;
474 store_word (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
475 State.regs[REG_D0 + DM1]);
476 }
477
478
479 // 1111 0011 01Dm DiAn; mov Dm,(Di,An)
480 8.0xf3+01,2.DM2,2.DI,2.AN0:D0j:::mov
481 "mov"
482 *mn10300
483 {
484 // OP_F340 ();
485 PC = cia;
486 store_word ((State.regs[REG_A0 + AN0] + State.regs[REG_D0 + DI]),
487 State.regs[REG_D0 + DM2]);
488 }
489
490
491 // 0000 Dm01 abs16..., mov Dm,(abs16) (abs16 is zero-extended).
492 4.0x0,2.DM1,01+8.IMM16A+8.IMM16B:S2a:::mov
493 "mov"
494 *mn10300
495 {
496 // OP_10000 ();
497 PC = cia;
498 store_word (FETCH16(IMM16A, IMM16B), State.regs[REG_D0 + DM1]);
499 }
500
501
502 // 1111 1100 1000 Dm01 abs32...; mov Dm,(abs32)
503 8.0xfc+4.0x8,2.DM1,01+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4h:::mov
504 "mov"
505 *mn10300
506 {
507 // OP_FC810000 ();
508 PC = cia;
509 store_word (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
510 State.regs[REG_D0 + DM1]);
511 }
512
513
514 // 1111 0000 0001 AmAn; mov Am,(An)
515 8.0xf0+4.0x1,2.AM1,2.AN0:D0k:::mov
516 "mov"
517 *mn10300
518 {
519 // OP_F010 ();
520 PC = cia;
521 store_word (State.regs[REG_A0 + AN0], State.regs[REG_A0 + AM1]);
522 }
523
524
525 // 1111 1000 0011 AmAn d8......; mov Am,(d8,An) (d8 is sign-extended)
526 8.0xf8+4.0x3,2.AM1,2.AN0+8.D8:D1d:::mov
527 "mov"
528 *mn10300
529 {
530 // OP_F83000 ();
531 PC = cia;
532 store_word ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)),
533 State.regs[REG_A0 + AM1]);
534 }
535
536
537 // 1111 1010 0011 AmAn d16.....; mov Am,(d16,An) (d16 is sign-extended.)
538 8.0xfa+4.0x3,2.AM1,2.AN0+8.D16A+8.D16B:D2g:::mov
539 "mov"
540 *mn10300
541 {
542 // OP_FA300000 ();
543 PC = cia;
544 store_word ((State.regs[REG_A0 + AN0] + EXTEND16 (FETCH16(D16A, D16B))),
545 State.regs[REG_A0 + AM1]);
546 }
547
548
549 // 1111 1100 0011 AmAn d32.....; mov Am,(d32,An)
550 8.0xfc+4.0x3,2.AM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4i:::mov
551 "mov"
552 *mn10300
553 {
554 // OP_FC300000 ();
555 PC = cia;
556 store_word ((State.regs[REG_A0 + AN0]
557 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)),
558 State.regs[REG_A0 + AM1]);
559 }
560
561
562 // 0100 Am11 d8......; mov Am,(d8,SP) (d8 is zero-extended)
563 4.0x4,2.AM1,11+8.D8:S1c:::mov
564 "mov"
565 *mn10300
566 {
567 // OP_4300 ();
568 PC = cia;
569 store_word (State.regs[REG_SP] + (D8), State.regs[REG_A0 + (AM1)]);
570 }
571
572
573 // 1111 1010 1001 Am00 d16.....; mov Am,(d16,SP) (d16 is zero-extended.)
574 8.0xfa+4.0x9,2.AM1,00+8.IMM16A+8.IMM16B:D2h:::mov
575 "mov"
576 *mn10300
577 {
578 // OP_FA900000 ();
579 PC = cia;
580 store_word (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B),
581 State.regs[REG_A0 + AM1]);
582 }
583
584
585 // 1111 1100 1001 Am00 d32.....; mov Am,(d32,SP)
586 8.0xfc+4.0x9,2.AM1,00+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4j:::mov
587 "mov"
588 *mn10300
589 {
590 // OP_FC900000 ();
591 PC = cia;
592 store_word (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
593 State.regs[REG_A0 + AM1]);
594 }
595
596
597 // 1111 0011 11Am DiAn; mov Am,(Di,An)
598 8.0xf3+11,2.AM2,2.DI,2.AN0:D0l:::mov
599 "mov"
600 *mn10300
601 {
602 // OP_F3C0 ();
603 PC = cia;
604 store_word ((State.regs[REG_A0 + AN0] + State.regs[REG_D0 + DI]),
605 State.regs[REG_A0 + AM2]);
606 }
607
608
609 // 1111 1010 1000 Am00 abs16...; mov Am,(abs16) (abs16 is zero-extended)
610 8.0xfa+4.0x8,2.AM1,00+8.IMM16A+8.IMM16B:D2i:::mov
611 "mov"
612 *mn10300
613 {
614 // OP_FA800000 ();
615 PC = cia;
616 store_word (FETCH16(IMM16A, IMM16B),
617 State.regs[REG_A0 + AM1]);
618 }
619
620
621 // 1111 1100 1000 Am00 abs32...; mov Am,(abs32)
622 8.0xfc+4.0x8,2.AM1,00+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4k:::mov
623 "mov"
624 *mn10300
625 {
626 // OP_FC800000 ();
627 PC = cia;
628 store_word (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
629 State.regs[REG_A0 + AM1]);
630 }
631
632
633 // 1111 1000 1111 01An d8......; mov SP,(d8,An) (d8 is sign-extended)
634 8.0xf8+4.0xf,01,2.AN0+8.D8:D1e:::mov
635 "mov"
636 *mn10300
637 {
638 // OP_F8F400 ();
639 PC = cia;
640 store_word (State.regs[REG_A0 + AN0] + EXTEND8 (D8),
641 State.regs[REG_SP]);
642 }
643
644
645 // 0010 11Dn imm16...; mov imm16,Dn (imm16 is sign-extended)
646 4.0x2,11,2.DN0+8.IMM16A+8.IMM16B:S2b:::mov
647 "mov"
648 *mn10300
649 {
650 // OP_2C0000 ();
651 unsigned long value;
652
653 PC = cia;
654 value = EXTEND16 (FETCH16(IMM16A, IMM16B));
655 State.regs[REG_D0 + DN0] = value;
656 }
657
658
659 // 1111 1100 1100 11Dn imm32...; mov imm32,Dn
660 8.0xfc+4.0xc,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4l:::mov
661 "mov"
662 *mn10300
663 {
664 // OP_FCCC0000 ();
665 unsigned long value;
666
667 PC = cia;
668 value = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
669 State.regs[REG_D0 + DN0] = value;
670 }
671
672
673 // 0010 01An imm16...; mov imm16,An (imm16 is zero-extended)
674 4.0x2,01,2.AN0+8.IMM16A+8.IMM16B:S2c:::mov
675 "mov"
676 *mn10300
677 {
678 // OP_240000 ();
679 unsigned long value;
680
681 PC = cia;
682 value = FETCH16(IMM16A, IMM16B);
683 State.regs[REG_A0 + AN0] = value;
684 }
685
686
687 // 1111 1100 1101 11An imm32...; mov imm32,An
688 8.0xfc+4.0xd,11,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4m:::mov
689 "mov"
690 *mn10300
691 {
692 // OP_FCDC0000 ();
693 PC = cia;
694 State.regs[REG_A0 + AN0] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
695 }
696
697
698 // 1111 0000 0100 DnAm; movbu (Am),Dn
699 8.0xf0+4.0x4,2.DN1,2.AM0:D0:::movbu
700 "movbu"
701 *mn10300
702 {
703 // OP_F040 ();
704 PC = cia;
705 State.regs[REG_D0 + DN1]
706 = load_byte (State.regs[REG_A0 + AM0]);
707 }
708
709
710 // 1111 1000 0100 DnAm d8......; movbu (d8,Am),Dn (d8 is sign-extended)
711 8.0xf8+4.0x4,2.DN1,2.AM0+8.D8:D1f:::movbu
712 "movbu"
713 *mn10300
714 {
715 // OP_F84000 ();
716 PC = cia;
717 State.regs[REG_D0 + DN1]
718 = load_byte ((State.regs[REG_A0 + AM0] + EXTEND8 (D8)));
719 }
720
721
722 // 1111 1010 0100 DnAm d16.....; movbu (d16,Am),Dn (d16 is sign-extended.)
723 8.0xfa+4.0x4,2.DN1,2.AM0+8.D16A+8.D16B:D2:::movbu
724 "movbu"
725 *mn10300
726 {
727 // OP_FA400000 ();
728 PC = cia;
729 State.regs[REG_D0 + DN1]
730 = load_byte ((State.regs[REG_A0 + AM0]
731 + EXTEND16 (FETCH16(D16A, D16B))));
732 }
733
734
735 // 1111 1100 0100 DnAm d32.....; movbu (d32,Am),Dn
736 8.0xfc+4.0x4,2.DN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::movbu
737 "movbu"
738 *mn10300
739 {
740 // OP_FC400000 ();
741 PC = cia;
742 State.regs[REG_D0 + DN1]
743 = load_byte ((State.regs[REG_A0 + AM0]
744 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
745 }
746
747
748 // 1111 1000 1011 10Dn d8......; movbu (d8,SP),Dn (d8 is zero-extended)
749 8.0xf8+4.0xb,10,2.DN0+8.D8:D1a:::movbu
750 "movbu"
751 *mn10300
752 {
753 // OP_F8B800 ();
754 PC = cia;
755 State.regs[REG_D0 + DN0]
756 = load_byte ((State.regs[REG_SP] + (D8)));
757 }
758
759
760 // 1111 1010 1011 10Dn d16.....; movbu (d16,SP),Dn (d16 is zero-extended.)
761 8.0xfa+4.0xb,10,2.DN0+8.IMM16A+8.IMM16B:D2a:::movbu
762 "movbu"
763 *mn10300
764 {
765 // OP_FAB80000 ();
766 PC = cia;
767 State.regs[REG_D0 + DN0]
768 = load_byte ((State.regs[REG_SP]
769 + FETCH16(IMM16A, IMM16B)));
770 }
771
772
773 // 1111 1100 1011 10Dn d32.....; movbu (d32,SP),Dn
774 8.0xfc+4.0xb,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::movbu
775 "movbu"
776 *mn10300
777 {
778 // OP_FCB80000 ();
779 PC = cia;
780 State.regs[REG_D0 + DN0]
781 = load_byte (State.regs[REG_SP]
782 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
783 }
784
785
786 // 1111 0100 00Dn DiAm; movbu (Di,Am),Dn
787 8.0xf4+00,2.DN2,2.DI,2.AM0:D0a:::movbu
788 "movbu"
789 *mn10300
790 {
791 // OP_F400 ();
792 PC = cia;
793 State.regs[REG_D0 + DN2]
794 = load_byte ((State.regs[REG_A0 + AM0]
795 + State.regs[REG_D0 + DI]));
796 }
797
798
799 // 0011 01Dn abs16...; movbu (abs16),Dn (abs16 is zero-extended)
800 4.0x3,01,2.DN0+8.IMM16A+8.IMM16B:S2:::movbu
801 "movbu"
802 *mn10300
803 {
804 // OP_340000 ();
805 PC = cia;
806 State.regs[REG_D0 + DN0] = load_byte (FETCH16(IMM16A, IMM16B));
807 }
808
809
810 // 1111 1100 1010 10Dn abs32...; movbu (abs32),Dn
811 8.0xfc+4.0xa,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::movbu
812 "movbu"
813 *mn10300
814 {
815 // OP_FCA80000 ();
816 PC = cia;
817 State.regs[REG_D0 + DN0]
818 = load_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
819 }
820
821
822 // 1111 0000 0101 DmAn; movbu Dm,(An)
823 8.0xf0+4.0x5,2.DM1,2.AN0:D0b:::movbu
824 "movbu"
825 *mn10300
826 {
827 // OP_F050 ();
828 PC = cia;
829 store_byte (State.regs[REG_A0 + AN0], State.regs[REG_D0 + DM1]);
830 }
831
832
833 // 1111 1000 0101 DmAn d8......; movbu Dm,(d8,An) (d8 is sign-extended)
834 8.0xf8+4.0x5,2.DM1,2.AN0+8.D8:D1b:::movbu
835 "movbu"
836 *mn10300
837 {
838 // OP_F85000 ();
839 PC = cia;
840 store_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)),
841 State.regs[REG_D0 + DM1]);
842 }
843
844
845 // 1111 1010 0101 DmAn d16.....; movbu Dm,(d16,An) (d16 is sign-extended.)
846 8.0xfa+4.0x5,2.DM1,2.AN0+8.D16A+8.D16B:D2b:::movbu
847 "movbu"
848 *mn10300
849 {
850 // OP_FA500000 ();
851 PC = cia;
852 store_byte ((State.regs[REG_A0 + AN0] + EXTEND16 (FETCH16(D16A, D16B))),
853 State.regs[REG_D0 + DM1]);
854 }
855
856
857 // 1111 1100 0101 DmAn d32.....; movbu Dm,(d32,An)
858 8.0xfc+4.0x5,2.DM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4c:::movbu
859 "movbu"
860 *mn10300
861 {
862 // OP_FC500000 ();
863 PC = cia;
864 store_byte ((State.regs[REG_A0 + AN0]
865 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)),
866 State.regs[REG_D0 + DM1]);
867 }
868
869
870 // 1111 1000 1001 Dm10 d8......; movbu Dm,(d8,SP) (d8 is zero-extended)
871 8.0xf8+4.0x9,2.DM1,10+8.D8:D1c:::movbu
872 "movbu"
873 *mn10300
874 {
875 // OP_F89200 ();
876 PC = cia;
877 store_byte (State.regs[REG_SP] + (D8), State.regs[REG_D0 + DM1]);
878 }
879
880
881 // 1111 1010 1001 Dm10 d16.....; movbu Dm,(d16,SP) (d16 is zero-extended.)
882 8.0xfa+4.0x9,2.DM1,10+8.IMM16A+8.IMM16B:D2c:::movbu
883 "movbu"
884 *mn10300
885 {
886 // OP_FA920000 ();
887 PC = cia;
888 store_byte (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B),
889 State.regs[REG_D0 + DM1]);
890 }
891
892
893 // 1111 1100 1001 Dm10 d32.....; movbu Dm,(d32,SP)
894 8.0xfc+4.0x9,2.DM1,10+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4d:::movbu
895 "movbu"
896 *mn10300
897 {
898 // OP_FC920000 ();
899 PC = cia;
900 store_byte (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
901 State.regs[REG_D0 + DM1]);
902 }
903
904
905 // 1111 0100 01Dm DiAn; movbu Dm,(Di,An)
906 8.0xf4+01,2.DM2,2.DI,2.AN0:D0c:::movbu
907 "movbu"
908 *mn10300
909 {
910 // OP_F440 ();
911 PC = cia;
912 store_byte ((State.regs[REG_A0 + AN0] + State.regs[REG_D0 + DI]),
913 State.regs[REG_D0 + DM2]);
914 }
915
916
917 // 0000 Dm10 abs16...; movbu Dm,(abs16) (abs16 is zero-extended)
918 4.0x0,2.DM1,10+8.IMM16A+8.IMM16B:S2a:::movbu
919 "movbu"
920 *mn10300
921 {
922 // OP_20000 ();
923 PC = cia;
924 store_byte (FETCH16(IMM16A, IMM16B),
925 State.regs[REG_D0 + DM1]);
926 }
927
928
929 // 1111 1100 1000 Dm10 abs32...; movbu Dm,(abs32)
930 8.0xfc+4.0x8,2.DM1,10+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4e:::movbu
931 "movbu"
932 *mn10300
933 {
934 // OP_FC820000 ();
935 PC = cia;
936 store_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
937 State.regs[REG_D0 + DM1]);
938 }
939
940
941 // 1111 0000 0110 DnAm; movhu (Am),Dn
942 8.0xf0+4.0x6,2.DN1,2.AM0:D0:::movhu
943 "movhu"
944 *mn10300
945 {
946 // OP_F060 ();
947 PC = cia;
948 State.regs[REG_D0 + DN1]
949 = load_half (State.regs[REG_A0 + AM0]);
950 }
951
952
953 // 1111 1000 0110 DnAm d8......; movhu (d8,Am),Dn (d8 is sign-extended)
954 8.0xf8+4.0x6,2.DN1,2.AM0+8.D8:D1d:::movhu
955 "movhu"
956 *mn10300
957 {
958 // OP_F86000 ();
959 PC = cia;
960 State.regs[REG_D0 + DN1]
961 = load_half ((State.regs[REG_A0 + AM0] + EXTEND8 (D8)));
962 }
963
964
965 // 1111 1010 0110 DnAm d16.....; movhu (d16,Am),Dn (d16 is sign-extended.)
966 8.0xfa+4.0x6,2.DN1,2.AM0+8.D16A+8.D16B:D2:::movhu
967 "movhu"
968 *mn10300
969 {
970 // OP_FA600000 ();
971 PC = cia;
972 State.regs[REG_D0 + DN1]
973 = load_half ((State.regs[REG_A0 + AM0]
974 + EXTEND16 (FETCH16(D16A, D16B))));
975 }
976
977
978 // 1111 1100 0110 DnAm d32.....; movhu (d32,Am),Dn
979 8.0xfc+4.0x6,2.DN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::movhu
980 "movhu"
981 *mn10300
982 {
983 // OP_FC600000 ();
984 PC = cia;
985 State.regs[REG_D0 + DN1]
986 = load_half ((State.regs[REG_A0 + AM0]
987 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
988 }
989
990
991 // 1111 1000 1011 11Dn d8.....; movhu (d8,SP),Dn (d8 is zero-extended)
992 8.0xf8+4.0xb,11,2.DN0+8.D8:D1a:::movhu
993 "movhu"
994 *mn10300
995 {
996 // OP_F8BC00 ();
997 PC = cia;
998 State.regs[REG_D0 + DN0]
999 = load_half ((State.regs[REG_SP] + (D8)));
1000 }
1001
1002
1003 // 1111 1010 1011 11Dn d16.....; movhu (d16,SP),Dn (d16 is zero-extended.)
1004 8.0xfa+4.0xb,11,2.DN0+8.IMM16A+8.IMM16B:D2a:::movhu
1005 "movhu"
1006 *mn10300
1007 {
1008 // OP_FABC0000 ();
1009 PC = cia;
1010 State.regs[REG_D0 + DN0]
1011 = load_half ((State.regs[REG_SP] + FETCH16(IMM16A, IMM16B)));
1012 }
1013
1014
1015 // 1111 1100 1011 11Dn d32.....; movhu (d32,SP),Dn
1016 8.0xfc+4.0xb,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::movhu
1017 "movhu"
1018 *mn10300
1019 {
1020 // OP_FCBC0000 ();
1021 PC = cia;
1022 State.regs[REG_D0 + DN0]
1023 = load_half (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
1024 }
1025
1026
1027 // 1111 0100 10Dn DiAm; movhu (Di,Am),Dn
1028 8.0xf4+10,2.DN2,2.DI,2.AM0:D0a:::movhu
1029 "movhu"
1030 *mn10300
1031 {
1032 // OP_F480 ();
1033 PC = cia;
1034 State.regs[REG_D0 + DN2]
1035 = load_half ((State.regs[REG_A0 + AM0] + State.regs[REG_D0 + DI]));
1036 }
1037
1038
1039 // 0011 10Dn abs16...; movhu (abs16),Dn (abs16 is zero-extended)
1040 4.0x3,10,2.DN0+8.IMM16A+8.IMM16B:S2:::movhu
1041 "movhu"
1042 *mn10300
1043 {
1044 // OP_380000 ();
1045 PC = cia;
1046 State.regs[REG_D0 + DN0] = load_half (FETCH16(IMM16A, IMM16B));
1047 }
1048
1049
1050 // 1111 1100 1010 11Dn abs32...; movhu (abs32),Dn
1051 8.0xfc+4.0xa,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::movhu
1052 "movhu"
1053 *mn10300
1054 {
1055 // OP_FCAC0000 ();
1056 PC = cia;
1057 State.regs[REG_D0 + DN0]
1058 = load_half (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
1059 }
1060
1061
1062 // 1111 0000 0111 DmAn; movhu Dm,(An)
1063 8.0xf0+4.0x7,2.DM1,2.AN0:D0b:::movhu
1064 "movhu"
1065 *mn10300
1066 {
1067 // OP_F070 ();
1068 PC = cia;
1069 store_half (State.regs[REG_A0 + AN0],
1070 State.regs[REG_D0 + DM1]);
1071 }
1072
1073
1074 // 1111 1000 0111 DmAn d8......; movhu Dm,(d8,An) (d8 is sign-extended)
1075 8.0xf8+4.0x7,2.DM1,2.AN0+8.D8:D1b:::movhu
1076 "movhu"
1077 *mn10300
1078 {
1079 // OP_F87000 ();
1080 PC = cia;
1081 store_half ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)),
1082 State.regs[REG_D0 + DM1]);
1083 }
1084
1085
1086 // 1111 1010 0111 DnAm d16.....; movhu Dm,(d16,An) (d16 is sign-extended.)
1087 8.0xfa+4.0x7,2.DM1,2.AN0+8.D16A+8.D16B:D2b:::movhu
1088 "movhu"
1089 *mn10300
1090 {
1091 // OP_FA700000 ();
1092 PC = cia;
1093 store_half ((State.regs[REG_A0 + AN0] + EXTEND16 (FETCH16(D16A, D16B))),
1094 State.regs[REG_D0 + DM1]);
1095 }
1096
1097
1098 // 1111 1100 0111 DmAn d32.....; movhu Dm,(d32,An)
1099 8.0xfc+4.0x7,2.DM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4c:::movhu
1100 "movhu"
1101 *mn10300
1102 {
1103 // OP_FC700000 ();
1104 PC = cia;
1105 store_half ((State.regs[REG_A0 + AN0]
1106 + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)),
1107 State.regs[REG_D0 + DM1]);
1108 }
1109
1110
1111 // 1111 1000 1001 Dm11 d8....; movhu Dm,(d8,SP) (d8 is zero-extended)
1112 8.0xf8+4.0x9,2.DM1,11+8.D8:D1c:::movhu
1113 "movhu"
1114 *mn10300
1115 {
1116 // OP_F89300 ();
1117 PC = cia;
1118 store_half (State.regs[REG_SP] + (D8),
1119 State.regs[REG_D0 + DM1]);
1120 }
1121
1122
1123 // 1111 1010 1001 Dm11 d16.....; movhu Dm,(d16,SP) (d16 is zero-extended.)
1124 8.0xfa+4.0x9,2.DM1,11+8.IMM16A+8.IMM16B:D2c:::movhu
1125 "movhu"
1126 *mn10300
1127 {
1128 // OP_FA930000 ();
1129 PC = cia;
1130 store_half (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B),
1131 State.regs[REG_D0 + DM1]);
1132 }
1133
1134
1135 // 1111 1100 1001 Dm11 d32.....; movhu Dm,(d32,SP)
1136 8.0xfc+4.0x9,2.DM1,11+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4d:::movhu
1137 "movhu"
1138 *mn10300
1139 {
1140 // OP_FC930000 ();
1141 PC = cia;
1142 store_half (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
1143 State.regs[REG_D0 + DM1]);
1144 }
1145
1146
1147 // 1111 0100 11Dm DiAn; movhu Dm,(Di,An)
1148 8.0xf4+11,2.DM2,2.DI,2.AN0:D0c:::movhu
1149 "movhu"
1150 *mn10300
1151 {
1152 // OP_F4C0 ();
1153 PC = cia;
1154 store_half ((State.regs[REG_A0 + AN0] + State.regs[REG_D0 + DI]),
1155 State.regs[REG_D0 + DM2]);
1156 }
1157
1158
1159 // 0000 Dm11 abs16...; movhu Dm,(abs16) (abs16 is zero-extended)
1160 4.0x0,2.DM1,11+8.IMM16A+8.IMM16B:S2a:::movhu
1161 "movhu"
1162 *mn10300
1163 {
1164 // OP_30000 ();
1165 PC = cia;
1166 store_half (FETCH16(IMM16A, IMM16B), State.regs[REG_D0 + DM1]);
1167 }
1168
1169
1170 // 1111 1100 1000 Dm11 abs32...; movhu Dm,(abs32)
1171 8.0xfc+4.0x8,2.DM1,11+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4e:::movhu
1172 "movhu"
1173 *mn10300
1174 {
1175 // OP_FC830000 ();
1176 PC = cia;
1177 store_half (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
1178 State.regs[REG_D0 + DM1]);
1179 }
1180
1181
1182 // 1111 0010 1101 00Dn; ext Dn
1183 8.0xf2+4.0xd,00,2.DN0:D0:::ext
1184 "ext"
1185 *mn10300
1186 {
1187 // OP_F2D0 ();
1188 PC = cia;
1189 if (State.regs[REG_D0 + DN0] & 0x80000000)
1190 State.regs[REG_MDR] = -1;
1191 else
1192 State.regs[REG_MDR] = 0;
1193 }
1194
1195
1196 // 0001 00Dn; extb Dn
1197 4.0x1,00,2.DN0:S0:::extb
1198 "extb"
1199 *mn10300
1200 {
1201 // OP_10 ();
1202 PC = cia;
1203 State.regs[REG_D0 + DN0] = EXTEND8 (State.regs[REG_D0 + DN0]);
1204 }
1205
1206
1207 // 0001 01Dn; extbu Dn
1208 4.0x1,01,2.DN0:S0:::extbu
1209 "extbu"
1210 *mn10300
1211 {
1212 // OP_14 ();
1213 PC = cia;
1214 State.regs[REG_D0 + DN0] &= 0xff;
1215 }
1216
1217
1218 // 0001 10Dn; exth Dn
1219 4.0x1,10,2.DN0:S0:::exth
1220 "exth"
1221 *mn10300
1222 {
1223 // OP_18 ();
1224 PC = cia;
1225 State.regs[REG_D0 + DN0] = EXTEND16 (State.regs[REG_D0 + DN0]);
1226 }
1227
1228
1229 // 0001 11Dn; exthu Dn
1230 4.0x1,11,2.DN0:S0:::exthu
1231 "exthu"
1232 *mn10300
1233 {
1234 // OP_1C ();
1235 PC = cia;
1236 State.regs[REG_D0 + DN0] &= 0xffff;
1237 }
1238
1239
1240 // 1100 1110 regs....; movm (SP),regs
1241 8.0xce+8.REGS:S1:::movm
1242 "movm"
1243 *mn10300
1244 {
1245 // OP_CE00 ();
1246 unsigned long sp = State.regs[REG_SP];
1247 unsigned long mask;
1248
1249 PC = cia;
1250 mask = REGS;
1251
1252 if (mask & 0x8)
1253 {
1254 sp += 4;
1255 State.regs[REG_LAR] = load_word (sp);
1256 sp += 4;
1257 State.regs[REG_LIR] = load_word (sp);
1258 sp += 4;
1259 State.regs[REG_MDR] = load_word (sp);
1260 sp += 4;
1261 State.regs[REG_A0 + 1] = load_word (sp);
1262 sp += 4;
1263 State.regs[REG_A0] = load_word (sp);
1264 sp += 4;
1265 State.regs[REG_D0 + 1] = load_word (sp);
1266 sp += 4;
1267 State.regs[REG_D0] = load_word (sp);
1268 sp += 4;
1269 }
1270
1271 if (mask & 0x10)
1272 {
1273 State.regs[REG_A0 + 3] = load_word (sp);
1274 sp += 4;
1275 }
1276
1277 if (mask & 0x20)
1278 {
1279 State.regs[REG_A0 + 2] = load_word (sp);
1280 sp += 4;
1281 }
1282
1283 if (mask & 0x40)
1284 {
1285 State.regs[REG_D0 + 3] = load_word (sp);
1286 sp += 4;
1287 }
1288
1289 if (mask & 0x80)
1290 {
1291 State.regs[REG_D0 + 2] = load_word (sp);
1292 sp += 4;
1293 }
1294
1295 /* And make sure to update the stack pointer. */
1296 State.regs[REG_SP] = sp;
1297 }
1298
1299
1300 // 1100 1111 regs....; movm regs,(SP)
1301 8.0xcf+8.REGS:S1a:::movm
1302 "movm"
1303 *mn10300
1304 {
1305 // OP_CF00 ();
1306 unsigned long sp = State.regs[REG_SP];
1307 unsigned long mask;
1308
1309 PC = cia;
1310 mask = REGS;
1311
1312 if (mask & 0x80)
1313 {
1314 sp -= 4;
1315 store_word (sp, State.regs[REG_D0 + 2]);
1316 }
1317
1318 if (mask & 0x40)
1319 {
1320 sp -= 4;
1321 store_word (sp, State.regs[REG_D0 + 3]);
1322 }
1323
1324 if (mask & 0x20)
1325 {
1326 sp -= 4;
1327 store_word (sp, State.regs[REG_A0 + 2]);
1328 }
1329
1330 if (mask & 0x10)
1331 {
1332 sp -= 4;
1333 store_word (sp, State.regs[REG_A0 + 3]);
1334 }
1335
1336 if (mask & 0x8)
1337 {
1338 sp -= 4;
1339 store_word (sp, State.regs[REG_D0]);
1340 sp -= 4;
1341 store_word (sp, State.regs[REG_D0 + 1]);
1342 sp -= 4;
1343 store_word (sp, State.regs[REG_A0]);
1344 sp -= 4;
1345 store_word (sp, State.regs[REG_A0 + 1]);
1346 sp -= 4;
1347 store_word (sp, State.regs[REG_MDR]);
1348 sp -= 4;
1349 store_word (sp, State.regs[REG_LIR]);
1350 sp -= 4;
1351 store_word (sp, State.regs[REG_LAR]);
1352 sp -= 4;
1353 }
1354
1355 /* And make sure to update the stack pointer. */
1356 State.regs[REG_SP] = sp;
1357 }
1358
1359
1360 // 0000 Dn00; clr Dn
1361 4.0x0,2.DN1,00:S0:::clr
1362 "clr"
1363 *mn10300
1364 {
1365 // OP_0 ();
1366 PC = cia;
1367 State.regs[REG_D0 + DN1] = 0;
1368
1369 PSW |= PSW_Z;
1370 PSW &= ~(PSW_V | PSW_C | PSW_N);
1371 }
1372
1373
1374 // 1110 DmDn; add Dm,Dn
1375 4.0xe,2.DM1,2.DN0:S0:::add
1376 "add"
1377 *mn10300
1378 {
1379 // OP_E0 ();
1380 PC = cia;
1381 genericAdd(State.regs[REG_D0 + DM1], REG_D0 + DN0);
1382 }
1383
1384 // 1111 0001 0110 DmAn; add Dm,An
1385 8.0xf1+4.0x6,2.DM1,2.AN0:D0:::add
1386 "add"
1387 *mn10300
1388 {
1389 // OP_F160 ();
1390 int z, c, n, v;
1391 unsigned long reg1, reg2, value;
1392
1393 PC = cia;
1394 genericAdd(State.regs[REG_D0 + DM1], REG_A0 + AN0);
1395 }
1396
1397
1398 // 1111 0001 0101 AmDn; add Am,Dn
1399 8.0xf1+4.0x5,2.AM1,2.DN0:D0a:::add
1400 "add"
1401 *mn10300
1402 {
1403 // OP_F150 ();
1404 PC = cia;
1405 genericAdd(State.regs[REG_A0 + AM1], REG_D0 + DN0);
1406 }
1407
1408
1409 // 1111 0001 0111 AmAn; add Am,An
1410 8.0xf1+4.0x7,2.AM1,2.AN0:D0b:::add
1411 "add"
1412 *mn10300
1413 {
1414 // OP_F170 ();
1415 PC = cia;
1416 genericAdd(State.regs[REG_A0 + AM1], REG_A0 + AN0);
1417 }
1418
1419
1420 // 0010 10Dn imm8....; add imm8,Dn (imm8 is sign-extended)
1421 4.0x2,10,2.DN0+8.IMM8:S1:::add
1422 "add"
1423 *mn10300
1424 {
1425 // OP_2800 ();
1426 PC = cia;
1427 genericAdd(EXTEND8(IMM8), REG_D0 + DN0);
1428 }
1429
1430
1431 // 1111 1010 1100 00Dn imm16...; add imm16,Dn
1432 8.0xfa+4.0xc,00,2.DN0+8.IMM16A+8.IMM16B:D2:::add
1433 "add"
1434 *mn10300
1435 {
1436 // OP_FAC00000 ();
1437 PC = cia;
1438 genericAdd(EXTEND16(FETCH16(IMM16A, IMM16B)), REG_D0 + DN0);
1439 }
1440
1441
1442 // 1111 1100 1100 00Dn imm32...; add imm32,Dn
1443 8.0xfc+4.0xc,00,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::add
1444 "add"
1445 *mn10300
1446 {
1447 // OP_FCC00000 ();
1448 PC = cia;
1449 genericAdd(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_D0 + DN0);
1450 }
1451
1452
1453 // 0010 00An imm8....; add imm8,An (imm8 is sign-extended)
1454 4.0x2,00,2.AN0+8.IMM8:S1a:::add
1455 "add"
1456 *mn10300
1457 {
1458 // OP_2000 ();
1459 PC = cia;
1460 genericAdd(EXTEND8(IMM8), REG_A0 + AN0);
1461 }
1462
1463
1464 // 1111 1010 1101 00An imm16...; add imm16,An (imm16 is sign-extended.)
1465 8.0xfa+4.0xd,00,2.AN0+8.IMM16A+8.IMM16B:D2a:::add
1466 "add"
1467 *mn10300
1468 {
1469 // OP_FAD00000 ();
1470 PC = cia;
1471 genericAdd(EXTEND16(FETCH16(IMM16A, IMM16B)), REG_A0 + AN0);
1472 }
1473
1474
1475 // 1111 1100 1101 00An imm32...; add imm32,An
1476 8.0xfc+4.0xd,00,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::add
1477 "add"
1478 *mn10300
1479 {
1480 // OP_FCD00000 ();
1481 PC = cia;
1482 genericAdd(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_A0 + AN0);
1483 }
1484
1485
1486 // 1111 1000 1111 1110 imm8....; add imm8,SP (imm8 is sign-extended.)
1487 8.0xf8+8.0xfe+8.IMM8:D1:::add
1488 "add"
1489 *mn10300
1490 {
1491 // OP_F8FE00 ();
1492 unsigned long imm;
1493
1494 // Note: no PSW changes.
1495 PC = cia;
1496 imm = EXTEND8 (IMM8);
1497 State.regs[REG_SP] += imm;
1498 }
1499
1500
1501 // 1111 1010 1111 1110 imm16...; add imm16,SP (imm16 is sign-extended.)
1502 8.0xfa+8.0xfe+8.IMM16A+8.IMM16B:D2b:::add
1503 "add"
1504 *mn10300
1505 {
1506 // OP_FAFE0000 ();
1507 unsigned long imm;
1508
1509 // Note: no PSW changes.
1510 PC = cia;
1511 imm = EXTEND16 (FETCH16(IMM16A, IMM16B));
1512 State.regs[REG_SP] += imm;
1513 }
1514
1515
1516 // 1111 1100 1111 1110 imm32...; add imm32,SP
1517 8.0xfc+8.0xfe+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::add
1518 "add"
1519 *mn10300
1520 {
1521 // OP_FCFE0000 ();
1522 unsigned long imm;
1523
1524 // Note: no PSW changes.
1525 PC = cia;
1526 imm = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
1527 State.regs[REG_SP] += imm;
1528 }
1529
1530
1531 // 1111 0001 0100 DmDn; addc Dm,Dn
1532 8.0xf1+4.0x4,2.DM1,2.DN0:D0:::addc
1533 "addc"
1534 *mn10300
1535 {
1536 // OP_F140 ();
1537 int z, c, n, v;
1538 unsigned long reg1, reg2, sum;
1539
1540 PC = cia;
1541 reg1 = State.regs[REG_D0 + DM1];
1542 reg2 = State.regs[REG_D0 + DN0];
1543 sum = reg1 + reg2 + ((PSW & PSW_C) != 0);
1544 State.regs[REG_D0 + DN0] = sum;
1545
1546 z = (sum == 0);
1547 n = (sum & 0x80000000);
1548 c = (sum < reg1) || (sum < reg2);
1549 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
1550 && (reg2 & 0x80000000) != (sum & 0x80000000));
1551
1552 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1553 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1554 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1555 }
1556
1557
1558 // 1111 0001 0000 DmDn; sub Dm,Dn
1559 8.0xf1+4.0x0,2.DM1,2.DN0:D0:::sub
1560 "sub"
1561 *mn10300
1562 {
1563 // OP_F100 ();
1564 PC = cia;
1565 genericSub(State.regs[REG_D0 + DM1], REG_D0 + DN0);
1566 }
1567
1568 // 1111 0001 0010 DmAn; sub DmAn
1569 8.0xf1+4.0x2,2.DM1,2.AN0:D0a:::sub
1570 "sub"
1571 *mn10300
1572 {
1573 // OP_F120 ();
1574 PC = cia;
1575 genericSub(State.regs[REG_D0 + DM1], REG_A0 + AN0);
1576 }
1577
1578
1579 // 1111 0001 0001 AmDn; sub AmDn
1580 8.0xf1+4.0x1,2.AM1,2.DN0:D0b:::sub
1581 "sub"
1582 *mn10300
1583 {
1584 // OP_F110 ();
1585 PC = cia;
1586 genericSub(State.regs[REG_A0 + AM1], REG_D0 + DN0);
1587 }
1588
1589
1590 // 1111 0001 0011 AmAn; sub Am,An
1591 8.0xf1+4.0x3,2.AM1,2.AN0:D0c:::sub
1592 "sub"
1593 *mn10300
1594 {
1595 // OP_F130 ();
1596 PC = cia;
1597 genericSub(State.regs[REG_A0 + AM1], REG_A0 + AN0);
1598 }
1599
1600
1601 // 1111 1100 1100 01Dn imm32...; sub imm32,Dn
1602 8.0xfc+4.0xc,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::sub
1603 "sub"
1604 *mn10300
1605 {
1606 // OP_FCC40000 ();
1607 PC = cia;
1608 genericSub(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_D0 + DN0);
1609 }
1610
1611
1612 // 1111 1100 1101 01An imm32...; sub imm32,An
1613 8.0xfc+4.0xd,01,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::sub
1614 "sub"
1615 *mn10300
1616 {
1617 // OP_FCD40000 ();
1618 PC = cia;
1619 genericSub(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_A0 + AN0);
1620 }
1621
1622
1623 // 1111 0001 1000 DmDn; subc Dm,Dn
1624 8.0xf1+4.0x8,2.DM1,2.DN0:D0:::subc
1625 "subc"
1626 *mn10300
1627 {
1628 // OP_F180 ();
1629 int z, c, n, v;
1630 unsigned long reg1, reg2, difference;
1631
1632 PC = cia;
1633 reg1 = State.regs[REG_D0 + DM1];
1634 reg2 = State.regs[REG_D0 + DN0];
1635 difference = reg2 - reg1 - ((PSW & PSW_C) != 0);
1636 State.regs[REG_D0 + DN0] = difference;
1637
1638 z = (difference == 0);
1639 n = (difference & 0x80000000);
1640 c = (reg1 > reg2);
1641 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1642 && (reg2 & 0x80000000) != (difference & 0x80000000));
1643
1644 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1645 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1646 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1647 }
1648
1649
1650 // 1111 0010 0100 DmDn; mul Dm,Dn
1651 8.0xf2+4.0x4,2.DM1,2.DN0:D0:::mul
1652 "mul"
1653 *mn10300
1654 {
1655 // OP_F240 ();
1656 unsigned long long temp;
1657 int n, z;
1658
1659 PC = cia;
1660 temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
1661 * (signed64)(signed32)State.regs[REG_D0 + DM1]);
1662 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
1663 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
1664 z = (State.regs[REG_D0 + DN0] == 0);
1665 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
1666 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1667 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1668 }
1669
1670
1671 // 1111 0010 0101 DmDn; mulu Dm,Dn
1672 8.0xf2+4.0x5,2.DM1,2.DN0:D0:::mulu
1673 "mulu"
1674 *mn10300
1675 {
1676 // OP_F250 ();
1677 unsigned long long temp;
1678 int n, z;
1679
1680 PC = cia;
1681 temp = ((unsigned64)State.regs[REG_D0 + DN0]
1682 * (unsigned64)State.regs[REG_D0 + DM1]);
1683 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
1684 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
1685 z = (State.regs[REG_D0 + DN0] == 0);
1686 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
1687 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1688 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1689 }
1690
1691
1692 // 1111 0010 0110 DmDn; div Dm,Dn
1693 8.0xf2+4.0x6,2.DM1,2.DN0:D0:::div
1694 "div"
1695 *mn10300
1696 {
1697 // OP_F260 ();
1698 long long temp;
1699 int n, z;
1700
1701 PC = cia;
1702 temp = State.regs[REG_MDR];
1703 temp <<= 32;
1704 temp |= State.regs[REG_D0 + DN0];
1705 State.regs[REG_MDR] = temp % (long)State.regs[REG_D0 + DM1];
1706 temp /= (long)State.regs[REG_D0 + DM1];
1707 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
1708 z = (State.regs[REG_D0 + DN0] == 0);
1709 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
1710 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1711 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1712 }
1713
1714
1715 // 1111 0010 0111 DmDn; divu Dm,Dn
1716 8.0xf2+4.0x7,2.DM1,2.DN0:D0:::divu
1717 "divu"
1718 *mn10300
1719 {
1720 // OP_F270 ();
1721 unsigned long long temp;
1722 int n, z;
1723
1724 PC = cia;
1725 temp = State.regs[REG_MDR];
1726 temp <<= 32;
1727 temp |= State.regs[REG_D0 + DN0];
1728 State.regs[REG_MDR] = temp % State.regs[REG_D0 + DM1];
1729 temp /= State.regs[REG_D0 + DM1];
1730 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
1731 z = (State.regs[REG_D0 + DN0] == 0);
1732 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
1733 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1734 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1735 }
1736
1737
1738 // 0100 Dn00; inc Dn
1739 4.0x4,2.DN1,00:S0:::inc
1740 "inc"
1741 *mn10300
1742 {
1743 // OP_40 ();
1744 unsigned int imm;
1745
1746 PC = cia;
1747 imm = 1;
1748 genericAdd(imm, REG_D0 + DN1);
1749 }
1750
1751
1752 // 0100 An01
1753 4.0x4,2.AN1,01:S0a:::inc
1754 "inc"
1755 *mn10300
1756 {
1757 // OP_41 ();
1758 PC = cia;
1759 State.regs[REG_A0 + AN1] += 1;
1760 }
1761
1762
1763 // 0101 00An; inc4 An
1764 4.0x5,00,2.AN0:S0:::inc4
1765 "inc4"
1766 *mn10300
1767 {
1768 // OP_50 ();
1769 PC = cia;
1770 State.regs[REG_A0 + AN0] += 4;
1771 }
1772
1773
1774 // 1010 DnDn imm8....; cmp imm8,Dn (imm8 is sign-extended.)
1775 // 1010 DmDn; cmp Dm,Dn (Dm != Dn, see above when Dm == Dn)
1776 4.0xa,2.DM1,2.DN0:S0:::cmp
1777 "cmp"
1778 *mn10300
1779 {
1780 PC = cia;
1781 if ( DM1 == DN0 )
1782 {
1783 signed32 immed = EXTEND8 (IMEM8_IMMED (cia, 1));
1784 nia = cia + 2;
1785 // OP_A000 ();
1786 genericCmp(immed, State.regs[REG_D0 + DN0]);
1787 }
1788 else
1789 {
1790 // OP_A0 ();
1791 genericCmp(State.regs[REG_D0 + DM1], State.regs[REG_D0 + DN0]);
1792 }
1793 }
1794
1795
1796 // 1111 0001 1010 DmAn; cmp Dm,An
1797 8.0xf1+4.0xa,2.DM1,2.AN0:D0:::cmp
1798 "cmp"
1799 *mn10300
1800 {
1801 // OP_F1A0 ();
1802 PC = cia;
1803 genericCmp(State.regs[REG_D0 + DM1], State.regs[REG_A0 + AN0]);
1804 }
1805
1806
1807 // 1111 0001 1001 AmDn; cmp Am,Dn
1808 8.0xf1+4.0x9,2.AM1,2.DN0:D0a:::cmp
1809 "cmp"
1810 *mn10300
1811 {
1812 // OP_F190 ();
1813 PC = cia;
1814 genericCmp(State.regs[REG_A0 + AM1], State.regs[REG_D0 + DN0]);
1815 }
1816
1817
1818 // 1011 AnAn imm8....; cmp imm8,An (imm8 is zero-extended.)
1819 // 1011 AmAn; cmp Am,An (Dm != Dn, see above when Dm == Dn)
1820 4.0xb,2.AM1,2.AN0:S0a:::cmp
1821 "cmp"
1822 *mn10300
1823 {
1824 PC = cia;
1825 if ( AM1 == AN0 )
1826 {
1827 // op_B000 ();
1828 genericCmp(EXTEND8 (IMEM8_IMMED (cia, 1)),
1829 State.regs[REG_A0 + AN0]);
1830 nia = cia + 2;
1831 }
1832 else
1833 {
1834 // OP_B0 ();
1835 genericCmp(State.regs[REG_A0 + AM1], State.regs[REG_A0 + AN0]);
1836 }
1837 }
1838
1839
1840 // 1111 1010 1100 10Dn imm16...; cmp imm16,Dn (imm16 is sign-extended.)
1841 8.0xfa+4.0xc,10,2.DN0+8.IMM16A+8.IMM16B:D2:::cmp
1842 "cmp"
1843 *mn10300
1844 {
1845 // OP_FAC80000 ();
1846 PC = cia;
1847 genericCmp(EXTEND16(FETCH16(IMM16A, IMM16B)),
1848 State.regs[REG_D0 + DN0]);
1849 }
1850
1851
1852 // 1111 1100 1100 10Dn imm32...; cmp imm32,Dn
1853 8.0xfc+4.0xc,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::cmp
1854 "cmp"
1855 *mn10300
1856 {
1857 // OP_FCC80000 ();
1858 PC = cia;
1859 genericCmp(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
1860 State.regs[REG_D0 + DN0]);
1861 }
1862
1863
1864 // 1111 1010 1101 10An imm16...; cmp imm16,An (imm16 is zero-extended.)
1865 8.0xfa+4.0xd,10,2.AN0+8.IMM16A+8.IMM16B:D2a:::cmp
1866 "cmp"
1867 *mn10300
1868 {
1869 // OP_FAD80000 ();
1870 PC = cia;
1871 genericCmp(FETCH16(IMM16A, IMM16B),
1872 State.regs[REG_A0 + AN0]);
1873 }
1874
1875
1876 // 1111 1100 1101 10An imm32...; cmp imm32,An
1877 8.0xfc+4.0xd,10,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::cmp
1878 "cmp"
1879 *mn10300
1880 {
1881 // OP_FCD80000 ();
1882 PC = cia;
1883 genericCmp(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
1884 State.regs[REG_A0 + AN0]);
1885 }
1886
1887
1888 // 1111 0010 0000 DmDn; and Dm,Dn
1889 8.0xf2+4.0x0,2.DM1,2.DN0:D0:::and
1890 "and"
1891 *mn10300
1892 {
1893 // OP_F200 ();
1894 int n, z;
1895
1896 PC = cia;
1897 State.regs[REG_D0 + DN0] &= State.regs[REG_D0 + DM1];
1898 z = (State.regs[REG_D0 + DN0] == 0);
1899 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
1900 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1901 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1902 }
1903
1904
1905 // 1111 1000 1110 00Dn imm8....; and imm8,Dn (imm8 is zero-extended.)
1906 8.0xf8+4.0xe,00,2.DN0+8.IMM8:D1:::and
1907 "and"
1908 *mn10300
1909 {
1910 // OP_F8E000 ();
1911 int n, z;
1912
1913 PC = cia;
1914 State.regs[REG_D0 + DN0] &= IMM8;
1915 z = (State.regs[REG_D0 + DN0] == 0);
1916 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
1917 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1918 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1919 }
1920
1921
1922 // 1111 1010 1110 00Dn imm16...; and imm16,Dn (imm16 is zero-extended.)
1923 8.0xfa+4.0xe,00,2.DN0+8.IMM16A+8.IMM16B:D2:::and
1924 "and"
1925 *mn10300
1926 {
1927 // OP_FAE00000 ();
1928 int n, z;
1929
1930 PC = cia;
1931 State.regs[REG_D0 + DN0] &= FETCH16(IMM16A, IMM16B);
1932 z = (State.regs[REG_D0 + DN0] == 0);
1933 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
1934 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1935 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1936 }
1937
1938
1939 // 1111 1100 1110 00Dn imm32...; and imm32,Dn
1940 8.0xfc+4.0xe,00,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::and
1941 "and"
1942 *mn10300
1943 {
1944 // OP_FCE00000 ();
1945 int n, z;
1946
1947 PC = cia;
1948 State.regs[REG_D0 + DN0]
1949 &= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
1950 z = (State.regs[REG_D0 + DN0] == 0);
1951 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
1952 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1953 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1954 }
1955
1956
1957 // 1111 1010 1111 1100 imm16...; and imm16,PSW (imm16 is zero-extended.)
1958 8.0xfa+8.0xfc+8.IMM16A+8.IMM16B:D2a:::and
1959 "and"
1960 *mn10300
1961 {
1962 // OP_FAFC0000 ();
1963 PC = cia;
1964 PSW &= FETCH16(IMM16A, IMM16B);
1965 }
1966
1967
1968
1969 // 1111 0010 0001 DmDn; or DmDn
1970 8.0xf2+4.0x1,2.DM1,2.DN0:D0:::or
1971 "or"
1972 *mn10300
1973 {
1974 // OP_F210 ();
1975 PC = cia;
1976 genericOr(State.regs[REG_D0 + DM1], REG_D0 + DN0);
1977 }
1978
1979
1980 // 1111 1000 1110 01Dn imm8....; or imm8,Dn (imm8 is zero-extended.)n
1981 8.0xf8+4.0xe,01,2.DN0+8.IMM8:D1:::or
1982 "or"
1983 *mn10300
1984 {
1985 // OP_F8E400 ();
1986 PC = cia;
1987 genericOr(IMM8, REG_D0 + DN0);
1988 }
1989
1990
1991 // 1111 1010 1110 01Dn imm16...; or imm16,DN (imm16 is zero-extended.)
1992 8.0xfa+4.0xe,01,2.DN0+8.IMM16A+8.IMM16B:D2:::or
1993 "or"
1994 *mn10300
1995 {
1996 // OP_FAE40000 ();
1997 PC = cia;
1998 genericOr(FETCH16(IMM16A, IMM16B), REG_D0 + DN0);
1999 }
2000
2001
2002 // 1111 1100 1110 01Dn imm32...; or imm32,Dn
2003 8.0xfc+4.0xe,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::or
2004 "or"
2005 *mn10300
2006 {
2007 // OP_FCE40000 ();
2008 PC = cia;
2009 genericOr(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_D0 + DN0);
2010 }
2011
2012
2013 // 1111 1010 1111 1101 imm16...; or imm16,PSW (imm16 is zero-extended.)
2014 8.0xfa+8.0xfd+8.IMM16A+8.IMM16B:D2a:::or
2015 "or"
2016 *mn10300
2017 {
2018 // OP_FAFD0000 ();
2019 PC = cia;
2020 PSW |= FETCH16(IMM16A, IMM16B);
2021 }
2022
2023
2024 // 1111 0010 0010 DmDn; xor Dm,Dn
2025 8.0xf2+4.0x2,2.DM1,2.DN0:D0:::xor
2026 "xor"
2027 *mn10300
2028 {
2029 // OP_F220 ();
2030 PC = cia;
2031 genericXor(State.regs[REG_D0 + DM1], REG_D0 + DN0);
2032 }
2033
2034
2035 // 1111 1010 1110 10Dn imm16...; xor imm16,Dn (imm16 is zero-extended.)
2036 8.0xfa+4.0xe,10,2.DN0+8.IMM16A+8.IMM16B:D2:::xor
2037 "xor"
2038 *mn10300
2039 {
2040 // OP_FAE80000 ();
2041 PC = cia;
2042 genericXor(FETCH16(IMM16A, IMM16B), REG_D0 + DN0);
2043 }
2044
2045
2046 // 1111 1100 1110 10Dn imm32...; xor imm32,Dn
2047 8.0xfc+4.0xe,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::xor
2048 "xor"
2049 *mn10300
2050 {
2051 // OP_FCE80000 ();
2052 PC = cia;
2053 genericXor(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_D0 + DN0);
2054 }
2055
2056
2057 // 1111 0010 0011 00Dn; not Dn
2058 8.0xf2+4.0x3,00,2.DN0:D0:::not
2059 "not"
2060 *mn10300
2061 {
2062 // OP_F230 ();
2063 int n, z;
2064
2065 PC = cia;
2066 State.regs[REG_D0 + DN0] = ~State.regs[REG_D0 + DN0];
2067 z = (State.regs[REG_D0 + DN0] == 0);
2068 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2069 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2070 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2071 }
2072
2073
2074 // 1111 1000 1110 11Dn imm8....; btst imm8,Dn (imm8 is zero-extended.)
2075 8.0xf8+4.0xe,11,2.DN0+8.IMM8:D1:::btst
2076 "btst"
2077 *mn10300
2078 {
2079 // OP_F8EC00 ();
2080 PC = cia;
2081 genericBtst(IMM8, State.regs[REG_D0 + DN0]);
2082 }
2083
2084
2085 // 1111 1010 1110 11Dn imm16.....; btst imm16,Dn (imm16 is zero-extended.)
2086 8.0xfa+4.0xe,11,2.DN0+8.IMM16A+8.IMM16B:D2:::btst
2087 "btst"
2088 *mn10300
2089 {
2090 // OP_FAEC0000 ();
2091 PC = cia;
2092 genericBtst(FETCH16(IMM16A, IMM16B), State.regs[REG_D0 + DN0]);
2093 }
2094
2095
2096 // 1111 1100 1110 11Dn imm32...; btst imm32,Dn
2097 8.0xfc+4.0xe,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::btst
2098 "btst"
2099 *mn10300
2100 {
2101 // OP_FCEC0000 ();
2102 PC = cia;
2103 genericBtst(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
2104 State.regs[REG_D0 + DN0]);
2105 }
2106
2107
2108 // 1111 1110 0000 0010 abs32... imm8....; btst imm8,(abs32) (imm8 is zero-extended., processing unit: byte)
2109 8.0xfe+8.0x02+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D+8.IMM8:D5:::btst
2110 "btst"
2111 *mn10300
2112 {
2113 // OP_FE020000 ();
2114 PC = cia;
2115 genericBtst(IMM8,
2116 load_byte(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
2117 }
2118
2119
2120 // 1111 1010 1111 10An d8...... imm8....;
2121 // btst imm8,(d8,An) (d8 is sign-extended,imm8 is zero-extended., processing unit: byte)
2122 8.0xfa+4.0xf,10,2.AN0+8.D8+8.IMM8:D2a:::btst
2123 "btst"
2124 *mn10300
2125 {
2126 // OP_FAF80000 ();
2127 PC = cia;
2128 genericBtst(IMM8,
2129 load_byte(State.regs[REG_A0 + AN0] + EXTEND8(D8)));
2130 }
2131
2132
2133 // 1111 0000 1000 DmAn; bset Dm,(An) (Processing unit byte)
2134 8.0xf0+4.8,2.DM1,2.AN0:D0:::bset
2135 "bset"
2136 *mn10300
2137 {
2138 // OP_F080 ();
2139 unsigned long temp;
2140 int z;
2141
2142 PC = cia;
2143 temp = load_byte (State.regs[REG_A0 + AN0]);
2144 z = (temp & State.regs[REG_D0 + DM1]) == 0;
2145 temp |= State.regs[REG_D0 + DM1];
2146 store_byte (State.regs[REG_A0 + AN0], temp);
2147 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2148 PSW |= (z ? PSW_Z : 0);
2149 }
2150
2151
2152 // 1111 1110 0000 0000 abs32... imm8....;
2153 // bset imm8,(abs32) (imm8 is zero-extended., processing unit: byte)
2154 8.0xfe+8.0x00+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D+8.IMM8:D5:::bset
2155 "bset"
2156 *mn10300
2157 {
2158 // OP_FE000000 ();
2159 unsigned long temp;
2160 int z;
2161
2162 PC = cia;
2163 temp = load_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
2164 z = (temp & IMM8) == 0;
2165 temp |= IMM8;
2166 store_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), temp);
2167 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2168 PSW |= (z ? PSW_Z : 0);
2169 }
2170
2171
2172 // 1111 1010 1111 00AnAn d8...... imm8....;
2173 // bset imm8,(d8,An) (d8 is sign-extended, imm8 is zero-extended., processing unit: byte)
2174 8.0xfa+4.0xf,00,2.AN0+8.D8+8.IMM8:D2:::bset
2175 "bset"
2176 *mn10300
2177 {
2178 // OP_FAF00000 ();
2179 unsigned long temp;
2180 int z;
2181
2182 PC = cia;
2183 temp = load_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)));
2184 z = (temp & (IMM8)) == 0;
2185 temp |= (IMM8);
2186 store_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)), temp);
2187 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2188 PSW |= (z ? PSW_Z : 0);
2189 }
2190
2191
2192 // 1111 0000 1001 DmAn; bclr Dm,(An) (Processing unit byte)
2193 8.0xf0+4.0x9,2.DM1,2.AN0:D0:::bclr
2194 "bclr"
2195 *mn10300
2196 {
2197 // OP_F090 ();
2198 unsigned long temp;
2199 int z;
2200
2201 PC = cia;
2202 temp = load_byte (State.regs[REG_A0 + AN0]);
2203 z = (temp & State.regs[REG_D0 + DM1]) == 0;
2204 temp = temp & ~State.regs[REG_D0 + DM1];
2205 store_byte (State.regs[REG_A0 + AN0], temp);
2206 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2207 PSW |= (z ? PSW_Z : 0);
2208 }
2209
2210
2211 // 1111 1110 0000 0001 abs32... imm8....;
2212 // bclr imm8,(abs32) (imm8 is zero-extended., processing unit: byte)
2213 8.0xfe+8.0x01+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D+8.IMM8:D5:::bclr
2214 "bclr"
2215 *mn10300
2216 {
2217 // OP_FE010000 ();
2218 unsigned long temp;
2219 int z;
2220
2221 PC = cia;
2222 temp = load_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
2223 z = (temp & IMM8) == 0;
2224 temp = temp & ~(IMM8);
2225 store_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), temp);
2226 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2227 PSW |= (z ? PSW_Z : 0);
2228 }
2229
2230
2231 // 1111 1010 1111 01An d8...... imm8....;
2232 // bclr imm8,(d8,An) (d8 is sign-extended, imm8 is zero-extended., processing unit: byte)
2233 8.0xfa+4.0xf,01,2.AN0+8.D8+8.IMM8:D2:::bclr
2234 "bclr"
2235 *mn10300
2236 {
2237 // OP_FAF40000 ();
2238 unsigned long temp;
2239 int z;
2240
2241 PC = cia;
2242 temp = load_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)));
2243 z = (temp & (IMM8)) == 0;
2244 temp = temp & ~(IMM8);
2245 store_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)), temp);
2246 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2247 PSW |= (z ? PSW_Z : 0);
2248 }
2249
2250
2251 // 1111 0010 1011 DmDn; asr Dm,Dn
2252 8.0xf2+4.0xb,2.DM1,2.DN0:D0:::asr
2253 "asr"
2254 *mn10300
2255 {
2256 // OP_F2B0 ();
2257 long temp;
2258 int z, n, c;
2259
2260 PC = cia;
2261 temp = State.regs[REG_D0 + DN0];
2262 c = temp & 1;
2263 temp >>= State.regs[REG_D0 + DM1];
2264 State.regs[REG_D0 + DN0] = temp;
2265 z = (State.regs[REG_D0 + DN0] == 0);
2266 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2267 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2268 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2269 }
2270
2271
2272 // 1111 1000 1100 10Dn imm8...; asr imm8,Dn (imm8 is zero-extended.)
2273 8.0xf8+4.0xc,10,2.DN0+8.IMM8:D1:::asr
2274 "asr"
2275 *mn10300
2276 {
2277 // OP_F8C800 ();
2278 long temp;
2279 int z, n, c;
2280
2281 PC = cia;
2282 temp = State.regs[REG_D0 + DN0];
2283 c = temp & 1;
2284 temp >>= IMM8;
2285 State.regs[REG_D0 + DN0] = temp;
2286 z = (State.regs[REG_D0 + DN0] == 0);
2287 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2288 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2289 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2290 }
2291
2292
2293 // 1111 0010 1010 DmDn; lsr Dm,Dn
2294 8.0xf2+4.0xa,2.DM1,2.DN0:D0:::lsr
2295 "lsr"
2296 *mn10300
2297 {
2298 // OP_F2A0 ();
2299 int z, n, c;
2300
2301 PC = cia;
2302 c = State.regs[REG_D0 + DN0] & 1;
2303 State.regs[REG_D0 + DN0]
2304 >>= State.regs[REG_D0 + DM1];
2305 z = (State.regs[REG_D0 + DN0] == 0);
2306 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2307 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2308 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2309 }
2310
2311
2312 // 1111 1000 1100 01Dn imm8...; lsr imm8,Dn (imm8 is zero-extended.)
2313 8.0xf8+4.0xc,01,2.DN0+8.IMM8:D1:::lsr
2314 "lsr"
2315 *mn10300
2316 {
2317 // OP_F8C400 ();
2318 int z, n, c;
2319
2320 PC = cia;
2321 c = State.regs[REG_D0 + DN0] & 1;
2322 State.regs[REG_D0 + DN0] >>= IMM8;
2323 z = (State.regs[REG_D0 + DN0] == 0);
2324 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2325 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2326 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2327 }
2328
2329
2330 // 1111 0010 1001 DmDn; asl Dm,Dn
2331 8.0xf2+4.0x9,2.DM1,2.DN0:D0:::asl
2332 "asl"
2333 *mn10300
2334 {
2335 // OP_F290 ();
2336 int n, z;
2337
2338 PC = cia;
2339 State.regs[REG_D0 + DN0]
2340 <<= State.regs[REG_D0 + DM1];
2341 z = (State.regs[REG_D0 + DN0] == 0);
2342 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2343 PSW &= ~(PSW_Z | PSW_N);
2344 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2345 }
2346
2347
2348 // 1111 1000 1100 00Dn imm8...; asl imm8,Dn (imm8 is zero-extended.)
2349 8.0xf8+4.0xc,00,2.DN0+8.IMM8:D1:::asl
2350 "asl"
2351 *mn10300
2352 {
2353 // OP_F8C000 ();
2354 int n, z;
2355
2356 PC = cia;
2357 State.regs[REG_D0 + DN0] <<= IMM8;
2358 z = (State.regs[REG_D0 + DN0] == 0);
2359 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2360 PSW &= ~(PSW_Z | PSW_N);
2361 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2362 }
2363
2364
2365 // 0101 01Dn; als2 Dn
2366 4.0x5,01,2.DN0:S0:::asl2
2367 "asl2"
2368 *mn10300
2369 {
2370 // OP_54 ();
2371 int n, z;
2372 PC = cia;
2373
2374 State.regs[REG_D0 + DN0] <<= 2;
2375 z = (State.regs[REG_D0 + DN0] == 0);
2376 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
2377 PSW &= ~(PSW_Z | PSW_N);
2378 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2379 }
2380
2381
2382 // 1111 0010 1000 01Dn; ror Dn
2383 8.0xf2+4.0x8,01,2.DN0:D0:::ror
2384 "ror"
2385 *mn10300
2386 {
2387 // OP_F284 ();
2388 unsigned long value;
2389 int c,n,z;
2390
2391 PC = cia;
2392 value = State.regs[REG_D0 + DN0];
2393 c = (value & 0x1);
2394
2395 value >>= 1;
2396 value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0;
2397 State.regs[REG_D0 + DN0] = value;
2398 z = (value == 0);
2399 n = (value & 0x80000000) != 0;
2400 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2401 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2402 }
2403
2404
2405 // 1111 0010 1000 00Dn; rol Dn
2406 8.0xf2+4.0x8,00,2.DN0:D0:::rol
2407 "rol"
2408 *mn10300
2409 {
2410 // handle ror above, too.
2411 // OP_F280 ();
2412 unsigned long value;
2413 int c,n,z;
2414
2415 PC = cia;
2416 value = State.regs[REG_D0 + DN0];
2417 c = (value & 0x80000000) ? 1 : 0;
2418
2419 value <<= 1;
2420 value |= ((PSW & PSW_C) != 0);
2421 State.regs[REG_D0 + DN0] = value;
2422 z = (value == 0);
2423 n = (value & 0x80000000) != 0;
2424 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2425 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2426 }
2427
2428
2429 // 1100 1000 d8......; beq (d8,PC) (d8 is sign-extended)
2430 8.0xc8+8.D8:S1:::beq
2431 "beq"
2432 *mn10300
2433 {
2434 // OP_C800 ();
2435 PC = cia;
2436 if ((PSW & PSW_Z))
2437 {
2438 State.regs[REG_PC] += EXTEND8 (D8);
2439 nia = PC;
2440 }
2441 }
2442
2443
2444 // 1100 1001 d8......; bne (d8,PC) (d8 is sign-extended)
2445 8.0xc9+8.D8:S1:::bne
2446 "bne"
2447 *mn10300
2448 {
2449 // OP_C900 ();
2450 PC = cia;
2451 if (!(PSW & PSW_Z))
2452 {
2453 State.regs[REG_PC] += EXTEND8 (D8);
2454 nia = PC;
2455 }
2456 }
2457
2458
2459 // 1100 0001 d8......; bgt (d8,PC) (d8 is sign-extended)
2460 8.0xc1+8.D8:S1:::bgt
2461 "bgt"
2462 *mn10300
2463 {
2464 // OP_C100 ();
2465 PC = cia;
2466 if (!((PSW & PSW_Z)
2467 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))))
2468 {
2469 State.regs[REG_PC] += EXTEND8 (D8);
2470 nia = PC;
2471 }
2472 }
2473
2474
2475 // 1100 0010 d8......; bge (d8,PC) (d8 is sign-extended)
2476 8.0xc2+8.D8:S1:::bge
2477 "bge"
2478 *mn10300
2479 {
2480 // OP_C200 ();
2481 PC = cia;
2482 if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
2483 {
2484 State.regs[REG_PC] += EXTEND8 (D8);
2485 nia = PC;
2486 }
2487 }
2488
2489
2490 // 1100 0011 d8......; ble (d8,PC) (d8 is sign-extended)
2491 8.0xc3+8.D8:S1:::ble
2492 "ble"
2493 *mn10300
2494 {
2495 // OP_C300 ();
2496 PC = cia;
2497 if ((PSW & PSW_Z)
2498 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
2499 {
2500 State.regs[REG_PC] += EXTEND8 (D8);
2501 nia = PC;
2502 }
2503 }
2504
2505
2506 // 1100 0000 d8......; blt (d8,PC) (d8 is sign-extended)
2507 8.0xc0+8.D8:S1:::blt
2508 "blt"
2509 *mn10300
2510 {
2511 // OP_C000 ();
2512 PC = cia;
2513 if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))
2514 {
2515 State.regs[REG_PC] += EXTEND8 (D8);
2516 nia = PC;
2517 }
2518 }
2519
2520
2521 // 1100 0101 d8......; bhi (d8,PC) (d8 is sign-extended)
2522 8.0xc5+8.D8:S1:::bhi
2523 "bhi"
2524 *mn10300
2525 {
2526 // OP_C500 ();
2527 PC = cia;
2528 if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
2529 {
2530 State.regs[REG_PC] += EXTEND8 (D8);
2531 nia = PC;
2532 }
2533 }
2534
2535
2536 // 1100 0110 d8......; bcc (d8,PC) (d8 is sign-extended)
2537 8.0xc6+8.D8:S1:::bcc
2538 "bcc"
2539 *mn10300
2540 {
2541 // OP_C600 ();
2542 PC = cia;
2543 if (!(PSW & PSW_C))
2544 {
2545 State.regs[REG_PC] += EXTEND8 (D8);
2546 nia = PC;
2547 }
2548 }
2549
2550
2551 // 1100 0101 d8......; bls (d8,PC) (d8 is sign-extended)
2552 8.0xc7+8.D8:S1:::bls
2553 "bls"
2554 *mn10300
2555 {
2556 // OP_C700 ();
2557 PC = cia;
2558 if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
2559 {
2560 State.regs[REG_PC] += EXTEND8 (D8);
2561 nia = PC;
2562 }
2563 }
2564
2565
2566 // 1100 0100 d8......; bcs (d8,PC) (d8 is sign-extended)
2567 8.0xc4+8.D8:S1:::bcs
2568 "bcs"
2569 *mn10300
2570 {
2571 // OP_C400 ();
2572 PC = cia;
2573 if (PSW & PSW_C)
2574 {
2575 State.regs[REG_PC] += EXTEND8 (D8);
2576 nia = PC;
2577 }
2578 }
2579
2580
2581 // 1111 1000 1110 1000 d8......; bvc (d8,PC) (d8 is sign-extended)
2582 8.0xf8+8.0xe8+8.D8:D1:::bvc
2583 "bvc"
2584 *mn10300
2585 {
2586 // OP_F8E800 ();
2587 PC = cia;
2588 if (!(PSW & PSW_V))
2589 {
2590 State.regs[REG_PC] += EXTEND8 (D8);
2591 nia = PC;
2592 }
2593 }
2594
2595
2596 // 1111 1000 1110 1001 d8......; bvs (d8,PC) (d8 is sign-extended)
2597 8.0xf8+8.0xe9+8.D8:D1:::bvs
2598 "bvs"
2599 *mn10300
2600 {
2601 // OP_F8E900 ();
2602 PC = cia;
2603 if (PSW & PSW_V)
2604 {
2605 State.regs[REG_PC] += EXTEND8 (D8);
2606 nia = PC;
2607 }
2608 }
2609
2610
2611 // 1111 1000 1110 1010 d8......; bnc (d8,PC) (d8 is sign-extended)
2612 8.0xf8+8.0xea+8.D8:D1:::bnc
2613 "bnc"
2614 *mn10300
2615 {
2616 // OP_F8EA00 ();
2617 PC = cia;
2618 if (!(PSW & PSW_N))
2619 {
2620 State.regs[REG_PC] += EXTEND8 (D8);
2621 nia = PC;
2622 }
2623 }
2624
2625
2626 // 1111 1000 1110 1010 d8......; bns (d8,PC) (d8 is sign-extended)
2627 8.0xf8+8.0xeb+8.D8:D1:::bns
2628 "bns"
2629 *mn10300
2630 {
2631 // OP_F8EB00 ();
2632 PC = cia;
2633 if (PSW & PSW_N)
2634 {
2635 State.regs[REG_PC] += EXTEND8 (D8);
2636 nia = PC;
2637 }
2638 }
2639
2640
2641 // 1100 1010 d8......; bra (d8,PC) (d8 is sign-extended)
2642 8.0xca+8.D8:S1:::bra
2643 "bra"
2644 *mn10300
2645 {
2646 // OP_CA00 ();
2647 PC = cia;
2648 State.regs[REG_PC] += EXTEND8 (D8);
2649 nia = PC;
2650 }
2651
2652
2653 // 1101 1000; leq
2654 8.0xd8:S0:::leq
2655 "leq"
2656 *mn10300
2657 {
2658 // OP_D8 ();
2659 PC = cia;
2660 if (PSW & PSW_Z)
2661 {
2662 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
2663 nia = PC;
2664 }
2665 }
2666
2667
2668 // 1101 1001; lne
2669 8.0xd9:S0:::lne
2670 "lne"
2671 *mn10300
2672 {
2673 // OP_D9 ();
2674 PC = cia;
2675 if (!(PSW & PSW_Z))
2676 {
2677 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
2678 nia = PC;
2679 }
2680 }
2681
2682
2683 // 1101 0001; lgt
2684 8.0xd1:S0:::lgt
2685 "lgt"
2686 *mn10300
2687 {
2688 // OP_D1 ();
2689 PC = cia;
2690 if (!((PSW & PSW_Z)
2691 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))))
2692 {
2693 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
2694 nia = PC;
2695 }
2696 }
2697
2698
2699 // 1101 0010; lge
2700 8.0xd2:S0:::lge
2701 "lge"
2702 *mn10300
2703 {
2704 // OP_D2 ();
2705 PC = cia;
2706 if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
2707 {
2708 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
2709 nia = PC;
2710 }
2711 }
2712
2713
2714 // 1101 0011; lle
2715 8.0xd3:S0:::lle
2716 "lle"
2717 *mn10300
2718 {
2719 // OP_D3 ();
2720 PC = cia;
2721 if ((PSW & PSW_Z)
2722 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
2723 {
2724 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
2725 nia = PC;
2726 }
2727 }
2728
2729
2730 // 1101 0000; llt
2731 8.0xd0:S0:::llt
2732 "llt"
2733 *mn10300
2734 {
2735 // OP_D0 ();
2736 PC = cia;
2737 if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))
2738 {
2739 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
2740 nia = PC;
2741 }
2742 }
2743
2744
2745 // 1101 0101; lhi
2746 8.0xd5:S0:::lhi
2747 "lhi"
2748 *mn10300
2749 {
2750 // OP_D5 ();
2751 PC = cia;
2752 if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
2753 {
2754 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
2755 nia = PC;
2756 }
2757 }
2758
2759
2760 // 1101 0110; lcc
2761 8.0xd6:S0:::lcc
2762 "lcc"
2763 *mn10300
2764 {
2765 // OP_D6 ();
2766 PC = cia;
2767 if (!(PSW & PSW_C))
2768 {
2769 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
2770 nia = PC;
2771 }
2772 }
2773
2774
2775 // 1101 0111; lls
2776 8.0xd7:S0:::lls
2777 "lls"
2778 *mn10300
2779 {
2780 // OP_D7 ();
2781 PC = cia;
2782 if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
2783 {
2784 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
2785 nia = PC;
2786 }
2787 }
2788
2789
2790 // 1101 0100; lcs
2791 8.0xd4:S0:::lcs
2792 "lcs"
2793 *mn10300
2794 {
2795 // OP_D4 ();
2796 PC = cia;
2797 if (PSW & PSW_C)
2798 {
2799 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
2800 nia = PC;
2801 }
2802 }
2803
2804
2805 // 1101 1010; lra
2806 8.0xda:S0:::lra
2807 "lra"
2808 *mn10300
2809 {
2810 // OP_DA ();
2811 PC = cia;
2812 State.regs[REG_PC] = State.regs[REG_LAR] - 4;
2813 nia = PC;
2814 }
2815
2816
2817 // 1101 1010; setlb
2818 8.0xdb:S0:::setlb
2819 "setlb"
2820 *mn10300
2821 {
2822 // OP_DB ();
2823 PC = cia;
2824 State.regs[REG_LIR] = load_word (State.regs[REG_PC] + 1);
2825 State.regs[REG_LAR] = State.regs[REG_PC] + 5;
2826 }
2827
2828
2829 // 1111 0000 1111 01An; jmp (An)
2830 8.0xf0+4.0xf,01,2.AN0:D0:::jmp
2831 "jmp"
2832 *mn10300
2833 {
2834 // OP_F0F4 ();
2835 PC = State.regs[REG_A0 + AN0];
2836 nia = PC;
2837 }
2838
2839
2840 // 1100 1100 d16.....; jmp (d16,PC) (d16 is sign-extended.)
2841 8.0xcc+8.D16A+8.D16B:S2:::jmp
2842 "jmp"
2843 *mn10300
2844 {
2845 // OP_CC0000 ();
2846 PC = cia + EXTEND16(FETCH16(D16A, D16B));
2847 nia = PC;
2848 }
2849
2850
2851 // 1101 1100 d32........; jmp (d32, PC)
2852 8.0xdc+8.D32A+8.D32B+8.D32C+8.D32D:S4:::jmp
2853 "jmp"
2854 *mn10300
2855 {
2856 // OP_DC000000 ();
2857 PC = cia + FETCH32(D32A, D32B, D32C, D32D);
2858 nia = PC;
2859 }
2860
2861
2862 // 1100 1101 d16..... regs.... imm8....;
2863 // call (d16,PC),regs,imm8 (d16 is sign-extended., imm8 is zero-extended.)
2864 8.0xcd+8.D16A+8.D16B+8.REGS+8.IMM8:S4:::call
2865 "call"
2866 *mn10300
2867 {
2868 // OP_CD000000 ();
2869 unsigned int next_pc, sp;
2870 unsigned long mask;
2871
2872 PC = cia;
2873 sp = State.regs[REG_SP];
2874 next_pc = PC + 5;
2875 store_word(sp, next_pc);
2876
2877 mask = REGS;
2878
2879 if (mask & 0x80)
2880 {
2881 sp -= 4;
2882 store_word (sp, State.regs[REG_D0 + 2]);
2883 }
2884
2885 if (mask & 0x40)
2886 {
2887 sp -= 4;
2888 store_word (sp, State.regs[REG_D0 + 3]);
2889 }
2890
2891 if (mask & 0x20)
2892 {
2893 sp -= 4;
2894 store_word (sp, State.regs[REG_A0 + 2]);
2895 }
2896
2897 if (mask & 0x10)
2898 {
2899 sp -= 4;
2900 store_word (sp, State.regs[REG_A0 + 3]);
2901 }
2902
2903 if (mask & 0x8)
2904 {
2905 sp -= 4;
2906 store_word (sp, State.regs[REG_D0]);
2907 sp -= 4;
2908 store_word (sp, State.regs[REG_D0 + 1]);
2909 sp -= 4;
2910 store_word (sp, State.regs[REG_A0]);
2911 sp -= 4;
2912 store_word (sp, State.regs[REG_A0 + 1]);
2913 sp -= 4;
2914 store_word (sp, State.regs[REG_MDR]);
2915 sp -= 4;
2916 store_word (sp, State.regs[REG_LIR]);
2917 sp -= 4;
2918 store_word (sp, State.regs[REG_LAR]);
2919 sp -= 4;
2920 }
2921
2922 /* Update the stack pointer, note that the register saves to do not
2923 modify SP. The SP adjustment is derived totally from the imm8
2924 field. */
2925 State.regs[REG_SP] -= IMM8;
2926 State.regs[REG_MDR] = next_pc;
2927 State.regs[REG_PC] += EXTEND16 (FETCH16(D16A, D16B));
2928 nia = PC;
2929 }
2930
2931
2932 // 1101 1101 d32..... regs.... imm8....;
2933 // call (d32,PC),regs,imm8 (imm8 is zero-extended.)
2934 8.0xdd+8.D32A+8.D32B+8.D32C+8.D32D+8.REGS+8.IMM8:S6:::call
2935 "call"
2936 *mn10300
2937 {
2938 // op_DD000000();
2939 unsigned int next_pc, sp;
2940 unsigned long mask;
2941
2942 PC = cia;
2943 sp = State.regs[REG_SP];
2944 next_pc = State.regs[REG_PC] + 7;
2945 /* could assert that nia == next_pc here */
2946 store_word(sp, next_pc);
2947 // store_byte(sp, next_pc & 0xff);
2948 // store_byte(sp+1, (next_pc & 0xff00) >> 8 );
2949 // store_byte(sp+2, (next_pc & 0xff0000) >> 16 );
2950 // store_byte(sp+3, (next_pc & 0xff000000) >> 24);
2951
2952 mask = REGS;
2953
2954 if (mask & 0x80)
2955 {
2956 sp -= 4;
2957 store_word (sp, State.regs[REG_D0 + 2]);
2958 }
2959
2960 if (mask & 0x40)
2961 {
2962 sp -= 4;
2963 store_word (sp, State.regs[REG_D0 + 3]);
2964 }
2965
2966 if (mask & 0x20)
2967 {
2968 sp -= 4;
2969 store_word (sp, State.regs[REG_A0 + 2]);
2970 }
2971
2972 if (mask & 0x10)
2973 {
2974 sp -= 4;
2975 store_word (sp, State.regs[REG_A0 + 3]);
2976 }
2977
2978 if (mask & 0x8)
2979 {
2980 sp -= 4;
2981 store_word (sp, State.regs[REG_D0]);
2982 sp -= 4;
2983 store_word (sp, State.regs[REG_D0 + 1]);
2984 sp -= 4;
2985 store_word (sp, State.regs[REG_A0]);
2986 sp -= 4;
2987 store_word (sp, State.regs[REG_A0 + 1]);
2988 sp -= 4;
2989 store_word (sp, State.regs[REG_MDR]);
2990 sp -= 4;
2991 store_word (sp, State.regs[REG_LIR]);
2992 sp -= 4;
2993 store_word (sp, State.regs[REG_LAR]);
2994 sp -= 4;
2995 }
2996
2997 /* Update the stack pointer, note that the register saves to do not
2998 modify SP. The SP adjustment is derived totally from the imm8
2999 field. */
3000 State.regs[REG_SP] -= IMM8;
3001 State.regs[REG_MDR] = next_pc;
3002 State.regs[REG_PC] += FETCH32(D32A, D32B, D32C, D32D);
3003 nia = PC;
3004 }
3005
3006
3007 // 1111 0000 1111 00An; calls (An)
3008 8.0xf0+4.0xf,00,2.AN0:D0:::calls
3009 "calls"
3010 *mn10300
3011 {
3012 // OP_F0F0 ();
3013 unsigned int next_pc, sp;
3014
3015 PC = cia;
3016 sp = State.regs[REG_SP];
3017 next_pc = State.regs[REG_PC] + 2;
3018 store_word(sp, next_pc);
3019 State.regs[REG_MDR] = next_pc;
3020 State.regs[REG_PC] = State.regs[REG_A0 + AN0];
3021 nia = PC;
3022 }
3023
3024
3025 // 1111 1010 1111 1111 d16.....; calls (d16,PC) (d16 is sign-extended.)
3026 8.0xfa+8.0xff+8.D16A+8.D16B:D2:::calls
3027 "calls"
3028 *mn10300
3029 {
3030 // OP_FAFF0000 ();
3031 unsigned int next_pc, sp;
3032
3033 PC = cia;
3034 sp = State.regs[REG_SP];
3035 next_pc = State.regs[REG_PC] + 4;
3036 store_word(sp, next_pc);
3037 State.regs[REG_MDR] = next_pc;
3038 State.regs[REG_PC] += EXTEND16 (FETCH16(D16A, D16B));
3039 nia = PC;
3040 }
3041
3042
3043 // 1111 1100 1111 1111 d32.....; calls (d32,PC)
3044 8.0xfc+8.0xff+8.D32A+8.D32B+8.D32C+8.D32D:D4:::calls
3045 "calls"
3046 *mn10300
3047 {
3048 // OP_FCFF0000 ();
3049 unsigned int next_pc, sp;
3050
3051 PC = cia;
3052 sp = State.regs[REG_SP];
3053 next_pc = State.regs[REG_PC] + 6;
3054 store_word(sp, next_pc);
3055 State.regs[REG_MDR] = next_pc;
3056 State.regs[REG_PC] += FETCH32(D32A, D32B, D32C, D32D);
3057 nia = PC;
3058 }
3059
3060
3061 // 1101 1111 regs.... imm8....; ret regs,imm8 (imm8 is zero-extended.)
3062 8.0xdf+8.REGS+8.IMM8:S2:::ret
3063 "ret"
3064 *mn10300
3065 {
3066 // OP_DF0000 ();
3067 unsigned int sp, offset;
3068 unsigned long mask;
3069
3070 PC = cia;
3071 State.regs[REG_SP] += IMM8;
3072 sp = State.regs[REG_SP];
3073
3074 offset = -4;
3075 mask = REGS;
3076
3077 if (mask & 0x80)
3078 {
3079 State.regs[REG_D0 + 2] = load_word (sp + offset);
3080 offset -= 4;
3081 }
3082
3083 if (mask & 0x40)
3084 {
3085 State.regs[REG_D0 + 3] = load_word (sp + offset);
3086 offset -= 4;
3087 }
3088
3089 if (mask & 0x20)
3090 {
3091 State.regs[REG_A0 + 2] = load_word (sp + offset);
3092 offset -= 4;
3093 }
3094
3095 if (mask & 0x10)
3096 {
3097 State.regs[REG_A0 + 3] = load_word (sp + offset);
3098 offset -= 4;
3099 }
3100
3101 if (mask & 0x8)
3102 {
3103 State.regs[REG_D0] = load_word (sp + offset);
3104 offset -= 4;
3105 State.regs[REG_D0 + 1] = load_word (sp + offset);
3106 offset -= 4;
3107 State.regs[REG_A0] = load_word (sp + offset);
3108 offset -= 4;
3109 State.regs[REG_A0 + 1] = load_word (sp + offset);
3110 offset -= 4;
3111 State.regs[REG_MDR] = load_word (sp + offset);
3112 offset -= 4;
3113 State.regs[REG_LIR] = load_word (sp + offset);
3114 offset -= 4;
3115 State.regs[REG_LAR] = load_word (sp + offset);
3116 offset -= 4;
3117 }
3118
3119 /* Restore the PC value. */
3120 State.regs[REG_PC] = load_word(sp);
3121 nia = PC;
3122 }
3123
3124
3125 // 1101 1110 regs.... imm8....; retf regs,imm8 (imm8 is zero-extended.)
3126 8.0xde+8.REGS+8.IMM8:S2:::retf
3127 "retf"
3128 *mn10300
3129 {
3130 // OP_DE0000 ();
3131 unsigned int sp, offset;
3132 unsigned long mask;
3133
3134 PC = cia;
3135 State.regs[REG_SP] += IMM8;
3136 sp = State.regs[REG_SP];
3137 State.regs[REG_PC] = State.regs[REG_MDR] - 3;
3138
3139 offset = -4;
3140 mask = REGS;
3141
3142 if (mask & 0x80)
3143 {
3144 State.regs[REG_D0 + 2] = load_word (sp + offset);
3145 offset -= 4;
3146 }
3147
3148 if (mask & 0x40)
3149 {
3150 State.regs[REG_D0 + 3] = load_word (sp + offset);
3151 offset -= 4;
3152 }
3153
3154 if (mask & 0x20)
3155 {
3156 State.regs[REG_A0 + 2] = load_word (sp + offset);
3157 offset -= 4;
3158 }
3159
3160 if (mask & 0x10)
3161 {
3162 State.regs[REG_A0 + 3] = load_word (sp + offset);
3163 offset -= 4;
3164 }
3165
3166 if (mask & 0x8)
3167 {
3168 State.regs[REG_D0] = load_word (sp + offset);
3169 offset -= 4;
3170 State.regs[REG_D0 + 1] = load_word (sp + offset);
3171 offset -= 4;
3172 State.regs[REG_A0] = load_word (sp + offset);
3173 offset -= 4;
3174 State.regs[REG_A0 + 1] = load_word (sp + offset);
3175 offset -= 4;
3176 State.regs[REG_MDR] = load_word (sp + offset);
3177 offset -= 4;
3178 State.regs[REG_LIR] = load_word (sp + offset);
3179 offset -= 4;
3180 State.regs[REG_LAR] = load_word (sp + offset);
3181 offset -= 4;
3182 }
3183 }
3184
3185
3186 // 1111 0000 1111 1100; rets
3187 8.0xf0+8.0xfc:D0:::rets
3188 "rets"
3189 *mn10300
3190 {
3191 // OP_F0FC ();
3192 unsigned int sp;
3193
3194 sp = State.regs[REG_SP];
3195 State.regs[REG_PC] = load_word(sp);
3196 nia = PC;
3197 }
3198
3199
3200 // 1111 0000 1111 1101; rti
3201 8.0xf0+8.0xfd:D0:::rti
3202 "rti"
3203 *mn10300
3204 {
3205 // OP_F0FD ();
3206 unsigned int sp;
3207
3208 sp = State.regs[REG_SP];
3209 PSW = load_half(sp);
3210 State.regs[REG_PC] = load_word(sp+4);
3211 State.regs[REG_SP] +=8;
3212 nia = PC;
3213 }
3214
3215
3216 // 1111 0000 1111 1110; trap
3217 8.0xf0+8.0xfe:D0:::trap
3218 "trap"
3219 *mn10300
3220 {
3221 // OP_F0FE ();
3222 unsigned int sp, next_pc;
3223
3224 PC = cia;
3225 sp = State.regs[REG_SP];
3226 next_pc = State.regs[REG_PC] + 2;
3227 store_word(sp, next_pc);
3228 nia = PC;
3229 }
3230
3231
3232 // 1111 0000 1111 1111; rtm
3233 8.0xf0+8.0xff:D0:::rtm
3234 "rtm"
3235 *mn10300
3236 {
3237 // OP_F0FF ();
3238 PC = cia;
3239 abort ();
3240 }
3241
3242
3243 // 1100 1011; nop
3244 8.0xcb:S0:::nop
3245 "nop"
3246 *mn10300
3247 {
3248 // OP_CB ();
3249 PC = cia;
3250 }
3251
3252
3253 // 1111 0101 0000 DmDn; udf20 Dm,Dn
3254 8.0xf5+4.0x0,2.DN1,2.DN0:D0:::putx
3255 "putx"
3256 *mn10300
3257 {
3258 // OP_F500 ();
3259 PC = cia;
3260 State.regs[REG_MDRQ] = State.regs[REG_D0 + DN0];
3261 }
3262
3263
3264 // 1111 0110 1111 DmDn; udf15 Dm,Dn
3265 8.0xf6+4.0xf,2.DM1,2.DN0:D0:::getx
3266 "getx"
3267 *mn10300
3268 {
3269 // OP_F6F0 ();
3270 int z, n;
3271
3272 PC = cia;
3273 z = (State.regs[REG_MDRQ] == 0);
3274 n = ((State.regs[REG_MDRQ] & 0x80000000) != 0);
3275 State.regs[REG_D0 + DN0] = State.regs[REG_MDRQ];
3276
3277 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3278 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
3279 }
3280
3281
3282 // 1111 0110 0000 DmDn; udf00 Dm,Dn
3283 8.0xf6+4.0x0,2.DM1,2.DN0:D0:::mulq
3284 "mulq"
3285 *mn10300
3286 {
3287 // OP_F600 ();
3288 unsigned long long temp;
3289 int n, z;
3290
3291 PC = cia;
3292 temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
3293 * (signed64)(signed32)State.regs[REG_D0 + DM1]);
3294 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3295 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3296 z = (State.regs[REG_D0 + DN0] == 0);
3297 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3298 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3299 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3300 }
3301
3302
3303 // 1111 1001 0000 00Dn imm8....; udf00 imm8,Dn (imm8 is sign-extended.)
3304 8.0xf9+4.0x,00,2.DN0+8.IMM8:D1:::mulq
3305 "mulq"
3306 *mn10300
3307 {
3308 // OP_F90000 ();
3309 unsigned long long temp;
3310 int n, z;
3311
3312 PC = cia;
3313 temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
3314 * (signed64)(signed32)EXTEND8 (IMM8));
3315 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3316 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3317 z = (State.regs[REG_D0 + DN0] == 0);
3318 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3319 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3320 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3321 }
3322
3323
3324 // 1111 1011 0000 00Dn imm16...; udf00 imm16,Dn (imm16 is sign-extended.)
3325 8.0xfb+4.0x0,00,2.DN0+8.IMM16A+8.IMM16B:D2:::mulq
3326 "mulq"
3327 *mn10300
3328 {
3329 // OP_FB000000 ();
3330 unsigned long long temp;
3331 int n, z;
3332
3333 PC = cia;
3334 temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
3335 * (signed64)(signed32)EXTEND16 (FETCH16(IMM16A, IMM16B)));
3336 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3337 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3338 z = (State.regs[REG_D0 + DN0] == 0);
3339 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3340 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3341 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3342 }
3343
3344
3345 // 1111 1101 0000 00Dn imm32...; udf00 imm32,Dn
3346 8.0xfd+4.0x0,00,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::mulq
3347 "mulq"
3348 *mn10300
3349 {
3350 // OP_FD000000 ();
3351 unsigned long long temp;
3352 int n, z;
3353
3354 PC = cia;
3355 temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
3356 * (signed64)(signed32)(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
3357 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3358 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3359 z = (State.regs[REG_D0 + DN0] == 0);
3360 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3361 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3362 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3363 }
3364
3365
3366 // 1111 0110 0001 DmDn; udf01 Dm,Dn
3367 8.0xf6+4.0x1,2.DM1,2.DN0:D0:::mulqu
3368 "mulqu"
3369 *mn10300
3370 {
3371 // OP_F610 ();
3372 unsigned long long temp;
3373 int n, z;
3374
3375 PC = cia;
3376 temp = ((unsigned64) State.regs[REG_D0 + DN0]
3377 * (unsigned64) State.regs[REG_D0 + DM1]);
3378 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3379 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3380 z = (State.regs[REG_D0 + DN0] == 0);
3381 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3382 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3383 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3384 }
3385
3386
3387 // 1111 1001 0001 01Dn imm8....; udfu01 imm8,Dn (imm8 is zero-extended.)
3388 8.0xf9+4.0x1,01,2.DN0+8.IMM8:D1:::mulqu
3389 "mulqu"
3390 *mn10300
3391 {
3392 // OP_F91400 ();
3393 unsigned long long temp;
3394 int n, z;
3395
3396 PC = cia;
3397 temp = ((unsigned64)State.regs[REG_D0 + DN0]
3398 * (unsigned64)EXTEND8 (IMM8));
3399 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3400 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3401 z = (State.regs[REG_D0 + DN0] == 0);
3402 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3403 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3404 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3405 }
3406
3407
3408 // 1111 1011 0001 01Dn imm16...; udfu01 imm16,Dn (imm16 is zero-extended.)
3409 8.0xfb+4.0x1,01,2.DN0+8.IMM16A+8.IMM16B:D2:::mulqu
3410 "mulqu"
3411 *mn10300
3412 {
3413 // OP_FB140000 ();
3414 unsigned long long temp;
3415 int n, z;
3416
3417 PC = cia;
3418 temp = ((unsigned64)State.regs[REG_D0 + DN0]
3419 * (unsigned64) EXTEND16 (FETCH16(IMM16A, IMM16B)));
3420 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3421 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3422 z = (State.regs[REG_D0 + DN0] == 0);
3423 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3424 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3425 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3426 }
3427
3428
3429 // 1111 1101 0001 01Dn imm32...; udfu01 imm32,Dn
3430 8.0xfd+4.0x1,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::mulqu
3431 "mulqu"
3432 *mn10300
3433 {
3434 // OP_FD140000 ();
3435 unsigned long long temp;
3436 int n, z;
3437
3438 PC = cia;
3439 temp = ((unsigned64)State.regs[REG_D0 + DN0]
3440 * (unsigned64)(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
3441 State.regs[REG_D0 + DN0] = temp & 0xffffffff;
3442 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3443 z = (State.regs[REG_D0 + DN0] == 0);
3444 n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
3445 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3446 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3447 }
3448
3449
3450 // 1111 0110 0100 DmDn; udf04 Dm,Dn
3451 8.0xf6+4.0x4,2.DM1,2.DN0:D0:::sat16
3452 "sat16"
3453 *mn10300
3454 {
3455 // OP_F640 ();
3456 int temp;
3457
3458 PC = cia;
3459 temp = State.regs[REG_D0 + DM1];
3460 temp = (temp > 0x7fff ? 0x7fff : temp);
3461 temp = (temp < -0x8000 ? -0x8000 : temp);
3462 State.regs[REG_D0 + DN0] = temp;
3463 }
3464
3465
3466 // 1111 0110 0101 DmDn; udf05 Dm,Dn
3467 8.0xf6+4.0x5,2.DM1,2.DN0:D0:::sat24
3468 "sat24"
3469 *mn10300
3470 {
3471 // OP_F650 ();
3472 int temp;
3473
3474 PC = cia;
3475 temp = State.regs[REG_D0 + DM1];
3476 temp = (temp > 0x7fffff ? 0x7fffff : temp);
3477 temp = (temp < -0x800000 ? -0x800000 : temp);
3478 State.regs[REG_D0 + DN0] = temp;
3479 }
3480
3481
3482 // 1111 0110 0111 DmDn; udf07 Dm,Dn
3483 8.0xf6+4.0x7,2.DM1,2.DN0:D0:::bsch
3484 "bsch"
3485 *mn10300
3486 {
3487 // OP_F670 ();
3488 int temp, c;
3489
3490 PC = cia;
3491 temp = State.regs[REG_D0 + DM1];
3492 temp <<= (State.regs[REG_D0 + DN0] & 0x1f);
3493 c = (temp != 0 ? 1 : 0);
3494 PSW &= ~(PSW_C);
3495 PSW |= (c ? PSW_C : 0);
3496 }
3497
3498
3499 // 1111 0000 0010 0000; syscall
3500 8.0xf0+8.0x20:D0:::syscall
3501 "syscall"
3502 *mn10300
3503 {
3504 // OP_F020 ();
3505 PC = cia;
3506 do_syscall ();
3507 }
3508
3509
3510 // 1111 1111; break
3511 8.0xff:S0:::break
3512 "break"
3513 *mn10300
3514 {
3515 // OP_FF ();
3516 PC = cia;
3517 // State.exception = SIGTRAP;
3518 sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
3519 PC -= 1;
3520 }
GDB Binutils - Deliverables
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