bfa88b66e875a7e74b7b0184749155aee32fc579
4 #include "gdb/callback.h"
5 #include "opcode/mn10300.h"
7 #include "gdb/remote-sim.h"
18 extern host_callback
*mn10300_callback
;
19 extern SIM_DESC simulator
;
21 #define DEBUG_TRACE 0x00000001
22 #define DEBUG_VALUES 0x00000002
24 extern int mn10300_debug
;
27 typedef unsigned char uint8
;
28 typedef signed char int8
;
30 #error "Char is not an 8-bit type"
34 typedef unsigned short uint16
;
35 typedef signed short int16
;
37 #error "Short is not a 16-bit type"
40 #if INT_MAX == 2147483647
42 typedef unsigned int uint32
;
43 typedef signed int int32
;
46 # if LONG_MAX == 2147483647
48 typedef unsigned long uint32
;
49 typedef signed long int32
;
52 # error "Neither int nor long is a 32-bit type"
69 /* The current state of the processor; registers, memory, etc. */
73 reg_t regs
[32]; /* registers, d0-d3, a0-a3, sp, pc, mdr, psw,
74 lir, lar, mdrq, plus some room for processor
76 uint8
*mem
; /* main memory */
80 /* All internal state modified by signal_exception() that may need to be
81 rolled back for passing moment-of-exception image back to gdb. */
82 reg_t exc_trigger_regs
[32];
83 reg_t exc_suspend_regs
[32];
86 #define SIM_CPU_EXCEPTION_TRIGGER(SD,CPU,CIA) mn10300_cpu_exception_trigger(SD,CPU,CIA)
87 #define SIM_CPU_EXCEPTION_SUSPEND(SD,CPU,EXC) mn10300_cpu_exception_suspend(SD,CPU,EXC)
88 #define SIM_CPU_EXCEPTION_RESUME(SD,CPU,EXC) mn10300_cpu_exception_resume(SD,CPU,EXC)
91 extern struct _state State
;
93 extern struct simops Simops
[];
95 #define PC (State.regs[REG_PC])
96 #define SP (State.regs[REG_SP])
98 #define PSW (State.regs[11])
103 #define PSW_IE LSBIT (11)
104 #define PSW_LM LSMASK (10, 8)
106 #define EXTRACT_PSW_LM LSEXTRACTED16 (PSW, 10, 8)
107 #define INSERT_PSW_LM(l) LSINSERTED16 ((l), 10, 8)
131 #define FETCH32(a,b,c,d) \
132 ((a)+((b)<<8)+((c)<<16)+((d)<<24))
134 #define FETCH24(a,b,c) \
135 ((a)+((b)<<8)+((c)<<16))
137 #define FETCH16(a,b) ((a)+((b)<<8))
139 #define load_byte(ADDR) \
140 sim_core_read_unaligned_1 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))
142 #define load_half(ADDR) \
143 sim_core_read_unaligned_2 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))
145 #define load_word(ADDR) \
146 sim_core_read_unaligned_4 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))
148 #define store_byte(ADDR, DATA) \
149 sim_core_write_unaligned_1 (STATE_CPU (simulator, 0), \
150 PC, write_map, (ADDR), (DATA))
153 #define store_half(ADDR, DATA) \
154 sim_core_write_unaligned_2 (STATE_CPU (simulator, 0), \
155 PC, write_map, (ADDR), (DATA))
158 #define store_word(ADDR, DATA) \
159 sim_core_write_unaligned_4 (STATE_CPU (simulator, 0), \
160 PC, write_map, (ADDR), (DATA))
162 /* Function declarations. */
164 uint32
get_word (uint8
*);
165 uint16
get_half (uint8
*);
166 uint8
get_byte (uint8
*);
167 void put_word (uint8
*, uint32
);
168 void put_half (uint8
*, uint16
);
169 void put_byte (uint8
*, uint8
);
171 extern uint8
*map (SIM_ADDR addr
);
173 INLINE_SIM_MAIN (void) genericAdd (unsigned32 source
, unsigned32 destReg
);
174 INLINE_SIM_MAIN (void) genericSub (unsigned32 source
, unsigned32 destReg
);
175 INLINE_SIM_MAIN (void) genericCmp (unsigned32 leftOpnd
, unsigned32 rightOpnd
);
176 INLINE_SIM_MAIN (void) genericOr (unsigned32 source
, unsigned32 destReg
);
177 INLINE_SIM_MAIN (void) genericXor (unsigned32 source
, unsigned32 destReg
);
178 INLINE_SIM_MAIN (void) genericBtst (unsigned32 leftOpnd
, unsigned32 rightOpnd
);
179 INLINE_SIM_MAIN (int) syscall_read_mem (host_callback
*cb
,
180 struct cb_syscall
*sc
,
184 INLINE_SIM_MAIN (int) syscall_write_mem (host_callback
*cb
,
185 struct cb_syscall
*sc
,
189 INLINE_SIM_MAIN (void) do_syscall (void);
190 void program_interrupt (SIM_DESC sd
, sim_cpu
*cpu
, sim_cia cia
, SIM_SIGNAL sig
);
192 void mn10300_cpu_exception_trigger(SIM_DESC sd
, sim_cpu
* cpu
, address_word pc
);
193 void mn10300_cpu_exception_suspend(SIM_DESC sd
, sim_cpu
* cpu
, int exception
);
194 void mn10300_cpu_exception_resume(SIM_DESC sd
, sim_cpu
* cpu
, int exception
);
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