sim/or1k/sim-main.h

   1 /* OpenRISC simulator main header
   2    Copyright (C) 2017-2020 Free Software Foundation, Inc.
   3
   4    This file is part of GDB, the GNU debugger.
   5
   6    This program is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3 of the License, or
   9    (at your option) any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  18
  19 #ifndef SIM_MAIN_H
  20 #define SIM_MAIN_H
  21
  22 #define WITH_SCACHE_PBB 1
  23
  24 #include "ansidecl.h"
  25 #include "or1k-desc.h"
  26 #include "sim-basics.h"
  27 #include "cgen-types.h"
  28 #include "arch.h"
  29 #include "sim-base.h"
  30 #include "sim-fpu.h"
  31
  32 #include "or1k-opc.h"
  33 #include "cgen-sim.h"
  34 #include "or1k-sim.h"
  35
  36 #define OR1K_DEFAULT_MEM_SIZE 0x800000  /* 8M */
  37
  38 /* The _sim_cpu struct.  */
  39 struct _sim_cpu
  40 {
  41   /* sim/common cpu base.  */
  42   sim_cpu_base base;
  43
  44   /* Static parts of cgen.  */
  45   CGEN_CPU cgen_cpu;
  46
  47   OR1K_MISC_PROFILE or1k_misc_profile;
  48 #define CPU_OR1K_MISC_PROFILE(cpu) (& (cpu)->or1k_misc_profile)
  49
  50   /* CPU specific parts go here.
  51      Note that in files that don't need to access these pieces WANT_CPU_FOO
  52      won't be defined and thus these parts won't appear.  This is ok in the
  53      sense that things work.  It is a source of bugs though.
  54      One has to of course be careful to not take the size of this
  55      struct and no structure members accessed in non-cpu specific files can
  56      go after here.  Oh for a better language.  */
  57   UWI spr[NUM_SPR];
  58
  59   /* Next instruction will be in delay slot.  */
  60   BI next_delay_slot;
  61   /* Currently in delay slot.  */
  62   BI delay_slot;
  63
  64 #ifdef WANT_CPU_OR1K32BF
  65   OR1K32BF_CPU_DATA cpu_data;
  66 #endif
  67 };
  68
  69 \f
  70
  71 /* The sim_state struct.  */
  72 struct sim_state
  73 {
  74   sim_cpu *cpu[MAX_NR_PROCESSORS];
  75
  76   CGEN_STATE cgen_state;
  77
  78   sim_state_base base;
  79 };
  80
  81 #endif /* SIM_MAIN_H */