1 /* This file is part of the program psim.
3 Copyright (C) 1994-1995, Andrew Cagney <cagney@highland.com.au>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 #ifndef _INTERRUPTS_H_
23 #define _INTERRUPTS_H_
27 The code below handles two different types of interrupts.
28 Synchronous and Asynchronous.
32 Interrupts that must immediately force either an abort or restart
33 of a current instruction are implemented by forcing an instruction
34 restart. (or to put it another way, long jump). In looking at the
35 code it may occure to you that, for some interrupts, they could
36 return instead of restarting the cpu (eg system_call). While true
37 (it once was like that) I've decided to make the behavour of all
38 interrupt routines roughly identical.
40 Because, a cpu's recorded state (ie what is in the cpu structure)
41 is allowed to lag behind the cpu's true current state (eg PC not
42 updated) sycnronous interrupt handers are parameterized with the
43 the cpu being interrupted so that, as part of moddeling the
44 interrupt, the cpu's state can be updated.
48 Interrupts such as reset or external exception are delivered using
49 more normal (returning) functions. It is assumed that these
50 functions are called out side of the normal processor execution
54 /* Software generated interrupts.
56 The below are generated by software driven events. For instance,
57 an invalid instruction or access (virtual or physical) to an
61 direct_store_storage_interrupt
,
62 hash_table_miss_storage_interrupt
,
63 protection_violation_storage_interrupt
,
64 earwax_violation_storage_interrupt
,
65 segment_table_miss_storage_interrupt
,
66 earwax_disabled_storage_interrupt
,
67 vea_storage_interrupt
,
68 } storage_interrupt_reasons
;
72 (void) data_storage_interrupt
76 storage_interrupt_reasons reason
,
80 (void) instruction_storage_interrupt
83 storage_interrupt_reasons reason
);
86 (void) alignment_interrupt
92 floating_point_enabled_program_interrupt
,
93 illegal_instruction_program_interrupt
,
94 privileged_instruction_program_interrupt
,
95 trap_program_interrupt
,
96 optional_instruction_program_interrupt
, /* subset of illegal instruction */
97 #ifdef WITH_OPTION_MPC860C0
98 mpc860c0_instruction_program_interrupt
, /* fwd br, taken but not predicted, near EO page */
99 #endif // WITH_OPTION_MPC860C0
100 nr_program_interrupt_reasons
101 } program_interrupt_reasons
;
104 (void) program_interrupt
107 program_interrupt_reasons reason
);
110 (void) floating_point_unavailable_interrupt
115 (void) system_call_interrupt
120 (void) floating_point_assist_interrupt
125 (void) machine_check_interrupt
129 /* Hardware generated interrupts:
131 These asynchronous hardware generated interrupts may be called at
132 any time. It is the responsibility of this (the interrupts) module
133 to ensure that interrupts are delivered correctly (when possible).
134 The delivery of these interrupts is controlled by the MSR's
135 external interrupt enable bit. When ever the MSR's value is
136 changed, the processor must call the check_masked_interrupts()
137 function in case delivery has been made possible.
139 decrementer_interrupt is `edge' sensitive. Multiple edges arriving
140 before the first edge has been delivered result in only one
143 external_interrupt is `level' sensitive. An external interrupt
144 will only be delivered when the external interrupt port is
145 `asserted'. While interrupts are disabled, the external interrupt
146 can be asserted and then de-asserted without an interrupt
147 eventually being delivered. */
150 external_interrupt_pending
= 1,
151 decrementer_interrupt_pending
= 2,
154 typedef struct _interrupts
{
155 event_entry_tag delivery_scheduled
;
156 int pending_interrupts
;
160 (void) check_masked_interrupts
164 (void) decrementer_interrupt
168 (void) external_interrupt
172 #endif /* _INTERRUPTS_H_ */