sim/ppc/registers.h

   1 /*  This file is part of the program psim.
   2
   3     Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au>
   4
   5     This program is free software; you can redistribute it and/or modify
   6     it under the terms of the GNU General Public License as published by
   7     the Free Software Foundation; either version 2 of the License, or
   8     (at your option) any later version.
   9
  10     This program is distributed in the hope that it will be useful,
  11     but WITHOUT ANY WARRANTY; without even the implied warranty of
  12     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13     GNU General Public License for more details.
  14
  15     You should have received a copy of the GNU General Public License
  16     along with this program; if not, write to the Free Software
  17     Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  18
  19     */
  20
  21
  22 #ifndef _REGISTERS_H_
  23 #define _REGISTERS_H_
  24
  25
  26 /*
  27  * The PowerPC registers
  28  *
  29  */
  30
  31
  32 /**
  33  ** General Purpose Registers
  34  **/
  35
  36 typedef signed_word gpreg;
  37
  38
  39
  40 /**
  41  ** Floating Point Registers
  42  **/
  43
  44 typedef unsigned64 fpreg;
  45
  46
  47
  48 /**
  49  ** The condition register
  50  **
  51  **/
  52
  53 typedef unsigned32 creg;
  54
  55 /* The following sub bits are defined for the condition register */
  56 enum {
  57   cr_i_negative = BIT4(0),
  58   cr_i_positive = BIT4(1),
  59   cr_i_zero = BIT4(2),
  60   cr_i_summary_overflow = BIT4(3),
  61 #if 0
  62   /* cr0 - integer status */
  63   cr0_i_summary_overflow_bit = 3,
  64   cr0_i_negative = BIT32(0),
  65   cr0_i_positive = BIT32(1),
  66   cr0_i_zero = BIT32(2),
  67   cr0_i_summary_overflow = BIT32(3),
  68   cr0_i_mask = MASK32(0,3),
  69 #endif
  70   /* cr1 - floating-point status */
  71   cr1_i_floating_point_exception_summary_bit = 4,
  72   cr1_i_floating_point_enabled_exception_summary_bit = 5,
  73   cr1_i_floating_point_invalid_operation_exception_summary_bit = 6,
  74   cr1_i_floating_point_overflow_exception_bit = 7,
  75   cr1_i_floating_point_exception_summary = BIT32(4),
  76   cr1_i_floating_point_enabled_exception_summary = BIT32(5),
  77   cr1_i_floating_point_invalid_operation_exception_summary = BIT32(6),
  78   cr1_i_floating_point_overflow_exception = BIT32(7),
  79   cr1_i_mask = MASK32(4,7),
  80 };
  81
  82
  83 /* Condition register 1 contains the result of floating point arithmetic */
  84 enum {
  85   cr_fp_exception = BIT4(0),
  86   cr_fp_enabled_exception = BIT4(1),
  87   cr_fp_invalid_exception = BIT4(2),
  88   cr_fp_overflow_exception = BIT4(3),
  89 };
  90
  91
  92
  93 /**
  94  ** Floating-Point Status and Control Register
  95  **/
  96
  97 typedef unsigned32 fpscreg;
  98 enum {
  99   fpscr_fx_bit = 0,
 100   fpscr_fx = BIT32(0),
 101   fpscr_fex_bit = 1,
 102   fpscr_fex = BIT32(1),
 103   fpscr_vx_bit = 2,
 104   fpscr_vx = BIT32(2),
 105   fpscr_ox_bit = 3,
 106   fpscr_ox = BIT32(3),
 107   fpscr_ux = BIT32(4),
 108   fpscr_zx = BIT32(5),
 109   fpscr_xx = BIT32(6),
 110   fpscr_vxsnan = BIT32(7), /* SNAN */
 111   fpscr_vxisi = BIT32(8), /* INF - INF */
 112   fpscr_vxidi = BIT32(9), /* INF / INF */
 113   fpscr_vxzdz = BIT32(10), /* 0 / 0 */
 114   fpscr_vximz = BIT32(11), /* INF * 0 */
 115   fpscr_vxvc = BIT32(12),
 116   fpscr_fr = BIT32(13),
 117   fpscr_fi = BIT32(14),
 118   fpscr_fprf = MASK32(15, 19),
 119   fpscr_c = BIT32(15),
 120   fpscr_fpcc_bit = 16, /* well sort of */
 121   fpscr_fpcc = MASK32(16, 19),
 122   fpscr_fl = BIT32(16),
 123   fpscr_fg = BIT32(17),
 124   fpscr_fe = BIT32(18),
 125   fpscr_fu = BIT32(19),
 126   fpscr_rf_quiet_nan = fpscr_c | fpscr_fu,
 127   fpscr_rf_neg_infinity = fpscr_fl | fpscr_fu,
 128   fpscr_rf_neg_normal_number = fpscr_fl,
 129   fpscr_rf_neg_denormalized_number = fpscr_c | fpscr_fl,
 130   fpscr_rf_neg_zero = fpscr_c | fpscr_fe,
 131   fpscr_rf_pos_zero = fpscr_fe,
 132   fpscr_rf_pos_denormalized_number = fpscr_c | fpscr_fg,
 133   fpscr_rf_pos_normal_number = fpscr_fg,
 134   fpscr_rf_pos_infinity = fpscr_fg | fpscr_fu,
 135   fpscr_reserved_20 = BIT32(20),
 136   fpscr_vxsoft = BIT32(21),
 137   fpscr_vxsqrt = BIT32(22),
 138   fpscr_vxcvi = BIT32(23),
 139   fpscr_ve = BIT32(24),
 140   fpscr_oe = BIT32(25),
 141   fpscr_ue = BIT32(26),
 142   fpscr_ze = BIT32(27),
 143   fpscr_xe = BIT32(28),
 144   fpscr_ni = BIT32(29),
 145   fpscr_rn = MASK32(30, 31),
 146   fpscr_rn_round_to_nearest = 0,
 147   fpscr_rn_round_towards_zero = MASK32(31,31),
 148   fpscr_rn_round_towards_pos_infinity = MASK32(30,30),
 149   fpscr_rn_round_towards_neg_infinity = MASK32(30,31),
 150   fpscr_vx_bits = (fpscr_vxsnan | fpscr_vxisi | fpscr_vxidi
 151                    | fpscr_vxzdz | fpscr_vximz | fpscr_vxvc
 152                    | fpscr_vxsoft | fpscr_vxsqrt | fpscr_vxcvi),
 153 };
 154
 155
 156
 157 /**
 158  ** XER Register
 159  **/
 160
 161 typedef unsigned32 xereg;
 162
 163 enum {
 164   xer_summary_overflow = BIT32(0), xer_summary_overflow_bit = 0,
 165   xer_carry = BIT32(2), xer_carry_bit = 2,
 166   xer_overflow = BIT32(1),
 167   xer_reserved_3_24 = MASK32(3,24),
 168   xer_byte_count_mask = MASK32(25,31)
 169 };
 170
 171
 172 /**
 173  ** SPR's
 174  **/
 175
 176 #include "spreg.h"
 177
 178
 179 /**
 180  ** Segment Registers
 181  **/
 182
 183 typedef unsigned32 sreg;
 184 enum {
 185   nr_of_srs = 16
 186 };
 187
 188
 189 /**
 190  ** Machine state register
 191  **/
 192 typedef unsigned_word msreg; /* 32 or 64 bits */
 193
 194 enum {
 195 #if (WITH_TARGET_WORD_BITSIZE == 64)
 196   msr_64bit_mode = BIT(0),
 197 #endif
 198 #if (WITH_TARGET_WORD_BITSIZE == 32)
 199   msr_64bit_mode = 0,
 200 #endif
 201   msr_power_management_enable = BIT(45),
 202   msr_tempoary_gpr_remapping = BIT(46), /* 603 specific */
 203   msr_interrupt_little_endian_mode = BIT(47),
 204   msr_external_interrupt_enable = BIT(48),
 205   msr_problem_state = BIT(49),
 206   msr_floating_point_available = BIT(50),
 207   msr_machine_check_enable = BIT(51),
 208   msr_floating_point_exception_mode_0 = BIT(52),
 209   msr_single_step_trace_enable = BIT(53),
 210   msr_branch_trace_enable = BIT(54),
 211   msr_floating_point_exception_mode_1 = BIT(55),
 212   msr_interrupt_prefix = BIT(57),
 213   msr_instruction_relocate = BIT(58),
 214   msr_data_relocate = BIT(59),
 215   msr_recoverable_interrupt = BIT(62),
 216   msr_little_endian_mode = BIT(63)
 217 };
 218
 219 enum {
 220   srr1_hash_table_or_ibat_miss = BIT(33),
 221   srr1_direct_store_error_exception = BIT(35),
 222   srr1_protection_violation = BIT(36),
 223   srr1_segment_table_miss = BIT(42),
 224   srr1_floating_point_enabled = BIT(43),
 225   srr1_illegal_instruction = BIT(44),
 226   srr1_priviliged_instruction = BIT(45),
 227   srr1_trap = BIT(46),
 228   srr1_subsequent_instruction = BIT(47)
 229 };
 230
 231
 232 /**
 233  ** storage interrupt registers
 234  **/
 235
 236 typedef enum {
 237   dsisr_direct_store_error_exception = BIT32(0),
 238   dsisr_hash_table_or_dbat_miss = BIT32(1),
 239   dsisr_protection_violation = BIT32(4),
 240   dsisr_earwax_violation = BIT32(5),
 241   dsisr_store_operation = BIT32(6),
 242   dsisr_segment_table_miss = BIT32(10),
 243   dsisr_earwax_disabled = BIT32(11)
 244 } dsisr_status;
 245
 246
 247
 248 /**
 249  ** And the registers proper
 250  **/
 251 typedef struct _registers {
 252
 253   gpreg gpr[32];
 254   fpreg fpr[32];
 255   creg cr;
 256   fpscreg fpscr;
 257
 258   /* Machine state register */
 259   msreg msr;
 260
 261   /* Spr's */
 262   spreg spr[nr_of_sprs];
 263
 264   /* Segment Registers */
 265   sreg sr[nr_of_srs];
 266
 267 } registers;
 268
 269
 270 /* dump out all the registers */
 271
 272 INLINE_REGISTERS\
 273 (void) registers_dump
 274 (registers *regs);
 275
 276
 277 /* return information on a register based on name */
 278
 279 typedef enum {
 280   reg_invalid,
 281   reg_gpr, reg_fpr, reg_spr, reg_msr,
 282   reg_cr, reg_fpscr, reg_pc, reg_sr,
 283   reg_insns, reg_stalls, reg_cycles,
 284   nr_register_types
 285 } register_types;
 286
 287 typedef struct {
 288   register_types type;
 289   int index;
 290   int size;
 291 } register_descriptions;
 292
 293 INLINE_REGISTERS\
 294 (register_descriptions) register_description
 295 (const char reg[]);
 296
 297
 298 /* Special purpose registers by their more common names */
 299
 300 #define SPREG(N)        cpu_registers(processor)->spr[N]
 301 #define XER             SPREG(spr_xer)
 302 #define LR              SPREG(spr_lr)
 303 #define CTR             SPREG(spr_ctr)
 304 #define SRR0            SPREG(spr_srr0)
 305 #define SRR1            SPREG(spr_srr1)
 306 #define DAR             SPREG(spr_dar)
 307 #define DSISR           SPREG(spr_dsisr)
 308
 309 /* general purpose registers - indexed access */
 310 #define GPR(N)          cpu_registers(processor)->gpr[N]
 311
 312 /* segment registers */
 313 #define SEGREG(N)       cpu_registers(processor)->sr[N]
 314
 315 /* condition register */
 316 #define CR              cpu_registers(processor)->cr
 317
 318 /* machine status register */
 319 #define MSR             cpu_registers(processor)->msr
 320
 321 /* floating-point status condition register */
 322 #define FPSCR           cpu_registers(processor)->fpscr
 323
 324 #endif /* _REGISTERS_H_ */