1 /* Simulator for the Texas Instruments PRU processor
2 Copyright 2009-2019 Free Software Foundation, Inc.
3 Inspired by the Microblaze simulator
4 Contributed by Dimitar Dimitrov <dimitar@dinux.eu>
6 This file is part of the simulators.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, see <http://www.gnu.org/licenses/>. */
26 #include "gdb/callback.h"
27 #include "libiberty.h"
28 #include "gdb/remote-sim.h"
30 #include "sim-assert.h"
31 #include "sim-options.h"
32 #include "sim-syscall.h"
35 /* DMEM zero address is perfectly valid. But if CRT leaves the first word
36 alone, we can use it as a trap to catch NULL pointer access. */
37 static bfd_boolean abort_on_dmem_zero_access
;
40 OPTION_ERROR_NULL_DEREF
= OPTION_START
,
43 /* Extract (from PRU endianess) and return an integer in HOST's endianness. */
45 pru_extract_unsigned_integer (uint8_t *addr
, size_t len
)
49 uint8_t *startaddr
= addr
;
50 uint8_t *endaddr
= startaddr
+ len
;
52 /* Start at the most significant end of the integer, and work towards
53 the least significant. */
56 for (p
= endaddr
; p
> startaddr
;)
57 retval
= (retval
<< 8) | * -- p
;
61 /* Store "val" (which is in HOST's endianess) into "addr"
62 (using PRU's endianness). */
64 pru_store_unsigned_integer (uint8_t *addr
, size_t len
, uint32_t val
)
67 uint8_t *startaddr
= (uint8_t *)addr
;
68 uint8_t *endaddr
= startaddr
+ len
;
70 for (p
= startaddr
; p
< endaddr
;)
77 /* Extract a field value from CPU register using the given REGSEL selector.
79 Byte number maps directly to first values of RSEL, so we can
80 safely use "regsel" as a register byte number (0..3). */
81 static inline uint32_t
82 extract_regval (uint32_t val
, uint32_t regsel
)
84 ASSERT (RSEL_7_0
== 0);
85 ASSERT (RSEL_15_8
== 1);
86 ASSERT (RSEL_23_16
== 2);
87 ASSERT (RSEL_31_24
== 3);
91 case RSEL_7_0
: return (val
>> 0) & 0xff;
92 case RSEL_15_8
: return (val
>> 8) & 0xff;
93 case RSEL_23_16
: return (val
>> 16) & 0xff;
94 case RSEL_31_24
: return (val
>> 24) & 0xff;
95 case RSEL_15_0
: return (val
>> 0) & 0xffff;
96 case RSEL_23_8
: return (val
>> 8) & 0xffff;
97 case RSEL_31_16
: return (val
>> 16) & 0xffff;
98 case RSEL_31_0
: return val
;
99 default: sim_io_error (NULL
, "invalid regsel");
103 /* Write a value into CPU subregister pointed by reg and regsel. */
105 write_regval (uint32_t val
, uint32_t *reg
, uint32_t regsel
)
111 case RSEL_7_0
: mask
= (0xffu
<< 0); sh
= 0; break;
112 case RSEL_15_8
: mask
= (0xffu
<< 8); sh
= 8; break;
113 case RSEL_23_16
: mask
= (0xffu
<< 16); sh
= 16; break;
114 case RSEL_31_24
: mask
= (0xffu
<< 24); sh
= 24; break;
115 case RSEL_15_0
: mask
= (0xffffu
<< 0); sh
= 0; break;
116 case RSEL_23_8
: mask
= (0xffffu
<< 8); sh
= 8; break;
117 case RSEL_31_16
: mask
= (0xffffu
<< 16); sh
= 16; break;
118 case RSEL_31_0
: mask
= 0xffffffffu
; sh
= 0; break;
119 default: sim_io_error (NULL
, "invalid regsel");
122 *reg
= (*reg
& ~mask
) | ((val
<< sh
) & mask
);
125 /* Convert the given IMEM word address to a regular byte address used by the
126 GNU ELF container. */
128 imem_wordaddr_to_byteaddr (SIM_CPU
*cpu
, uint16_t wa
)
130 return (((uint32_t) wa
<< 2) & IMEM_ADDR_MASK
) | PC_ADDR_SPACE_MARKER
;
133 /* Convert the given ELF text byte address to IMEM word address. */
135 imem_byteaddr_to_wordaddr (SIM_CPU
*cpu
, uint32_t ba
)
137 return (ba
>> 2) & 0xffff;
141 /* Store "nbytes" into DMEM "addr" from CPU register file, starting with
142 register "regn", and byte "regb" within it. */
144 pru_reg2dmem (SIM_CPU
*cpu
, uint32_t addr
, unsigned int nbytes
,
147 /* GDB assumes unconditional access to all memories, so enable additional
148 checks only in standalone mode. */
149 bool standalone
= (STATE_OPEN_KIND (CPU_STATE (cpu
)) == SIM_OPEN_STANDALONE
);
151 if (abort_on_dmem_zero_access
&& addr
< 4)
153 sim_core_signal (CPU_STATE (cpu
), cpu
, PC_byteaddr
, write_map
,
154 nbytes
, addr
, write_transfer
,
155 sim_core_unmapped_signal
);
157 else if (standalone
&& ((addr
>= PC_ADDR_SPACE_MARKER
)
158 || (addr
+ nbytes
> PC_ADDR_SPACE_MARKER
)))
160 sim_core_signal (CPU_STATE (cpu
), cpu
, PC_byteaddr
, write_map
,
161 nbytes
, addr
, write_transfer
,
162 sim_core_unmapped_signal
);
164 else if ((regn
* 4 + regb
+ nbytes
) > (32 * 4))
166 sim_io_eprintf (CPU_STATE (cpu
),
167 "SBBO/SBCO with invalid store data length\n");
168 RAISE_SIGILL (CPU_STATE (cpu
));
172 TRACE_MEMORY (cpu
, "write of %d bytes to %08x", nbytes
, addr
);
175 sim_core_write_1 (cpu
,
179 extract_regval (CPU
.regs
[regn
], regb
));
190 /* Load "nbytes" from DMEM "addr" into CPU register file, starting with
191 register "regn", and byte "regb" within it. */
193 pru_dmem2reg (SIM_CPU
*cpu
, uint32_t addr
, unsigned int nbytes
,
196 /* GDB assumes unconditional access to all memories, so enable additional
197 checks only in standalone mode. */
198 bool standalone
= (STATE_OPEN_KIND (CPU_STATE (cpu
)) == SIM_OPEN_STANDALONE
);
200 if (abort_on_dmem_zero_access
&& addr
< 4)
202 sim_core_signal (CPU_STATE (cpu
), cpu
, PC_byteaddr
, read_map
,
203 nbytes
, addr
, read_transfer
,
204 sim_core_unmapped_signal
);
206 else if (standalone
&& ((addr
>= PC_ADDR_SPACE_MARKER
)
207 || (addr
+ nbytes
> PC_ADDR_SPACE_MARKER
)))
209 /* This check is necessary because our IMEM "address space"
210 is not really accessible, yet we have mapped it as a generic
212 sim_core_signal (CPU_STATE (cpu
), cpu
, PC_byteaddr
, read_map
,
213 nbytes
, addr
, read_transfer
,
214 sim_core_unmapped_signal
);
216 else if ((regn
* 4 + regb
+ nbytes
) > (32 * 4))
218 sim_io_eprintf (CPU_STATE (cpu
),
219 "LBBO/LBCO with invalid load data length\n");
220 RAISE_SIGILL (CPU_STATE (cpu
));
225 TRACE_MEMORY (cpu
, "read of %d bytes from %08x", nbytes
, addr
);
228 b
= sim_core_read_1 (cpu
, PC_byteaddr
, read_map
, addr
++);
230 /* Reuse the fact the Register Byte Number maps directly to RSEL. */
231 ASSERT (RSEL_7_0
== 0);
232 write_regval (b
, &CPU
.regs
[regn
], regb
);
243 /* Set reset values of general-purpose registers. */
245 set_initial_gprs (SIM_CPU
*cpu
)
249 /* Set up machine just out of reset. */
251 PC_ADDR_SPACE_MARKER
= IMEM_ADDR_DEFAULT
; /* from default linker script? */
253 /* Clean out the GPRs. */
254 for (i
= 0; i
< ARRAY_SIZE (CPU
.regs
); i
++)
256 for (i
= 0; i
< ARRAY_SIZE (CPU
.macregs
); i
++)
259 CPU
.loop
.looptop
= CPU
.loop
.loopend
= 0;
260 CPU
.loop
.loop_in_progress
= 0;
261 CPU
.loop
.loop_counter
= 0;
267 /* AM335x should provide sane defaults. */
268 CPU
.ctable
[0] = 0x00020000;
269 CPU
.ctable
[1] = 0x48040000;
270 CPU
.ctable
[2] = 0x4802a000;
271 CPU
.ctable
[3] = 0x00030000;
272 CPU
.ctable
[4] = 0x00026000;
273 CPU
.ctable
[5] = 0x48060000;
274 CPU
.ctable
[6] = 0x48030000;
275 CPU
.ctable
[7] = 0x00028000;
276 CPU
.ctable
[8] = 0x46000000;
277 CPU
.ctable
[9] = 0x4a100000;
278 CPU
.ctable
[10] = 0x48318000;
279 CPU
.ctable
[11] = 0x48022000;
280 CPU
.ctable
[12] = 0x48024000;
281 CPU
.ctable
[13] = 0x48310000;
282 CPU
.ctable
[14] = 0x481cc000;
283 CPU
.ctable
[15] = 0x481d0000;
284 CPU
.ctable
[16] = 0x481a0000;
285 CPU
.ctable
[17] = 0x4819c000;
286 CPU
.ctable
[18] = 0x48300000;
287 CPU
.ctable
[19] = 0x48302000;
288 CPU
.ctable
[20] = 0x48304000;
289 CPU
.ctable
[21] = 0x00032400;
290 CPU
.ctable
[22] = 0x480c8000;
291 CPU
.ctable
[23] = 0x480ca000;
292 CPU
.ctable
[24] = 0x00000000;
293 CPU
.ctable
[25] = 0x00002000;
294 CPU
.ctable
[26] = 0x0002e000;
295 CPU
.ctable
[27] = 0x00032000;
296 CPU
.ctable
[28] = 0x00000000;
297 CPU
.ctable
[29] = 0x49000000;
298 CPU
.ctable
[30] = 0x40000000;
299 CPU
.ctable
[31] = 0x80000000;
302 /* Map regsel selector to subregister field width. */
303 static inline unsigned int
304 regsel_width (uint32_t regsel
)
308 case RSEL_7_0
: return 8;
309 case RSEL_15_8
: return 8;
310 case RSEL_23_16
: return 8;
311 case RSEL_31_24
: return 8;
312 case RSEL_15_0
: return 16;
313 case RSEL_23_8
: return 16;
314 case RSEL_31_16
: return 16;
315 case RSEL_31_0
: return 32;
316 default: sim_io_error (NULL
, "invalid regsel");
320 /* Handle XIN instruction addressing the MAC peripheral. */
322 pru_sim_xin_mac (SIM_DESC sd
, SIM_CPU
*cpu
, unsigned int rd_regn
,
323 unsigned int rdb
, unsigned int length
)
325 if (rd_regn
< 25 || (rd_regn
* 4 + rdb
+ length
) > (27 + 1) * 4)
326 sim_io_error (sd
, "XIN MAC: invalid transfer regn=%u.%u, length=%u\n",
327 rd_regn
, rdb
, length
);
329 /* Copy from MAC to PRU regs. Ranges have been validated above. */
332 write_regval (CPU
.macregs
[rd_regn
- 25] >> (rdb
* 8),
343 /* Handle XIN instruction. */
345 pru_sim_xin (SIM_DESC sd
, SIM_CPU
*cpu
, unsigned int wba
,
346 unsigned int rd_regn
, unsigned int rdb
, unsigned int length
)
350 pru_sim_xin_mac (sd
, cpu
, rd_regn
, rdb
, length
);
352 else if (wba
== XFRID_SCRATCH_BANK_0
|| wba
== XFRID_SCRATCH_BANK_1
353 || wba
== XFRID_SCRATCH_BANK_2
|| wba
== XFRID_SCRATCH_BANK_PEER
)
359 val
= extract_regval (CPU
.scratchpads
[wba
][rd_regn
], rdb
);
360 write_regval (val
, &CPU
.regs
[rd_regn
], rdb
);
368 else if (wba
== 254 || wba
== 255)
370 /* FILL/ZERO pseudos implemented via XIN. */
371 unsigned int fillbyte
= (wba
== 254) ? 0xff : 0x00;
374 write_regval (fillbyte
, &CPU
.regs
[rd_regn
], rdb
);
384 sim_io_error (sd
, "XIN: XFR device %d not supported.\n", wba
);
388 /* Handle XOUT instruction addressing the MAC peripheral. */
390 pru_sim_xout_mac (SIM_DESC sd
, SIM_CPU
*cpu
, unsigned int rd_regn
,
391 unsigned int rdb
, unsigned int length
)
393 const int modereg_accessed
= (rd_regn
== 25);
395 /* Multiple Accumulate. */
396 if (rd_regn
< 25 || (rd_regn
* 4 + rdb
+ length
) > (27 + 1) * 4)
397 sim_io_error (sd
, "XOUT MAC: invalid transfer regn=%u.%u, length=%u\n",
398 rd_regn
, rdb
, length
);
400 /* Copy from PRU to MAC regs. Ranges have been validated above. */
403 write_regval (CPU
.regs
[rd_regn
] >> (rdb
* 8),
404 &CPU
.macregs
[rd_regn
- 25],
414 && (CPU
.macregs
[PRU_MACREG_MODE
] & MAC_R25_MAC_MODE_MASK
))
416 /* MUL/MAC operands are sampled every XOUT in multiply and
418 uint64_t prod
, oldsum
, sum
;
419 CPU
.macregs
[PRU_MACREG_OP_0
] = CPU
.regs
[28];
420 CPU
.macregs
[PRU_MACREG_OP_1
] = CPU
.regs
[29];
422 prod
= CPU
.macregs
[PRU_MACREG_OP_0
];
423 prod
*= (uint64_t)CPU
.macregs
[PRU_MACREG_OP_1
];
425 oldsum
= CPU
.macregs
[PRU_MACREG_ACC_L
];
426 oldsum
+= (uint64_t)CPU
.macregs
[PRU_MACREG_ACC_H
] << 32;
429 CPU
.macregs
[PRU_MACREG_PROD_L
] = sum
& 0xfffffffful
;
430 CPU
.macregs
[PRU_MACREG_PROD_H
] = sum
>> 32;
431 CPU
.macregs
[PRU_MACREG_ACC_L
] = CPU
.macregs
[PRU_MACREG_PROD_L
];
432 CPU
.macregs
[PRU_MACREG_ACC_H
] = CPU
.macregs
[PRU_MACREG_PROD_H
];
435 CPU
.macregs
[PRU_MACREG_MODE
] |= MAC_R25_ACC_CARRY_MASK
;
438 && (CPU
.macregs
[PRU_MACREG_MODE
] & MAC_R25_ACC_CARRY_MASK
))
440 /* store 1 to clear. */
441 CPU
.macregs
[PRU_MACREG_MODE
] &= ~MAC_R25_ACC_CARRY_MASK
;
442 CPU
.macregs
[PRU_MACREG_ACC_L
] = 0;
443 CPU
.macregs
[PRU_MACREG_ACC_H
] = 0;
448 /* Handle XOUT instruction. */
450 pru_sim_xout (SIM_DESC sd
, SIM_CPU
*cpu
, unsigned int wba
,
451 unsigned int rd_regn
, unsigned int rdb
, unsigned int length
)
455 pru_sim_xout_mac (sd
, cpu
, rd_regn
, rdb
, length
);
457 else if (wba
== XFRID_SCRATCH_BANK_0
|| wba
== XFRID_SCRATCH_BANK_1
458 || wba
== XFRID_SCRATCH_BANK_2
|| wba
== XFRID_SCRATCH_BANK_PEER
)
464 val
= extract_regval (CPU
.regs
[rd_regn
], rdb
);
465 write_regval (val
, &CPU
.scratchpads
[wba
][rd_regn
], rdb
);
474 sim_io_error (sd
, "XOUT: XFR device %d not supported.\n", wba
);
477 /* Handle XCHG instruction. */
479 pru_sim_xchg (SIM_DESC sd
, SIM_CPU
*cpu
, unsigned int wba
,
480 unsigned int rd_regn
, unsigned int rdb
, unsigned int length
)
482 if (wba
== XFRID_SCRATCH_BANK_0
|| wba
== XFRID_SCRATCH_BANK_1
483 || wba
== XFRID_SCRATCH_BANK_2
|| wba
== XFRID_SCRATCH_BANK_PEER
)
487 unsigned int valr
, vals
;
489 valr
= extract_regval (CPU
.regs
[rd_regn
], rdb
);
490 vals
= extract_regval (CPU
.scratchpads
[wba
][rd_regn
], rdb
);
491 write_regval (valr
, &CPU
.scratchpads
[wba
][rd_regn
], rdb
);
492 write_regval (vals
, &CPU
.regs
[rd_regn
], rdb
);
501 sim_io_error (sd
, "XOUT: XFR device %d not supported.\n", wba
);
504 /* Handle syscall simulation. Its ABI is specific to the GNU simulator. */
506 pru_sim_syscall (SIM_DESC sd
, SIM_CPU
*cpu
)
508 /* If someday TI confirms that the "reserved" HALT opcode fields
509 can be used for extra arguments, then maybe we can embed
510 the syscall number there. Until then, let's use R1. */
511 const uint32_t syscall_num
= CPU
.regs
[1];
514 ret
= sim_syscall (cpu
, syscall_num
,
515 CPU
.regs
[14], CPU
.regs
[15],
516 CPU
.regs
[16], CPU
.regs
[17]);
520 /* Simulate one instruction. */
522 sim_step_once (SIM_DESC sd
)
524 SIM_CPU
*cpu
= STATE_CPU (sd
, 0);
525 const struct pru_opcode
*op
;
527 uint32_t _RDVAL
, OP2
; /* intermediate values. */
528 int rd_is_modified
= 0; /* RD modified and must be stored back. */
530 /* Fetch the initial instruction that we'll decode. */
531 inst
= sim_core_read_4 (cpu
, PC_byteaddr
, exec_map
, PC_byteaddr
);
532 TRACE_MEMORY (cpu
, "read of insn 0x%08x from %08x", inst
, PC_byteaddr
);
534 op
= pru_find_opcode (inst
);
538 sim_io_eprintf (sd
, "Unknown instruction 0x%04x\n", inst
);
543 TRACE_DISASM (cpu
, PC_byteaddr
);
545 /* In multiply-only mode, R28/R29 operands are sampled on every clock
547 if ((CPU
.macregs
[PRU_MACREG_MODE
] & MAC_R25_MAC_MODE_MASK
) == 0)
549 CPU
.macregs
[PRU_MACREG_OP_0
] = CPU
.regs
[28];
550 CPU
.macregs
[PRU_MACREG_OP_1
] = CPU
.regs
[29];
555 /* Helper macro to improve clarity of pru.isa. The empty while is a
556 guard against using RD as a left-hand side value. */
557 #define RD do { } while (0); rd_is_modified = 1; _RDVAL
558 #define INSTRUCTION(NAME, ACTION) \
559 case prui_ ## NAME: \
571 write_regval (_RDVAL
, &CPU
.regs
[RD_REGN
], RDSEL
);
573 /* Don't treat r30 and r31 as regular registers, they are I/O! */
577 /* Handle PC match of loop end. */
578 if (LOOP_IN_PROGRESS
&& (PC
== LOOPEND
))
580 SIM_ASSERT (LOOPCNT
> 0);
582 LOOP_IN_PROGRESS
= 0;
587 /* In multiply-only mode, MAC does multiplication every cycle. */
588 if ((CPU
.macregs
[PRU_MACREG_MODE
] & MAC_R25_MAC_MODE_MASK
) == 0)
591 prod
= CPU
.macregs
[PRU_MACREG_OP_0
];
592 prod
*= (uint64_t)CPU
.macregs
[PRU_MACREG_OP_1
];
593 CPU
.macregs
[PRU_MACREG_PROD_L
] = prod
& 0xfffffffful
;
594 CPU
.macregs
[PRU_MACREG_PROD_H
] = prod
>> 32;
596 /* Clear the MAC accumulator when in normal mode. */
597 CPU
.macregs
[PRU_MACREG_ACC_L
] = 0;
598 CPU
.macregs
[PRU_MACREG_ACC_H
] = 0;
601 /* Update cycle counts. */
602 CPU
.insts
+= 1; /* One instruction completed ... */
603 CPU
.cycles
+= 1; /* ... and it takes a single cycle. */
605 /* Account for memory access latency with a reasonable estimate.
606 No distinction is currently made between SRAM, DRAM and generic
608 if (op
->type
== prui_lbbo
|| op
->type
== prui_sbbo
609 || op
->type
== prui_lbco
|| op
->type
== prui_sbco
)
615 /* Implement standard sim_engine_run function. */
617 sim_engine_run (SIM_DESC sd
,
618 int next_cpu_nr
, /* ignore */
619 int nr_cpus
, /* ignore */
620 int siggnal
) /* ignore */
625 if (sim_events_tick (sd
))
626 sim_events_process (sd
);
631 /* Implement callback for standard CPU_PC_FETCH routine. */
633 pru_pc_get (sim_cpu
*cpu
)
635 /* Present PC as byte address. */
636 return imem_wordaddr_to_byteaddr (cpu
, cpu
->pru_cpu
.pc
);
639 /* Implement callback for standard CPU_PC_STORE routine. */
641 pru_pc_set (sim_cpu
*cpu
, sim_cia pc
)
643 /* PC given as byte address. */
644 cpu
->pru_cpu
.pc
= imem_byteaddr_to_wordaddr (cpu
, pc
);
648 /* Implement callback for standard CPU_REG_STORE routine. */
650 pru_store_register (SIM_CPU
*cpu
, int rn
, unsigned char *memory
, int length
)
652 if (rn
< NUM_REGS
&& rn
>= 0)
656 /* Misalignment safe. */
657 long ival
= pru_extract_unsigned_integer (memory
, 4);
661 pru_pc_set (cpu
, ival
);
671 /* Implement callback for standard CPU_REG_FETCH routine. */
673 pru_fetch_register (SIM_CPU
*cpu
, int rn
, unsigned char *memory
, int length
)
677 if (rn
< NUM_REGS
&& rn
>= 0)
684 ival
= pru_pc_get (cpu
);
686 /* Misalignment-safe. */
687 pru_store_unsigned_integer (memory
, 4, ival
);
698 free_state (SIM_DESC sd
)
700 if (STATE_MODULES (sd
) != NULL
)
701 sim_module_uninstall (sd
);
702 sim_cpu_free_all (sd
);
706 /* Declare the PRU option handler. */
707 static DECLARE_OPTION_HANDLER (pru_option_handler
);
709 /* Implement the PRU option handler. */
711 pru_option_handler (SIM_DESC sd
, sim_cpu
*cpu
, int opt
, char *arg
,
716 case OPTION_ERROR_NULL_DEREF
:
717 abort_on_dmem_zero_access
= TRUE
;
721 sim_io_eprintf (sd
, "Unknown PRU option %d\n", opt
);
726 /* List of PRU-specific options. */
727 static const OPTION pru_options
[] =
729 { {"error-null-deref", no_argument
, NULL
, OPTION_ERROR_NULL_DEREF
},
730 '\0', NULL
, "Trap any access to DMEM address zero",
731 pru_option_handler
, NULL
},
733 { {NULL
, no_argument
, NULL
, 0}, '\0', NULL
, NULL
, NULL
, NULL
}
736 /* Implement standard sim_open function. */
738 sim_open (SIM_OPEN_KIND kind
, host_callback
*cb
,
739 struct bfd
*abfd
, char * const *argv
)
743 SIM_DESC sd
= sim_state_alloc (kind
, cb
);
744 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
746 /* The cpu data is kept in a separately allocated chunk of memory. */
747 if (sim_cpu_alloc_all (sd
, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK
)
753 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
758 sim_add_option_table (sd
, NULL
, pru_options
);
760 /* The parser will print an error message for us, so we silently return. */
761 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
767 /* Check for/establish a reference program image. */
768 if (sim_analyze_program (sd
,
769 (STATE_PROG_ARGV (sd
) != NULL
770 ? *STATE_PROG_ARGV (sd
)
771 : NULL
), abfd
) != SIM_RC_OK
)
777 /* Configure/verify the target byte order and other runtime
778 configuration options. */
779 if (sim_config (sd
) != SIM_RC_OK
)
781 sim_module_uninstall (sd
);
785 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
787 /* Uninstall the modules to avoid memory leaks,
788 file descriptor leaks, etc. */
789 sim_module_uninstall (sd
);
793 /* CPU specific initialization. */
794 for (i
= 0; i
< MAX_NR_PROCESSORS
; ++i
)
796 SIM_CPU
*cpu
= STATE_CPU (sd
, i
);
798 CPU_REG_STORE (cpu
) = pru_store_register
;
799 CPU_REG_FETCH (cpu
) = pru_fetch_register
;
800 CPU_PC_FETCH (cpu
) = pru_pc_get
;
801 CPU_PC_STORE (cpu
) = pru_pc_set
;
803 set_initial_gprs (cpu
);
806 /* Allocate external memory if none specified by user.
807 Use address 4 here in case the user wanted address 0 unmapped. */
808 if (sim_core_read_buffer (sd
, NULL
, read_map
, &c
, 4, 1) == 0)
810 sim_do_commandf (sd
, "memory-region 0x%x,0x%x",
814 if (sim_core_read_buffer (sd
, NULL
, read_map
, &c
, IMEM_ADDR_DEFAULT
, 1) == 0)
816 sim_do_commandf (sd
, "memory-region 0x%x,0x%x",
824 /* Implement standard sim_create_inferior function. */
826 sim_create_inferior (SIM_DESC sd
, struct bfd
*prog_bfd
,
827 char * const *argv
, char * const *env
)
829 SIM_CPU
*cpu
= STATE_CPU (sd
, 0);
832 addr
= bfd_get_start_address (prog_bfd
);
834 sim_pc_set (cpu
, addr
);
835 PC_ADDR_SPACE_MARKER
= addr
& ~IMEM_ADDR_MASK
;
837 /* Standalone mode (i.e. `run`) will take care of the argv for us in
838 sim_open () -> sim_parse_args (). But in debug mode (i.e. 'target sim'
839 with `gdb`), we need to handle it because the user can change the
840 argv on the fly via gdb's 'run'. */
841 if (STATE_PROG_ARGV (sd
) != argv
)
843 freeargv (STATE_PROG_ARGV (sd
));
844 STATE_PROG_ARGV (sd
) = dupargv (argv
);