1 /* Simulator for the Renesas (formerly Hitachi) / SuperH Inc. SH architecture.
3 Written by Steve Chamberlain of Cygnus Support.
6 This file is part of SH sim
9 THIS SOFTWARE IS NOT COPYRIGHTED
11 Cygnus offers the following for use in the public domain. Cygnus
12 makes no warranty with regard to the software or it's performance
13 and the user accepts the software "AS IS" with all faults.
15 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
16 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
32 # define MAP_FAILED -1
34 # if !defined (MAP_ANONYMOUS) && defined (MAP_ANON)
35 # define MAP_ANONYMOUS MAP_ANON
51 #ifdef HAVE_SYS_STAT_H
56 #include "gdb/callback.h"
57 #include "gdb/remote-sim.h"
58 #include "gdb/sim-sh.h"
60 /* This file is local - if newlib changes, then so should this. */
66 #include <float.h> /* Needed for _isnan() */
71 #define SIGBUS SIGSEGV
75 #define SIGQUIT SIGTERM
82 extern unsigned short sh_jump_table
[], sh_dsp_table
[0x1000], ppi_table
[];
84 int sim_write (SIM_DESC sd
, SIM_ADDR addr
, const unsigned char *buffer
, int size
);
86 #define O_RECOMPILE 85
88 #define DISASSEMBLER_TABLE
90 /* Define the rate at which the simulator should poll the host
92 #define POLL_QUIT_INTERVAL 0x60000
107 /* System registers. For sh-dsp this also includes A0 / X0 / X1 / Y0 / Y1
108 which are located in fregs, i.e. strictly speaking, these are
109 out-of-bounds accesses of sregs.i . This wart of the code could be
110 fixed by making fregs part of sregs, and including pc too - to avoid
111 alignment repercussions - but this would cause very onerous union /
112 structure nesting, which would only be managable with anonymous
113 unions and structs. */
122 int fpul
; /* A1 for sh-dsp - but only for movs etc. */
123 int fpscr
; /* dsr for sh-dsp */
137 /* Control registers; on the SH4, ldc / stc is privileged, except when
154 int dbr
; /* debug base register */
155 int sgr
; /* saved gr15 */
156 int ldst
; /* load/store flag (boolean) */
158 int ibcr
; /* sh2a bank control register */
159 int ibnr
; /* sh2a bank number register */
164 unsigned char *insn_end
;
176 int end_of_registers
;
179 #define PROFILE_FREQ 1
180 #define PROFILE_SHIFT 2
182 unsigned short *profile_hist
;
183 unsigned char *memory
;
184 int xyram_select
, xram_start
, yram_start
;
187 unsigned char *xmem_offset
;
188 unsigned char *ymem_offset
;
189 unsigned long bfd_mach
;
190 regstacktype
*regstack
;
196 saved_state_type saved_state
;
198 struct loop_bounds
{ unsigned char *start
, *end
; };
200 /* These variables are at file scope so that functions other than
201 sim_resume can use the fetch/store macros */
203 static int target_little_endian
;
204 static int global_endianw
, endianb
;
205 static int target_dsp
;
206 static int host_little_endian
;
207 static char **prog_argv
;
209 static int maskw
= 0;
210 static int maskl
= 0;
212 static SIM_OPEN_KIND sim_kind
;
214 static int tracing
= 0;
217 /* Short hand definitions of the registers */
219 #define SBIT(x) ((x)&sbit)
220 #define R0 saved_state.asregs.regs[0]
221 #define Rn saved_state.asregs.regs[n]
222 #define Rm saved_state.asregs.regs[m]
223 #define UR0 (unsigned int) (saved_state.asregs.regs[0])
224 #define UR (unsigned int) R
225 #define UR (unsigned int) R
226 #define SR0 saved_state.asregs.regs[0]
227 #define CREG(n) (saved_state.asregs.cregs.i[(n)])
228 #define GBR saved_state.asregs.cregs.named.gbr
229 #define VBR saved_state.asregs.cregs.named.vbr
230 #define DBR saved_state.asregs.cregs.named.dbr
231 #define TBR saved_state.asregs.cregs.named.tbr
232 #define IBCR saved_state.asregs.cregs.named.ibcr
233 #define IBNR saved_state.asregs.cregs.named.ibnr
234 #define BANKN (saved_state.asregs.cregs.named.ibnr & 0x1ff)
235 #define ME ((saved_state.asregs.cregs.named.ibnr >> 14) & 0x3)
236 #define SSR saved_state.asregs.cregs.named.ssr
237 #define SPC saved_state.asregs.cregs.named.spc
238 #define SGR saved_state.asregs.cregs.named.sgr
239 #define SREG(n) (saved_state.asregs.sregs.i[(n)])
240 #define MACH saved_state.asregs.sregs.named.mach
241 #define MACL saved_state.asregs.sregs.named.macl
242 #define PR saved_state.asregs.sregs.named.pr
243 #define FPUL saved_state.asregs.sregs.named.fpul
249 /* Alternate bank of registers r0-r7 */
251 /* Note: code controling SR handles flips between BANK0 and BANK1 */
252 #define Rn_BANK(n) (saved_state.asregs.cregs.named.bank[(n)])
253 #define SET_Rn_BANK(n, EXP) do { saved_state.asregs.cregs.named.bank[(n)] = (EXP); } while (0)
258 #define SR_MASK_BO (1 << 14)
259 #define SR_MASK_CS (1 << 13)
260 #define SR_MASK_DMY (1 << 11)
261 #define SR_MASK_DMX (1 << 10)
262 #define SR_MASK_M (1 << 9)
263 #define SR_MASK_Q (1 << 8)
264 #define SR_MASK_I (0xf << 4)
265 #define SR_MASK_S (1 << 1)
266 #define SR_MASK_T (1 << 0)
268 #define SR_MASK_BL (1 << 28)
269 #define SR_MASK_RB (1 << 29)
270 #define SR_MASK_MD (1 << 30)
271 #define SR_MASK_RC 0x0fff0000
272 #define SR_RC_INCREMENT -0x00010000
274 #define BO ((saved_state.asregs.cregs.named.sr & SR_MASK_BO) != 0)
275 #define CS ((saved_state.asregs.cregs.named.sr & SR_MASK_CS) != 0)
276 #define M ((saved_state.asregs.cregs.named.sr & SR_MASK_M) != 0)
277 #define Q ((saved_state.asregs.cregs.named.sr & SR_MASK_Q) != 0)
278 #define S ((saved_state.asregs.cregs.named.sr & SR_MASK_S) != 0)
279 #define T ((saved_state.asregs.cregs.named.sr & SR_MASK_T) != 0)
280 #define LDST ((saved_state.asregs.cregs.named.ldst) != 0)
282 #define SR_BL ((saved_state.asregs.cregs.named.sr & SR_MASK_BL) != 0)
283 #define SR_RB ((saved_state.asregs.cregs.named.sr & SR_MASK_RB) != 0)
284 #define SR_MD ((saved_state.asregs.cregs.named.sr & SR_MASK_MD) != 0)
285 #define SR_DMY ((saved_state.asregs.cregs.named.sr & SR_MASK_DMY) != 0)
286 #define SR_DMX ((saved_state.asregs.cregs.named.sr & SR_MASK_DMX) != 0)
287 #define SR_RC ((saved_state.asregs.cregs.named.sr & SR_MASK_RC))
289 /* Note: don't use this for privileged bits */
290 #define SET_SR_BIT(EXP, BIT) \
293 saved_state.asregs.cregs.named.sr |= (BIT); \
295 saved_state.asregs.cregs.named.sr &= ~(BIT); \
298 #define SET_SR_BO(EXP) SET_SR_BIT ((EXP), SR_MASK_BO)
299 #define SET_SR_CS(EXP) SET_SR_BIT ((EXP), SR_MASK_CS)
300 #define SET_BANKN(EXP) \
302 IBNR = (IBNR & 0xfe00) | (EXP & 0x1f); \
304 #define SET_ME(EXP) \
306 IBNR = (IBNR & 0x3fff) | ((EXP & 0x3) << 14); \
308 #define SET_SR_M(EXP) SET_SR_BIT ((EXP), SR_MASK_M)
309 #define SET_SR_Q(EXP) SET_SR_BIT ((EXP), SR_MASK_Q)
310 #define SET_SR_S(EXP) SET_SR_BIT ((EXP), SR_MASK_S)
311 #define SET_SR_T(EXP) SET_SR_BIT ((EXP), SR_MASK_T)
312 #define SET_LDST(EXP) (saved_state.asregs.cregs.named.ldst = ((EXP) != 0))
314 /* stc currently relies on being able to read SR without modifications. */
315 #define GET_SR() (saved_state.asregs.cregs.named.sr - 0)
317 #define SET_SR(x) set_sr (x)
320 (saved_state.asregs.cregs.named.sr \
321 = saved_state.asregs.cregs.named.sr & 0xf000ffff | ((x) & 0xfff) << 16)
323 /* Manipulate FPSCR */
325 #define FPSCR_MASK_FR (1 << 21)
326 #define FPSCR_MASK_SZ (1 << 20)
327 #define FPSCR_MASK_PR (1 << 19)
329 #define FPSCR_FR ((GET_FPSCR () & FPSCR_MASK_FR) != 0)
330 #define FPSCR_SZ ((GET_FPSCR () & FPSCR_MASK_SZ) != 0)
331 #define FPSCR_PR ((GET_FPSCR () & FPSCR_MASK_PR) != 0)
333 /* Count the number of arguments in an argv. */
335 count_argc (char **argv
)
342 for (i
= 0; argv
[i
] != NULL
; ++i
)
351 int old
= saved_state
.asregs
.sregs
.named
.fpscr
;
352 saved_state
.asregs
.sregs
.named
.fpscr
= (x
);
353 /* swap the floating point register banks */
354 if ((saved_state
.asregs
.sregs
.named
.fpscr
^ old
) & FPSCR_MASK_FR
355 /* Ignore bit change if simulating sh-dsp. */
358 union fregs_u tmpf
= saved_state
.asregs
.fregs
[0];
359 saved_state
.asregs
.fregs
[0] = saved_state
.asregs
.fregs
[1];
360 saved_state
.asregs
.fregs
[1] = tmpf
;
364 /* sts relies on being able to read fpscr directly. */
365 #define GET_FPSCR() (saved_state.asregs.sregs.named.fpscr)
366 #define SET_FPSCR(x) \
371 #define DSR (saved_state.asregs.sregs.named.fpscr)
379 #define RAISE_EXCEPTION(x) \
380 (saved_state.asregs.exception = x, saved_state.asregs.insn_end = 0)
382 #define RAISE_EXCEPTION_IF_IN_DELAY_SLOT() \
383 if (in_delay_slot) RAISE_EXCEPTION (SIGILL)
385 /* This function exists mainly for the purpose of setting a breakpoint to
386 catch simulated bus errors when running the simulator under GDB. */
398 raise_exception (SIGBUS
);
401 #define PROCESS_SPECIAL_ADDRESS(addr, endian, ptr, bits_written, \
402 forbidden_addr_bits, data, retval) \
404 if (addr & forbidden_addr_bits) \
409 else if ((addr & saved_state.asregs.xyram_select) \
410 == saved_state.asregs.xram_start) \
411 ptr = (void *) &saved_state.asregs.xmem_offset[addr ^ endian]; \
412 else if ((addr & saved_state.asregs.xyram_select) \
413 == saved_state.asregs.yram_start) \
414 ptr = (void *) &saved_state.asregs.ymem_offset[addr ^ endian]; \
415 else if ((unsigned) addr >> 24 == 0xf0 \
416 && bits_written == 32 && (data & 1) == 0) \
417 /* This invalidates (if not associative) or might invalidate \
418 (if associative) an instruction cache line. This is used for \
419 trampolines. Since we don't simulate the cache, this is a no-op \
420 as far as the simulator is concerned. */ \
424 if (bits_written == 8 && addr > 0x5000000) \
425 IOMEM (addr, 1, data); \
426 /* We can't do anything useful with the other stuff, so fail. */ \
432 /* FIXME: sim_resume should be renamed to sim_engine_run. sim_resume
433 being implemented by ../common/sim_resume.c and the below should
434 make a call to sim_engine_halt */
436 #define BUSERROR(addr, mask) ((addr) & (mask))
438 #define WRITE_BUSERROR(addr, mask, data, addr_func) \
443 addr_func (addr, data); \
449 #define READ_BUSERROR(addr, mask, addr_func) \
453 return addr_func (addr); \
457 /* Define this to enable register lifetime checking.
458 The compiler generates "add #0,rn" insns to mark registers as invalid,
459 the simulator uses this info to call fail if it finds a ref to an invalid
460 register before a def
467 #define CREF(x) if (!valid[x]) fail ();
468 #define CDEF(x) valid[x] = 1;
469 #define UNDEF(x) valid[x] = 0;
476 static void parse_and_set_memory_size (char *str
);
477 static int IOMEM (int addr
, int write
, int value
);
478 static struct loop_bounds
get_loop_bounds (int, int, unsigned char *,
479 unsigned char *, int, int);
480 static void process_wlat_addr (int, int);
481 static void process_wwat_addr (int, int);
482 static void process_wbat_addr (int, int);
483 static int process_rlat_addr (int);
484 static int process_rwat_addr (int);
485 static int process_rbat_addr (int);
486 static void INLINE
wlat_fast (unsigned char *, int, int, int);
487 static void INLINE
wwat_fast (unsigned char *, int, int, int, int);
488 static void INLINE
wbat_fast (unsigned char *, int, int, int);
489 static int INLINE
rlat_fast (unsigned char *, int, int);
490 static int INLINE
rwat_fast (unsigned char *, int, int, int);
491 static int INLINE
rbat_fast (unsigned char *, int, int);
493 static host_callback
*callback
;
497 /* Floating point registers */
499 #define DR(n) (get_dr (n))
505 if (host_little_endian
)
512 dr
.i
[1] = saved_state
.asregs
.fregs
[0].i
[n
+ 0];
513 dr
.i
[0] = saved_state
.asregs
.fregs
[0].i
[n
+ 1];
517 return (saved_state
.asregs
.fregs
[0].d
[n
>> 1]);
520 #define SET_DR(n, EXP) set_dr ((n), (EXP))
527 if (host_little_endian
)
535 saved_state
.asregs
.fregs
[0].i
[n
+ 0] = dr
.i
[1];
536 saved_state
.asregs
.fregs
[0].i
[n
+ 1] = dr
.i
[0];
539 saved_state
.asregs
.fregs
[0].d
[n
>> 1] = exp
;
542 #define SET_FI(n,EXP) (saved_state.asregs.fregs[0].i[(n)] = (EXP))
543 #define FI(n) (saved_state.asregs.fregs[0].i[(n)])
545 #define FR(n) (saved_state.asregs.fregs[0].f[(n)])
546 #define SET_FR(n,EXP) (saved_state.asregs.fregs[0].f[(n)] = (EXP))
548 #define XD_TO_XF(n) ((((n) & 1) << 5) | ((n) & 0x1e))
549 #define XF(n) (saved_state.asregs.fregs[(n) >> 5].i[(n) & 0x1f])
550 #define SET_XF(n,EXP) (saved_state.asregs.fregs[(n) >> 5].i[(n) & 0x1f] = (EXP))
552 #define RS saved_state.asregs.cregs.named.rs
553 #define RE saved_state.asregs.cregs.named.re
554 #define MOD (saved_state.asregs.cregs.named.mod)
557 MOD_ME = (unsigned) MOD >> 16 | (SR_DMY ? ~0xffff : (SR_DMX ? 0 : 0x10000)), \
558 MOD_DELTA = (MOD & 0xffff) - ((unsigned) MOD >> 16))
560 #define DSP_R(n) saved_state.asregs.sregs.i[(n)]
561 #define DSP_GRD(n) DSP_R ((n) + 8)
562 #define GET_DSP_GRD(n) ((n | 2) == 7 ? SEXT (DSP_GRD (n)) : SIGN32 (DSP_R (n)))
567 #define Y0 DSP_R (10)
568 #define Y1 DSP_R (11)
569 #define M0 DSP_R (12)
570 #define A1G DSP_R (13)
571 #define M1 DSP_R (14)
572 #define A0G DSP_R (15)
573 /* DSP_R (16) / DSP_GRD (16) are used as a fake destination for pcmp. */
574 #define MOD_ME DSP_GRD (17)
575 #define MOD_DELTA DSP_GRD (18)
577 #define FP_OP(n, OP, m) \
581 if (((n) & 1) || ((m) & 1)) \
582 RAISE_EXCEPTION (SIGILL); \
584 SET_DR (n, (DR (n) OP DR (m))); \
587 SET_FR (n, (FR (n) OP FR (m))); \
590 #define FP_UNARY(n, OP) \
595 RAISE_EXCEPTION (SIGILL); \
597 SET_DR (n, (OP (DR (n)))); \
600 SET_FR (n, (OP (FR (n)))); \
603 #define FP_CMP(n, OP, m) \
607 if (((n) & 1) || ((m) & 1)) \
608 RAISE_EXCEPTION (SIGILL); \
610 SET_SR_T (DR (n) OP DR (m)); \
613 SET_SR_T (FR (n) OP FR (m)); \
620 /* do we need to swap banks */
621 int old_gpr
= SR_MD
&& SR_RB
;
622 int new_gpr
= (new_sr
& SR_MASK_MD
) && (new_sr
& SR_MASK_RB
);
623 if (old_gpr
!= new_gpr
)
626 for (i
= 0; i
< 8; i
++)
628 tmp
= saved_state
.asregs
.cregs
.named
.bank
[i
];
629 saved_state
.asregs
.cregs
.named
.bank
[i
] = saved_state
.asregs
.regs
[i
];
630 saved_state
.asregs
.regs
[i
] = tmp
;
633 saved_state
.asregs
.cregs
.named
.sr
= new_sr
;
638 wlat_fast (memory
, x
, value
, maskl
)
639 unsigned char *memory
;
642 unsigned int *p
= (unsigned int *) (memory
+ x
);
643 WRITE_BUSERROR (x
, maskl
, v
, process_wlat_addr
);
648 wwat_fast (memory
, x
, value
, maskw
, endianw
)
649 unsigned char *memory
;
652 unsigned short *p
= (unsigned short *) (memory
+ (x
^ endianw
));
653 WRITE_BUSERROR (x
, maskw
, v
, process_wwat_addr
);
658 wbat_fast (memory
, x
, value
, maskb
)
659 unsigned char *memory
;
661 unsigned char *p
= memory
+ (x
^ endianb
);
662 WRITE_BUSERROR (x
, maskb
, value
, process_wbat_addr
);
670 rlat_fast (memory
, x
, maskl
)
671 unsigned char *memory
;
673 unsigned int *p
= (unsigned int *) (memory
+ x
);
674 READ_BUSERROR (x
, maskl
, process_rlat_addr
);
680 rwat_fast (memory
, x
, maskw
, endianw
)
681 unsigned char *memory
;
682 int x
, maskw
, endianw
;
684 unsigned short *p
= (unsigned short *) (memory
+ (x
^ endianw
));
685 READ_BUSERROR (x
, maskw
, process_rwat_addr
);
691 riat_fast (insn_ptr
, endianw
)
692 unsigned char *insn_ptr
;
694 unsigned short *p
= (unsigned short *) ((size_t) insn_ptr
^ endianw
);
700 rbat_fast (memory
, x
, maskb
)
701 unsigned char *memory
;
703 unsigned char *p
= memory
+ (x
^ endianb
);
704 READ_BUSERROR (x
, maskb
, process_rbat_addr
);
709 #define RWAT(x) (rwat_fast (memory, x, maskw, endianw))
710 #define RLAT(x) (rlat_fast (memory, x, maskl))
711 #define RBAT(x) (rbat_fast (memory, x, maskb))
712 #define RIAT(p) (riat_fast ((p), endianw))
713 #define WWAT(x,v) (wwat_fast (memory, x, v, maskw, endianw))
714 #define WLAT(x,v) (wlat_fast (memory, x, v, maskl))
715 #define WBAT(x,v) (wbat_fast (memory, x, v, maskb))
717 #define RUWAT(x) (RWAT (x) & 0xffff)
718 #define RSWAT(x) ((short) (RWAT (x)))
719 #define RSLAT(x) ((long) (RLAT (x)))
720 #define RSBAT(x) (SEXT (RBAT (x)))
722 #define RDAT(x, n) (do_rdat (memory, (x), (n), (maskl)))
724 do_rdat (memory
, x
, n
, maskl
)
734 f0
= rlat_fast (memory
, x
+ 0, maskl
);
735 f1
= rlat_fast (memory
, x
+ 4, maskl
);
736 saved_state
.asregs
.fregs
[i
].i
[(j
+ 0)] = f0
;
737 saved_state
.asregs
.fregs
[i
].i
[(j
+ 1)] = f1
;
741 #define WDAT(x, n) (do_wdat (memory, (x), (n), (maskl)))
743 do_wdat (memory
, x
, n
, maskl
)
753 f0
= saved_state
.asregs
.fregs
[i
].i
[(j
+ 0)];
754 f1
= saved_state
.asregs
.fregs
[i
].i
[(j
+ 1)];
755 wlat_fast (memory
, (x
+ 0), f0
, maskl
);
756 wlat_fast (memory
, (x
+ 4), f1
, maskl
);
761 process_wlat_addr (addr
, value
)
767 PROCESS_SPECIAL_ADDRESS (addr
, endianb
, ptr
, 32, 3, value
, );
772 process_wwat_addr (addr
, value
)
778 PROCESS_SPECIAL_ADDRESS (addr
, endianb
, ptr
, 16, 1, value
, );
783 process_wbat_addr (addr
, value
)
789 PROCESS_SPECIAL_ADDRESS (addr
, endianb
, ptr
, 8, 0, value
, );
794 process_rlat_addr (addr
)
799 PROCESS_SPECIAL_ADDRESS (addr
, endianb
, ptr
, -32, 3, -1, 0);
804 process_rwat_addr (addr
)
809 PROCESS_SPECIAL_ADDRESS (addr
, endianb
, ptr
, -16, 1, -1, 0);
814 process_rbat_addr (addr
)
819 PROCESS_SPECIAL_ADDRESS (addr
, endianb
, ptr
, -8, 0, -1, 0);
823 #define SEXT(x) (((x & 0xff) ^ (~0x7f))+0x80)
824 #define SEXT12(x) (((x & 0xfff) ^ 0x800) - 0x800)
825 #define SEXTW(y) ((int) ((short) y))
827 #define SEXT32(x) ((int) ((x & 0xffffffff) ^ 0x80000000U) - 0x7fffffff - 1)
829 #define SEXT32(x) ((int) (x))
831 #define SIGN32(x) (SEXT32 (x) >> 31)
833 /* convert pointer from target to host value. */
834 #define PT2H(x) ((x) + memory)
835 /* convert pointer from host to target value. */
836 #define PH2T(x) ((x) - memory)
838 #define SKIP_INSN(p) ((p) += ((RIAT (p) & 0xfc00) == 0xf800 ? 4 : 2))
840 #define SET_NIP(x) nip = (x); CHECK_INSN_PTR (nip);
842 static int in_delay_slot
= 0;
843 #define Delay_Slot(TEMPPC) iword = RIAT (TEMPPC); in_delay_slot = 1; goto top;
845 #define CHECK_INSN_PTR(p) \
847 if (saved_state.asregs.exception || PH2T (p) & maskw) \
848 saved_state.asregs.insn_end = 0; \
849 else if (p < loop.end) \
850 saved_state.asregs.insn_end = loop.end; \
852 saved_state.asregs.insn_end = mem_end; \
865 do { memstalls += ((((long) PC & 3) != 0) ? (n) : ((n) - 1)); } while (0)
867 #define L(x) thislock = x;
868 #define TL(x) if ((x) == prevlock) stalls++;
869 #define TB(x,y) if ((x) == prevlock || (y) == prevlock) stalls++;
873 #if defined(__GO32__)
874 int sim_memory_size
= 19;
876 int sim_memory_size
= 24;
879 static int sim_profile_size
= 17;
885 #define SMR1 (0x05FFFEC8) /* Channel 1 serial mode register */
886 #define BRR1 (0x05FFFEC9) /* Channel 1 bit rate register */
887 #define SCR1 (0x05FFFECA) /* Channel 1 serial control register */
888 #define TDR1 (0x05FFFECB) /* Channel 1 transmit data register */
889 #define SSR1 (0x05FFFECC) /* Channel 1 serial status register */
890 #define RDR1 (0x05FFFECD) /* Channel 1 receive data register */
892 #define SCI_RDRF 0x40 /* Recieve data register full */
893 #define SCI_TDRE 0x80 /* Transmit data register empty */
896 IOMEM (addr
, write
, value
)
928 return time ((long *) 0);
937 static FILE *profile_file
;
939 static unsigned INLINE
944 n
= (n
<< 24 | (n
& 0xff00) << 8
945 | (n
& 0xff0000) >> 8 | (n
& 0xff000000) >> 24);
949 static unsigned short INLINE
954 n
= n
<< 8 | (n
& 0xff00) >> 8;
964 union { char b
[4]; int n
; } u
;
966 fwrite (u
.b
, 4, 1, profile_file
);
974 union { char b
[4]; int n
; } u
;
976 fwrite (u
.b
, 2, 1, profile_file
);
979 /* Turn a pointer in a register into a pointer into real memory. */
985 return (char *) (x
+ saved_state
.asregs
.memory
);
988 /* STR points to a zero-terminated string in target byte order. Return
989 the number of bytes that need to be converted to host byte order in order
990 to use this string as a zero-terminated string on the host.
991 (Not counting the rounding up needed to operate on entire words.) */
996 unsigned char *memory
= saved_state
.asregs
.memory
;
998 int endian
= endianb
;
1003 for (end
= str
; memory
[end
^ endian
]; end
++) ;
1004 return end
- str
+ 1;
1014 if (! endianb
|| ! len
)
1016 start
= (int *) ptr (str
& ~3);
1017 end
= (int *) ptr (str
+ len
);
1021 *start
= (old
<< 24 | (old
& 0xff00) << 8
1022 | (old
& 0xff0000) >> 8 | (old
& 0xff000000) >> 24);
1025 while (start
< end
);
1028 /* Simulate a monitor trap, put the result into r0 and errno into r1
1029 return offset by which to adjust pc. */
1032 trap (i
, regs
, insn_ptr
, memory
, maskl
, maskw
, endianw
)
1035 unsigned char *insn_ptr
;
1036 unsigned char *memory
;
1041 printf ("%c", regs
[0]);
1044 raise_exception (SIGQUIT
);
1046 case 3: /* FIXME: for backwards compat, should be removed */
1049 unsigned int countp
= * (unsigned int *) (insn_ptr
+ 4);
1051 WLAT (countp
, RLAT (countp
) + 1);
1063 #if !defined(__GO32__) && !defined(_WIN32)
1067 /* This would work only if endianness matched between host and target.
1068 Besides, it's quite dangerous. */
1071 regs
[0] = execve (ptr (regs
[5]), (char **) ptr (regs
[6]),
1072 (char **) ptr (regs
[7]));
1075 regs
[0] = execve (ptr (regs
[5]), (char **) ptr (regs
[6]), 0);
1080 regs
[0] = (BUSERROR (regs
[5], maskl
)
1082 : pipe ((int *) ptr (regs
[5])));
1087 regs
[0] = wait (ptr (regs
[5]));
1089 #endif /* !defined(__GO32__) && !defined(_WIN32) */
1092 strnswap (regs
[6], regs
[7]);
1094 = callback
->read (callback
, regs
[5], ptr (regs
[6]), regs
[7]);
1095 strnswap (regs
[6], regs
[7]);
1098 strnswap (regs
[6], regs
[7]);
1100 regs
[0] = (int) callback
->write_stdout (callback
,
1101 ptr (regs
[6]), regs
[7]);
1103 regs
[0] = (int) callback
->write (callback
, regs
[5],
1104 ptr (regs
[6]), regs
[7]);
1105 strnswap (regs
[6], regs
[7]);
1108 regs
[0] = callback
->lseek (callback
,regs
[5], regs
[6], regs
[7]);
1111 regs
[0] = callback
->close (callback
,regs
[5]);
1115 int len
= strswaplen (regs
[5]);
1116 strnswap (regs
[5], len
);
1117 regs
[0] = callback
->open (callback
, ptr (regs
[5]), regs
[6]);
1118 strnswap (regs
[5], len
);
1122 /* EXIT - caller can look in r5 to work out the reason */
1123 raise_exception (SIGQUIT
);
1127 case SYS_stat
: /* added at hmsi */
1128 /* stat system call */
1130 struct stat host_stat
;
1132 int len
= strswaplen (regs
[5]);
1134 strnswap (regs
[5], len
);
1135 regs
[0] = stat (ptr (regs
[5]), &host_stat
);
1136 strnswap (regs
[5], len
);
1140 WWAT (buf
, host_stat
.st_dev
);
1142 WWAT (buf
, host_stat
.st_ino
);
1144 WLAT (buf
, host_stat
.st_mode
);
1146 WWAT (buf
, host_stat
.st_nlink
);
1148 WWAT (buf
, host_stat
.st_uid
);
1150 WWAT (buf
, host_stat
.st_gid
);
1152 WWAT (buf
, host_stat
.st_rdev
);
1154 WLAT (buf
, host_stat
.st_size
);
1156 WLAT (buf
, host_stat
.st_atime
);
1160 WLAT (buf
, host_stat
.st_mtime
);
1164 WLAT (buf
, host_stat
.st_ctime
);
1178 int len
= strswaplen (regs
[5]);
1180 strnswap (regs
[5], len
);
1181 regs
[0] = chown (ptr (regs
[5]), regs
[6], regs
[7]);
1182 strnswap (regs
[5], len
);
1188 int len
= strswaplen (regs
[5]);
1190 strnswap (regs
[5], len
);
1191 regs
[0] = chmod (ptr (regs
[5]), regs
[6]);
1192 strnswap (regs
[5], len
);
1197 /* Cast the second argument to void *, to avoid type mismatch
1198 if a prototype is present. */
1199 int len
= strswaplen (regs
[5]);
1201 strnswap (regs
[5], len
);
1202 regs
[0] = utime (ptr (regs
[5]), (void *) ptr (regs
[6]));
1203 strnswap (regs
[5], len
);
1207 regs
[0] = count_argc (prog_argv
);
1210 if (regs
[5] < count_argc (prog_argv
))
1211 regs
[0] = strlen (prog_argv
[regs
[5]]);
1216 if (regs
[5] < count_argc (prog_argv
))
1218 /* Include the termination byte. */
1219 int i
= strlen (prog_argv
[regs
[5]]) + 1;
1220 regs
[0] = sim_write (0, regs
[6], prog_argv
[regs
[5]], i
);
1226 regs
[0] = get_now ();
1229 regs
[0] = callback
->ftruncate (callback
, regs
[5], regs
[6]);
1233 int len
= strswaplen (regs
[5]);
1234 strnswap (regs
[5], len
);
1235 regs
[0] = callback
->truncate (callback
, ptr (regs
[5]), regs
[6]);
1236 strnswap (regs
[5], len
);
1243 regs
[1] = callback
->get_errno (callback
);
1248 case 13: /* Set IBNR */
1249 IBNR
= regs
[0] & 0xffff;
1251 case 14: /* Set IBCR */
1252 IBCR
= regs
[0] & 0xffff;
1256 raise_exception (SIGTRAP
);
1265 div1 (R
, iRn2
, iRn1
/*, T*/)
1272 unsigned char old_q
, tmp1
;
1275 SET_SR_Q ((unsigned char) ((0x80000000 & R
[iRn1
]) != 0));
1277 R
[iRn1
] |= (unsigned long) T
;
1287 tmp1
= (R
[iRn1
] > tmp0
);
1294 SET_SR_Q ((unsigned char) (tmp1
== 0));
1301 tmp1
= (R
[iRn1
] < tmp0
);
1305 SET_SR_Q ((unsigned char) (tmp1
== 0));
1320 tmp1
= (R
[iRn1
] < tmp0
);
1327 SET_SR_Q ((unsigned char) (tmp1
== 0));
1334 tmp1
= (R
[iRn1
] > tmp0
);
1338 SET_SR_Q ((unsigned char) (tmp1
== 0));
1359 unsigned long RnL
, RnH
;
1360 unsigned long RmL
, RmH
;
1361 unsigned long temp0
, temp1
, temp2
, temp3
;
1362 unsigned long Res2
, Res1
, Res0
;
1365 RnH
= (rn
>> 16) & 0xffff;
1367 RmH
= (rm
>> 16) & 0xffff;
1373 Res1
= temp1
+ temp2
;
1376 temp1
= (Res1
<< 16) & 0xffff0000;
1377 Res0
= temp0
+ temp1
;
1380 Res2
+= ((Res1
>> 16) & 0xffff) + temp3
;
1384 if (rn
& 0x80000000)
1386 if (rm
& 0x80000000)
1395 macw (regs
, memory
, n
, m
, endianw
)
1397 unsigned char *memory
;
1402 long prod
, macl
, sum
;
1404 tempm
=RSWAT (regs
[m
]); regs
[m
]+=2;
1405 tempn
=RSWAT (regs
[n
]); regs
[n
]+=2;
1408 prod
= (long) (short) tempm
* (long) (short) tempn
;
1412 if ((~(prod
^ macl
) & (sum
^ prod
)) < 0)
1414 /* MACH's lsb is a sticky overflow bit. */
1416 /* Store the smallest negative number in MACL if prod is
1417 negative, and the largest positive number otherwise. */
1418 sum
= 0x7fffffff + (prod
< 0);
1424 /* Add to MACH the sign extended product, and carry from low sum. */
1425 mach
= MACH
+ (-(prod
< 0)) + ((unsigned long) sum
< prod
);
1426 /* Sign extend at 10:th bit in MACH. */
1427 MACH
= (mach
& 0x1ff) | -(mach
& 0x200);
1433 macl (regs
, memory
, n
, m
)
1435 unsigned char *memory
;
1443 tempm
= RSLAT (regs
[m
]);
1446 tempn
= RSLAT (regs
[n
]);
1452 mac64
= ((long long) macl
& 0xffffffff) |
1453 ((long long) mach
& 0xffffffff) << 32;
1455 ans
= (long long) tempm
* (long long) tempn
; /* Multiply 32bit * 32bit */
1457 mac64
+= ans
; /* Accumulate 64bit + 64 bit */
1459 macl
= (long) (mac64
& 0xffffffff);
1460 mach
= (long) ((mac64
>> 32) & 0xffffffff);
1462 if (S
) /* Store only 48 bits of the result */
1464 if (mach
< 0) /* Result is negative */
1466 mach
= mach
& 0x0000ffff; /* Mask higher 16 bits */
1467 mach
|= 0xffff8000; /* Sign extend higher 16 bits */
1470 mach
= mach
& 0x00007fff; /* Postive Result */
1501 /* Do extended displacement move instructions. */
1503 do_long_move_insn (int op
, int disp12
, int m
, int n
, int *thatlock
)
1506 int thislock
= *thatlock
;
1507 int endianw
= global_endianw
;
1508 int *R
= &(saved_state
.asregs
.regs
[0]);
1509 unsigned char *memory
= saved_state
.asregs
.memory
;
1510 int maskb
= ~((saved_state
.asregs
.msize
- 1) & ~0);
1511 unsigned char *insn_ptr
= PT2H (saved_state
.asregs
.pc
);
1514 case MOVB_RM
: /* signed */
1515 WBAT (disp12
* 1 + R
[n
], R
[m
]);
1518 WWAT (disp12
* 2 + R
[n
], R
[m
]);
1521 WLAT (disp12
* 4 + R
[n
], R
[m
]);
1523 case FMOV_RM
: /* floating point */
1527 WDAT (R
[n
] + 8 * disp12
, m
);
1530 WLAT (R
[n
] + 4 * disp12
, FI (m
));
1533 R
[n
] = RSBAT (disp12
* 1 + R
[m
]);
1537 R
[n
] = RSWAT (disp12
* 2 + R
[m
]);
1541 R
[n
] = RLAT (disp12
* 4 + R
[m
]);
1547 RDAT (R
[m
] + 8 * disp12
, n
);
1550 SET_FI (n
, RLAT (R
[m
] + 4 * disp12
));
1552 case MOVU_BMR
: /* unsigned */
1553 R
[n
] = RBAT (disp12
* 1 + R
[m
]);
1557 R
[n
] = RWAT (disp12
* 2 + R
[m
]);
1561 RAISE_EXCEPTION (SIGINT
);
1564 saved_state
.asregs
.memstalls
+= memstalls
;
1565 *thatlock
= thislock
;
1568 /* Do binary logical bit-manipulation insns. */
1570 do_blog_insn (int imm
, int addr
, int binop
,
1571 unsigned char *memory
, int maskb
)
1573 int oldval
= RBAT (addr
);
1576 case B_BCLR
: /* bclr.b */
1577 WBAT (addr
, oldval
& ~imm
);
1579 case B_BSET
: /* bset.b */
1580 WBAT (addr
, oldval
| imm
);
1582 case B_BST
: /* bst.b */
1584 WBAT (addr
, oldval
| imm
);
1586 WBAT (addr
, oldval
& ~imm
);
1588 case B_BLD
: /* bld.b */
1589 SET_SR_T ((oldval
& imm
) != 0);
1591 case B_BAND
: /* band.b */
1592 SET_SR_T (T
&& ((oldval
& imm
) != 0));
1594 case B_BOR
: /* bor.b */
1595 SET_SR_T (T
|| ((oldval
& imm
) != 0));
1597 case B_BXOR
: /* bxor.b */
1598 SET_SR_T (T
^ ((oldval
& imm
) != 0));
1600 case B_BLDNOT
: /* bldnot.b */
1601 SET_SR_T ((oldval
& imm
) == 0);
1603 case B_BANDNOT
: /* bandnot.b */
1604 SET_SR_T (T
&& ((oldval
& imm
) == 0));
1606 case B_BORNOT
: /* bornot.b */
1607 SET_SR_T (T
|| ((oldval
& imm
) == 0));
1612 fsca_s (int in
, double (*f
) (double))
1614 double rad
= ldexp ((in
& 0xffff), -15) * 3.141592653589793238462643383;
1615 double result
= (*f
) (rad
);
1616 double error
, upper
, lower
, frac
;
1619 /* Search the value with the maximum error that is still within the
1620 architectural spec. */
1621 error
= ldexp (1., -21);
1622 /* compensate for calculation inaccuracy by reducing error. */
1623 error
= error
- ldexp (1., -50);
1624 upper
= result
+ error
;
1625 frac
= frexp (upper
, &exp
);
1626 upper
= ldexp (floor (ldexp (frac
, 24)), exp
- 24);
1627 lower
= result
- error
;
1628 frac
= frexp (lower
, &exp
);
1629 lower
= ldexp (ceil (ldexp (frac
, 24)), exp
- 24);
1630 return abs (upper
- result
) >= abs (lower
- result
) ? upper
: lower
;
1636 double result
= 1. / sqrt (in
);
1638 double frac
, upper
, lower
, error
, eps
;
1641 result
= result
- (result
* result
* in
- 1) * 0.5 * result
;
1642 /* Search the value with the maximum error that is still within the
1643 architectural spec. */
1644 frac
= frexp (result
, &exp
);
1645 frac
= ldexp (frac
, 24);
1646 error
= 4.0; /* 1 << 24-1-21 */
1647 /* use eps to compensate for possible 1 ulp error in our 'exact' result. */
1648 eps
= ldexp (1., -29);
1649 upper
= floor (frac
+ error
- eps
);
1650 if (upper
> 16777216.)
1651 upper
= floor ((frac
+ error
- eps
) * 0.5) * 2.;
1652 lower
= ceil ((frac
- error
+ eps
) * 2) * .5;
1653 if (lower
> 8388608.)
1654 lower
= ceil (frac
- error
+ eps
);
1655 upper
= ldexp (upper
, exp
- 24);
1656 lower
= ldexp (lower
, exp
- 24);
1657 return upper
- result
>= result
- lower
? upper
: lower
;
1661 /* GET_LOOP_BOUNDS {EXTENDED}
1662 These two functions compute the actual starting and ending point
1663 of the repeat loop, based on the RS and RE registers (repeat start,
1664 repeat stop). The extended version is called for LDRC, and the
1665 regular version is called for SETRC. The difference is that for
1666 LDRC, the loop start and end instructions are literally the ones
1667 pointed to by RS and RE -- for SETRC, they're not (see docs). */
1669 static struct loop_bounds
1670 get_loop_bounds_ext (rs
, re
, memory
, mem_end
, maskw
, endianw
)
1672 unsigned char *memory
, *mem_end
;
1675 struct loop_bounds loop
;
1677 /* FIXME: should I verify RS < RE? */
1678 loop
.start
= PT2H (RS
); /* FIXME not using the params? */
1679 loop
.end
= PT2H (RE
& ~1); /* Ignore bit 0 of RE. */
1680 SKIP_INSN (loop
.end
);
1681 if (loop
.end
>= mem_end
)
1682 loop
.end
= PT2H (0);
1686 static struct loop_bounds
1687 get_loop_bounds (rs
, re
, memory
, mem_end
, maskw
, endianw
)
1689 unsigned char *memory
, *mem_end
;
1692 struct loop_bounds loop
;
1698 loop
.start
= PT2H (RE
- 4);
1699 SKIP_INSN (loop
.start
);
1700 loop
.end
= loop
.start
;
1702 SKIP_INSN (loop
.end
);
1704 SKIP_INSN (loop
.end
);
1705 SKIP_INSN (loop
.end
);
1709 loop
.start
= PT2H (RS
);
1710 loop
.end
= PT2H (RE
- 4);
1711 SKIP_INSN (loop
.end
);
1712 SKIP_INSN (loop
.end
);
1713 SKIP_INSN (loop
.end
);
1714 SKIP_INSN (loop
.end
);
1716 if (loop
.end
>= mem_end
)
1717 loop
.end
= PT2H (0);
1720 loop
.end
= PT2H (0);
1725 static void ppi_insn ();
1729 /* Provide calloc / free versions that use an anonymous mmap. This can
1730 significantly cut the start-up time when a large simulator memory is
1731 required, because pages are only zeroed on demand. */
1732 #ifdef MAP_ANONYMOUS
1734 mcalloc (size_t nmemb
, size_t size
)
1740 return mmap (0, size
, PROT_READ
| PROT_WRITE
, MAP_PRIVATE
| MAP_ANONYMOUS
,
1744 #define mfree(start,length) munmap ((start), (length))
1746 #define mcalloc calloc
1747 #define mfree(start,length) free(start)
1750 /* Set the memory size to the power of two provided. */
1757 sim_memory_size
= power
;
1759 if (saved_state
.asregs
.memory
)
1761 mfree (saved_state
.asregs
.memory
, saved_state
.asregs
.msize
);
1764 saved_state
.asregs
.msize
= 1 << power
;
1766 saved_state
.asregs
.memory
=
1767 (unsigned char *) mcalloc (1, saved_state
.asregs
.msize
);
1769 if (!saved_state
.asregs
.memory
)
1772 "Not enough VM for simulation of %d bytes of RAM\n",
1773 saved_state
.asregs
.msize
);
1775 saved_state
.asregs
.msize
= 1;
1776 saved_state
.asregs
.memory
= (unsigned char *) mcalloc (1, 1);
1784 int was_dsp
= target_dsp
;
1785 unsigned long mach
= bfd_get_mach (abfd
);
1787 if (mach
== bfd_mach_sh_dsp
||
1788 mach
== bfd_mach_sh4al_dsp
||
1789 mach
== bfd_mach_sh3_dsp
)
1791 int ram_area_size
, xram_start
, yram_start
;
1795 if (mach
== bfd_mach_sh_dsp
)
1797 /* SH7410 (orig. sh-sdp):
1798 4KB each for X & Y memory;
1799 On-chip X RAM 0x0800f000-0x0800ffff
1800 On-chip Y RAM 0x0801f000-0x0801ffff */
1801 xram_start
= 0x0800f000;
1802 ram_area_size
= 0x1000;
1804 if (mach
== bfd_mach_sh3_dsp
|| mach
== bfd_mach_sh4al_dsp
)
1807 8KB each for X & Y memory;
1808 On-chip X RAM 0x1000e000-0x1000ffff
1809 On-chip Y RAM 0x1001e000-0x1001ffff */
1810 xram_start
= 0x1000e000;
1811 ram_area_size
= 0x2000;
1813 yram_start
= xram_start
+ 0x10000;
1814 new_select
= ~(ram_area_size
- 1);
1815 if (saved_state
.asregs
.xyram_select
!= new_select
)
1817 saved_state
.asregs
.xyram_select
= new_select
;
1818 free (saved_state
.asregs
.xmem
);
1819 free (saved_state
.asregs
.ymem
);
1820 saved_state
.asregs
.xmem
=
1821 (unsigned char *) calloc (1, ram_area_size
);
1822 saved_state
.asregs
.ymem
=
1823 (unsigned char *) calloc (1, ram_area_size
);
1825 /* Disable use of X / Y mmeory if not allocated. */
1826 if (! saved_state
.asregs
.xmem
|| ! saved_state
.asregs
.ymem
)
1828 saved_state
.asregs
.xyram_select
= 0;
1829 if (saved_state
.asregs
.xmem
)
1830 free (saved_state
.asregs
.xmem
);
1831 if (saved_state
.asregs
.ymem
)
1832 free (saved_state
.asregs
.ymem
);
1835 saved_state
.asregs
.xram_start
= xram_start
;
1836 saved_state
.asregs
.yram_start
= yram_start
;
1837 saved_state
.asregs
.xmem_offset
= saved_state
.asregs
.xmem
- xram_start
;
1838 saved_state
.asregs
.ymem_offset
= saved_state
.asregs
.ymem
- yram_start
;
1843 if (saved_state
.asregs
.xyram_select
)
1845 saved_state
.asregs
.xyram_select
= 0;
1846 free (saved_state
.asregs
.xmem
);
1847 free (saved_state
.asregs
.ymem
);
1851 if (! saved_state
.asregs
.xyram_select
)
1853 saved_state
.asregs
.xram_start
= 1;
1854 saved_state
.asregs
.yram_start
= 1;
1857 if (saved_state
.asregs
.regstack
== NULL
)
1858 saved_state
.asregs
.regstack
=
1859 calloc (512, sizeof *saved_state
.asregs
.regstack
);
1861 if (target_dsp
!= was_dsp
)
1865 for (i
= (sizeof sh_dsp_table
/ sizeof sh_dsp_table
[0]) - 1; i
>= 0; i
--)
1867 tmp
= sh_jump_table
[0xf000 + i
];
1868 sh_jump_table
[0xf000 + i
] = sh_dsp_table
[i
];
1869 sh_dsp_table
[i
] = tmp
;
1877 host_little_endian
= 0;
1878 * (char*) &host_little_endian
= 1;
1879 host_little_endian
&= 1;
1881 if (saved_state
.asregs
.msize
!= 1 << sim_memory_size
)
1883 sim_size (sim_memory_size
);
1886 if (saved_state
.asregs
.profile
&& !profile_file
)
1888 profile_file
= fopen ("gmon.out", "wb");
1889 /* Seek to where to put the call arc data */
1890 nsamples
= (1 << sim_profile_size
);
1892 fseek (profile_file
, nsamples
* 2 + 12, 0);
1896 fprintf (stderr
, "Can't open gmon.out\n");
1900 saved_state
.asregs
.profile_hist
=
1901 (unsigned short *) calloc (64, (nsamples
* sizeof (short) / 64));
1914 p
= saved_state
.asregs
.profile_hist
;
1916 maxpc
= (1 << sim_profile_size
);
1918 fseek (profile_file
, 0L, 0);
1919 swapout (minpc
<< PROFILE_SHIFT
);
1920 swapout (maxpc
<< PROFILE_SHIFT
);
1921 swapout (nsamples
* 2 + 12);
1922 for (i
= 0; i
< nsamples
; i
++)
1923 swapout16 (saved_state
.asregs
.profile_hist
[i
]);
1937 #define MMASKB ((saved_state.asregs.msize -1) & ~0)
1943 raise_exception (SIGINT
);
1948 sim_resume (sd
, step
, siggnal
)
1952 register unsigned char *insn_ptr
;
1953 unsigned char *mem_end
;
1954 struct loop_bounds loop
;
1955 register int cycles
= 0;
1956 register int stalls
= 0;
1957 register int memstalls
= 0;
1958 register int insts
= 0;
1959 register int prevlock
;
1963 register int thislock
;
1965 register unsigned int doprofile
;
1966 register int pollcount
= 0;
1967 /* endianw is used for every insn fetch, hence it makes sense to cache it.
1968 endianb is used less often. */
1969 register int endianw
= global_endianw
;
1971 int tick_start
= get_now ();
1972 void (*prev_fpe
) ();
1974 register unsigned short *jump_table
= sh_jump_table
;
1976 register int *R
= &(saved_state
.asregs
.regs
[0]);
1982 register int maskb
= ~((saved_state
.asregs
.msize
- 1) & ~0);
1983 register int maskw
= ~((saved_state
.asregs
.msize
- 1) & ~1);
1984 register int maskl
= ~((saved_state
.asregs
.msize
- 1) & ~3);
1985 register unsigned char *memory
;
1986 register unsigned int sbit
= ((unsigned int) 1 << 31);
1988 prev_fpe
= signal (SIGFPE
, SIG_IGN
);
1991 saved_state
.asregs
.exception
= 0;
1993 memory
= saved_state
.asregs
.memory
;
1994 mem_end
= memory
+ saved_state
.asregs
.msize
;
1997 loop
= get_loop_bounds_ext (RS
, RE
, memory
, mem_end
, maskw
, endianw
);
1999 loop
= get_loop_bounds (RS
, RE
, memory
, mem_end
, maskw
, endianw
);
2001 insn_ptr
= PT2H (saved_state
.asregs
.pc
);
2002 CHECK_INSN_PTR (insn_ptr
);
2005 PR
= saved_state
.asregs
.sregs
.named
.pr
;
2007 /*T = GET_SR () & SR_MASK_T;*/
2008 prevlock
= saved_state
.asregs
.prevlock
;
2009 thislock
= saved_state
.asregs
.thislock
;
2010 doprofile
= saved_state
.asregs
.profile
;
2012 /* If profiling not enabled, disable it by asking for
2013 profiles infrequently. */
2018 if (step
&& insn_ptr
< saved_state
.asregs
.insn_end
)
2020 if (saved_state
.asregs
.exception
)
2021 /* This can happen if we've already been single-stepping and
2022 encountered a loop end. */
2023 saved_state
.asregs
.insn_end
= insn_ptr
;
2026 saved_state
.asregs
.exception
= SIGTRAP
;
2027 saved_state
.asregs
.insn_end
= insn_ptr
+ 2;
2031 while (insn_ptr
< saved_state
.asregs
.insn_end
)
2033 register unsigned int iword
= RIAT (insn_ptr
);
2034 register unsigned int ult
;
2035 register unsigned char *nip
= insn_ptr
+ 2;
2042 fprintf (stderr
, "PC: %08x, insn: %04x\n", PH2T (insn_ptr
), iword
);
2050 if (--pollcount
< 0)
2052 pollcount
= POLL_QUIT_INTERVAL
;
2053 if ((*callback
->poll_quit
) != NULL
2054 && (*callback
->poll_quit
) (callback
))
2061 prevlock
= thislock
;
2065 if (cycles
>= doprofile
)
2068 saved_state
.asregs
.cycles
+= doprofile
;
2069 cycles
-= doprofile
;
2070 if (saved_state
.asregs
.profile_hist
)
2072 int n
= PH2T (insn_ptr
) >> PROFILE_SHIFT
;
2075 int i
= saved_state
.asregs
.profile_hist
[n
];
2077 saved_state
.asregs
.profile_hist
[n
] = i
+ 1;
2084 if (saved_state
.asregs
.insn_end
== loop
.end
)
2086 saved_state
.asregs
.cregs
.named
.sr
+= SR_RC_INCREMENT
;
2088 insn_ptr
= loop
.start
;
2091 saved_state
.asregs
.insn_end
= mem_end
;
2092 loop
.end
= PT2H (0);
2097 if (saved_state
.asregs
.exception
== SIGILL
2098 || saved_state
.asregs
.exception
== SIGBUS
)
2102 /* Check for SIGBUS due to insn fetch. */
2103 else if (! saved_state
.asregs
.exception
)
2104 saved_state
.asregs
.exception
= SIGBUS
;
2106 saved_state
.asregs
.ticks
+= get_now () - tick_start
;
2107 saved_state
.asregs
.cycles
+= cycles
;
2108 saved_state
.asregs
.stalls
+= stalls
;
2109 saved_state
.asregs
.memstalls
+= memstalls
;
2110 saved_state
.asregs
.insts
+= insts
;
2111 saved_state
.asregs
.pc
= PH2T (insn_ptr
);
2113 saved_state
.asregs
.sregs
.named
.pr
= PR
;
2116 saved_state
.asregs
.prevlock
= prevlock
;
2117 saved_state
.asregs
.thislock
= thislock
;
2124 signal (SIGFPE
, prev_fpe
);
2128 sim_write (sd
, addr
, buffer
, size
)
2131 const unsigned char *buffer
;
2138 for (i
= 0; i
< size
; i
++)
2140 saved_state
.asregs
.memory
[(MMASKB
& (addr
+ i
)) ^ endianb
] = buffer
[i
];
2146 sim_read (sd
, addr
, buffer
, size
)
2149 unsigned char *buffer
;
2156 for (i
= 0; i
< size
; i
++)
2158 buffer
[i
] = saved_state
.asregs
.memory
[(MMASKB
& (addr
+ i
)) ^ endianb
];
2163 static int gdb_bank_number
;
2173 sim_store_register (sd
, rn
, memory
, length
)
2176 unsigned char *memory
;
2182 val
= swap (* (int *) memory
);
2185 case SIM_SH_R0_REGNUM
: case SIM_SH_R1_REGNUM
: case SIM_SH_R2_REGNUM
:
2186 case SIM_SH_R3_REGNUM
: case SIM_SH_R4_REGNUM
: case SIM_SH_R5_REGNUM
:
2187 case SIM_SH_R6_REGNUM
: case SIM_SH_R7_REGNUM
: case SIM_SH_R8_REGNUM
:
2188 case SIM_SH_R9_REGNUM
: case SIM_SH_R10_REGNUM
: case SIM_SH_R11_REGNUM
:
2189 case SIM_SH_R12_REGNUM
: case SIM_SH_R13_REGNUM
: case SIM_SH_R14_REGNUM
:
2190 case SIM_SH_R15_REGNUM
:
2191 saved_state
.asregs
.regs
[rn
] = val
;
2193 case SIM_SH_PC_REGNUM
:
2194 saved_state
.asregs
.pc
= val
;
2196 case SIM_SH_PR_REGNUM
:
2199 case SIM_SH_GBR_REGNUM
:
2202 case SIM_SH_VBR_REGNUM
:
2205 case SIM_SH_MACH_REGNUM
:
2208 case SIM_SH_MACL_REGNUM
:
2211 case SIM_SH_SR_REGNUM
:
2214 case SIM_SH_FPUL_REGNUM
:
2217 case SIM_SH_FPSCR_REGNUM
:
2220 case SIM_SH_FR0_REGNUM
: case SIM_SH_FR1_REGNUM
: case SIM_SH_FR2_REGNUM
:
2221 case SIM_SH_FR3_REGNUM
: case SIM_SH_FR4_REGNUM
: case SIM_SH_FR5_REGNUM
:
2222 case SIM_SH_FR6_REGNUM
: case SIM_SH_FR7_REGNUM
: case SIM_SH_FR8_REGNUM
:
2223 case SIM_SH_FR9_REGNUM
: case SIM_SH_FR10_REGNUM
: case SIM_SH_FR11_REGNUM
:
2224 case SIM_SH_FR12_REGNUM
: case SIM_SH_FR13_REGNUM
: case SIM_SH_FR14_REGNUM
:
2225 case SIM_SH_FR15_REGNUM
:
2226 SET_FI (rn
- SIM_SH_FR0_REGNUM
, val
);
2228 case SIM_SH_DSR_REGNUM
:
2231 case SIM_SH_A0G_REGNUM
:
2234 case SIM_SH_A0_REGNUM
:
2237 case SIM_SH_A1G_REGNUM
:
2240 case SIM_SH_A1_REGNUM
:
2243 case SIM_SH_M0_REGNUM
:
2246 case SIM_SH_M1_REGNUM
:
2249 case SIM_SH_X0_REGNUM
:
2252 case SIM_SH_X1_REGNUM
:
2255 case SIM_SH_Y0_REGNUM
:
2258 case SIM_SH_Y1_REGNUM
:
2261 case SIM_SH_MOD_REGNUM
:
2264 case SIM_SH_RS_REGNUM
:
2267 case SIM_SH_RE_REGNUM
:
2270 case SIM_SH_SSR_REGNUM
:
2273 case SIM_SH_SPC_REGNUM
:
2276 /* The rn_bank idiosyncracies are not due to hardware differences, but to
2277 a weird aliasing naming scheme for sh3 / sh3e / sh4. */
2278 case SIM_SH_R0_BANK0_REGNUM
: case SIM_SH_R1_BANK0_REGNUM
:
2279 case SIM_SH_R2_BANK0_REGNUM
: case SIM_SH_R3_BANK0_REGNUM
:
2280 case SIM_SH_R4_BANK0_REGNUM
: case SIM_SH_R5_BANK0_REGNUM
:
2281 case SIM_SH_R6_BANK0_REGNUM
: case SIM_SH_R7_BANK0_REGNUM
:
2282 if (saved_state
.asregs
.bfd_mach
== bfd_mach_sh2a
)
2284 rn
-= SIM_SH_R0_BANK0_REGNUM
;
2285 saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[rn
] = val
;
2289 Rn_BANK (rn
- SIM_SH_R0_BANK0_REGNUM
) = val
;
2291 saved_state
.asregs
.regs
[rn
- SIM_SH_R0_BANK0_REGNUM
] = val
;
2293 case SIM_SH_R0_BANK1_REGNUM
: case SIM_SH_R1_BANK1_REGNUM
:
2294 case SIM_SH_R2_BANK1_REGNUM
: case SIM_SH_R3_BANK1_REGNUM
:
2295 case SIM_SH_R4_BANK1_REGNUM
: case SIM_SH_R5_BANK1_REGNUM
:
2296 case SIM_SH_R6_BANK1_REGNUM
: case SIM_SH_R7_BANK1_REGNUM
:
2297 if (saved_state
.asregs
.bfd_mach
== bfd_mach_sh2a
)
2299 rn
-= SIM_SH_R0_BANK1_REGNUM
;
2300 saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[rn
+ 8] = val
;
2304 saved_state
.asregs
.regs
[rn
- SIM_SH_R0_BANK1_REGNUM
] = val
;
2306 Rn_BANK (rn
- SIM_SH_R0_BANK1_REGNUM
) = val
;
2308 case SIM_SH_R0_BANK_REGNUM
: case SIM_SH_R1_BANK_REGNUM
:
2309 case SIM_SH_R2_BANK_REGNUM
: case SIM_SH_R3_BANK_REGNUM
:
2310 case SIM_SH_R4_BANK_REGNUM
: case SIM_SH_R5_BANK_REGNUM
:
2311 case SIM_SH_R6_BANK_REGNUM
: case SIM_SH_R7_BANK_REGNUM
:
2312 SET_Rn_BANK (rn
- SIM_SH_R0_BANK_REGNUM
, val
);
2314 case SIM_SH_TBR_REGNUM
:
2317 case SIM_SH_IBNR_REGNUM
:
2320 case SIM_SH_IBCR_REGNUM
:
2323 case SIM_SH_BANK_REGNUM
:
2324 /* This is a pseudo-register maintained just for gdb.
2325 It tells us what register bank gdb would like to read/write. */
2326 gdb_bank_number
= val
;
2328 case SIM_SH_BANK_MACL_REGNUM
:
2329 saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[REGBANK_MACL
] = val
;
2331 case SIM_SH_BANK_GBR_REGNUM
:
2332 saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[REGBANK_GBR
] = val
;
2334 case SIM_SH_BANK_PR_REGNUM
:
2335 saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[REGBANK_PR
] = val
;
2337 case SIM_SH_BANK_IVN_REGNUM
:
2338 saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[REGBANK_IVN
] = val
;
2340 case SIM_SH_BANK_MACH_REGNUM
:
2341 saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[REGBANK_MACH
] = val
;
2350 sim_fetch_register (sd
, rn
, memory
, length
)
2353 unsigned char *memory
;
2361 case SIM_SH_R0_REGNUM
: case SIM_SH_R1_REGNUM
: case SIM_SH_R2_REGNUM
:
2362 case SIM_SH_R3_REGNUM
: case SIM_SH_R4_REGNUM
: case SIM_SH_R5_REGNUM
:
2363 case SIM_SH_R6_REGNUM
: case SIM_SH_R7_REGNUM
: case SIM_SH_R8_REGNUM
:
2364 case SIM_SH_R9_REGNUM
: case SIM_SH_R10_REGNUM
: case SIM_SH_R11_REGNUM
:
2365 case SIM_SH_R12_REGNUM
: case SIM_SH_R13_REGNUM
: case SIM_SH_R14_REGNUM
:
2366 case SIM_SH_R15_REGNUM
:
2367 val
= saved_state
.asregs
.regs
[rn
];
2369 case SIM_SH_PC_REGNUM
:
2370 val
= saved_state
.asregs
.pc
;
2372 case SIM_SH_PR_REGNUM
:
2375 case SIM_SH_GBR_REGNUM
:
2378 case SIM_SH_VBR_REGNUM
:
2381 case SIM_SH_MACH_REGNUM
:
2384 case SIM_SH_MACL_REGNUM
:
2387 case SIM_SH_SR_REGNUM
:
2390 case SIM_SH_FPUL_REGNUM
:
2393 case SIM_SH_FPSCR_REGNUM
:
2396 case SIM_SH_FR0_REGNUM
: case SIM_SH_FR1_REGNUM
: case SIM_SH_FR2_REGNUM
:
2397 case SIM_SH_FR3_REGNUM
: case SIM_SH_FR4_REGNUM
: case SIM_SH_FR5_REGNUM
:
2398 case SIM_SH_FR6_REGNUM
: case SIM_SH_FR7_REGNUM
: case SIM_SH_FR8_REGNUM
:
2399 case SIM_SH_FR9_REGNUM
: case SIM_SH_FR10_REGNUM
: case SIM_SH_FR11_REGNUM
:
2400 case SIM_SH_FR12_REGNUM
: case SIM_SH_FR13_REGNUM
: case SIM_SH_FR14_REGNUM
:
2401 case SIM_SH_FR15_REGNUM
:
2402 val
= FI (rn
- SIM_SH_FR0_REGNUM
);
2404 case SIM_SH_DSR_REGNUM
:
2407 case SIM_SH_A0G_REGNUM
:
2410 case SIM_SH_A0_REGNUM
:
2413 case SIM_SH_A1G_REGNUM
:
2416 case SIM_SH_A1_REGNUM
:
2419 case SIM_SH_M0_REGNUM
:
2422 case SIM_SH_M1_REGNUM
:
2425 case SIM_SH_X0_REGNUM
:
2428 case SIM_SH_X1_REGNUM
:
2431 case SIM_SH_Y0_REGNUM
:
2434 case SIM_SH_Y1_REGNUM
:
2437 case SIM_SH_MOD_REGNUM
:
2440 case SIM_SH_RS_REGNUM
:
2443 case SIM_SH_RE_REGNUM
:
2446 case SIM_SH_SSR_REGNUM
:
2449 case SIM_SH_SPC_REGNUM
:
2452 /* The rn_bank idiosyncracies are not due to hardware differences, but to
2453 a weird aliasing naming scheme for sh3 / sh3e / sh4. */
2454 case SIM_SH_R0_BANK0_REGNUM
: case SIM_SH_R1_BANK0_REGNUM
:
2455 case SIM_SH_R2_BANK0_REGNUM
: case SIM_SH_R3_BANK0_REGNUM
:
2456 case SIM_SH_R4_BANK0_REGNUM
: case SIM_SH_R5_BANK0_REGNUM
:
2457 case SIM_SH_R6_BANK0_REGNUM
: case SIM_SH_R7_BANK0_REGNUM
:
2458 if (saved_state
.asregs
.bfd_mach
== bfd_mach_sh2a
)
2460 rn
-= SIM_SH_R0_BANK0_REGNUM
;
2461 val
= saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[rn
];
2464 val
= (SR_MD
&& SR_RB
2465 ? Rn_BANK (rn
- SIM_SH_R0_BANK0_REGNUM
)
2466 : saved_state
.asregs
.regs
[rn
- SIM_SH_R0_BANK0_REGNUM
]);
2468 case SIM_SH_R0_BANK1_REGNUM
: case SIM_SH_R1_BANK1_REGNUM
:
2469 case SIM_SH_R2_BANK1_REGNUM
: case SIM_SH_R3_BANK1_REGNUM
:
2470 case SIM_SH_R4_BANK1_REGNUM
: case SIM_SH_R5_BANK1_REGNUM
:
2471 case SIM_SH_R6_BANK1_REGNUM
: case SIM_SH_R7_BANK1_REGNUM
:
2472 if (saved_state
.asregs
.bfd_mach
== bfd_mach_sh2a
)
2474 rn
-= SIM_SH_R0_BANK1_REGNUM
;
2475 val
= saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[rn
+ 8];
2478 val
= (! SR_MD
|| ! SR_RB
2479 ? Rn_BANK (rn
- SIM_SH_R0_BANK1_REGNUM
)
2480 : saved_state
.asregs
.regs
[rn
- SIM_SH_R0_BANK1_REGNUM
]);
2482 case SIM_SH_R0_BANK_REGNUM
: case SIM_SH_R1_BANK_REGNUM
:
2483 case SIM_SH_R2_BANK_REGNUM
: case SIM_SH_R3_BANK_REGNUM
:
2484 case SIM_SH_R4_BANK_REGNUM
: case SIM_SH_R5_BANK_REGNUM
:
2485 case SIM_SH_R6_BANK_REGNUM
: case SIM_SH_R7_BANK_REGNUM
:
2486 val
= Rn_BANK (rn
- SIM_SH_R0_BANK_REGNUM
);
2488 case SIM_SH_TBR_REGNUM
:
2491 case SIM_SH_IBNR_REGNUM
:
2494 case SIM_SH_IBCR_REGNUM
:
2497 case SIM_SH_BANK_REGNUM
:
2498 /* This is a pseudo-register maintained just for gdb.
2499 It tells us what register bank gdb would like to read/write. */
2500 val
= gdb_bank_number
;
2502 case SIM_SH_BANK_MACL_REGNUM
:
2503 val
= saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[REGBANK_MACL
];
2505 case SIM_SH_BANK_GBR_REGNUM
:
2506 val
= saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[REGBANK_GBR
];
2508 case SIM_SH_BANK_PR_REGNUM
:
2509 val
= saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[REGBANK_PR
];
2511 case SIM_SH_BANK_IVN_REGNUM
:
2512 val
= saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[REGBANK_IVN
];
2514 case SIM_SH_BANK_MACH_REGNUM
:
2515 val
= saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[REGBANK_MACH
];
2520 * (int *) memory
= swap (val
);
2529 sim_resume (sd
, 0, 0);
2535 sim_stop_reason (sd
, reason
, sigrc
)
2537 enum sim_stop
*reason
;
2540 /* The SH simulator uses SIGQUIT to indicate that the program has
2541 exited, so we must check for it here and translate it to exit. */
2542 if (saved_state
.asregs
.exception
== SIGQUIT
)
2544 *reason
= sim_exited
;
2545 *sigrc
= saved_state
.asregs
.regs
[5];
2549 *reason
= sim_stopped
;
2550 *sigrc
= saved_state
.asregs
.exception
;
2555 sim_info (sd
, verbose
)
2560 (double) saved_state
.asregs
.ticks
/ (double) now_persec ();
2561 double virttime
= saved_state
.asregs
.cycles
/ 36.0e6
;
2563 callback
->printf_filtered (callback
, "\n\n# instructions executed %10d\n",
2564 saved_state
.asregs
.insts
);
2565 callback
->printf_filtered (callback
, "# cycles %10d\n",
2566 saved_state
.asregs
.cycles
);
2567 callback
->printf_filtered (callback
, "# pipeline stalls %10d\n",
2568 saved_state
.asregs
.stalls
);
2569 callback
->printf_filtered (callback
, "# misaligned load/store %10d\n",
2570 saved_state
.asregs
.memstalls
);
2571 callback
->printf_filtered (callback
, "# real time taken %10.4f\n",
2573 callback
->printf_filtered (callback
, "# virtual time taken %10.4f\n",
2575 callback
->printf_filtered (callback
, "# profiling size %10d\n",
2577 callback
->printf_filtered (callback
, "# profiling frequency %10d\n",
2578 saved_state
.asregs
.profile
);
2579 callback
->printf_filtered (callback
, "# profile maxpc %10x\n",
2580 (1 << sim_profile_size
) << PROFILE_SHIFT
);
2584 callback
->printf_filtered (callback
, "# cycles/second %10d\n",
2585 (int) (saved_state
.asregs
.cycles
/ timetaken
));
2586 callback
->printf_filtered (callback
, "# simulation ratio %10.4f\n",
2587 virttime
/ timetaken
);
2595 saved_state
.asregs
.profile
= n
;
2599 sim_set_profile_size (n
)
2602 sim_profile_size
= n
;
2606 sim_open (kind
, cb
, abfd
, argv
)
2627 for (p
= argv
+ 1; *p
!= NULL
; ++p
)
2629 if (strcmp (*p
, "-E") == 0)
2634 /* FIXME: This doesn't use stderr, but then the rest of the
2635 file doesn't either. */
2636 callback
->printf_filtered (callback
, "Missing argument to `-E'.\n");
2639 target_little_endian
= strcmp (*p
, "big") != 0;
2642 else if (isdigit (**p
))
2643 parse_and_set_memory_size (*p
);
2646 if (abfd
!= NULL
&& ! endian_set
)
2647 target_little_endian
= ! bfd_big_endian (abfd
);
2652 for (i
= 4; (i
-= 2) >= 0; )
2653 mem_word
.s
[i
>> 1] = i
;
2654 global_endianw
= mem_word
.i
>> (target_little_endian
? 0 : 16) & 0xffff;
2656 for (i
= 4; --i
>= 0; )
2658 endianb
= mem_word
.i
>> (target_little_endian
? 0 : 24) & 0xff;
2660 /* fudge our descriptor for now */
2661 return (SIM_DESC
) 1;
2665 parse_and_set_memory_size (str
)
2670 n
= strtol (str
, NULL
, 10);
2671 if (n
> 0 && n
<= 24)
2672 sim_memory_size
= n
;
2674 callback
->printf_filtered (callback
, "Bad memory size %d; must be 1 to 24, inclusive\n", n
);
2678 sim_close (sd
, quitting
)
2686 sim_load (sd
, prog
, abfd
, from_tty
)
2692 extern bfd
*sim_load_file (); /* ??? Don't know where this should live. */
2695 prog_bfd
= sim_load_file (sd
, myname
, callback
, prog
, abfd
,
2696 sim_kind
== SIM_OPEN_DEBUG
,
2699 /* Set the bfd machine type. */
2701 saved_state
.asregs
.bfd_mach
= bfd_get_mach (prog_bfd
);
2703 saved_state
.asregs
.bfd_mach
= bfd_get_mach (abfd
);
2705 saved_state
.asregs
.bfd_mach
= 0;
2707 if (prog_bfd
== NULL
)
2710 bfd_close (prog_bfd
);
2715 sim_create_inferior (sd
, prog_bfd
, argv
, env
)
2717 struct bfd
*prog_bfd
;
2721 /* Clear the registers. */
2722 memset (&saved_state
, 0,
2723 (char*) &saved_state
.asregs
.end_of_registers
- (char*) &saved_state
);
2726 if (prog_bfd
!= NULL
)
2727 saved_state
.asregs
.pc
= bfd_get_start_address (prog_bfd
);
2729 /* Set the bfd machine type. */
2730 if (prog_bfd
!= NULL
)
2731 saved_state
.asregs
.bfd_mach
= bfd_get_mach (prog_bfd
);
2733 /* Record the program's arguments. */
2740 sim_do_command (sd
, cmd
)
2744 char *sms_cmd
= "set-memory-size";
2747 if (cmd
== NULL
|| *cmd
== '\0')
2752 cmdsize
= strlen (sms_cmd
);
2753 if (strncmp (cmd
, sms_cmd
, cmdsize
) == 0
2754 && strchr (" \t", cmd
[cmdsize
]) != NULL
)
2756 parse_and_set_memory_size (cmd
+ cmdsize
+ 1);
2758 else if (strcmp (cmd
, "help") == 0)
2760 (callback
->printf_filtered
) (callback
,
2761 "List of SH simulator commands:\n\n");
2762 (callback
->printf_filtered
) (callback
, "set-memory-size <n> -- Set the number of address bits to use\n");
2763 (callback
->printf_filtered
) (callback
, "\n");
2767 (callback
->printf_filtered
) (callback
, "Error: \"%s\" is not a valid SH simulator command.\n", cmd
);
2772 sim_set_callbacks (p
)
2779 sim_complete_command (SIM_DESC sd
, const char *text
, const char *word
)