sim/sh/interp.c

   1 /* Simulator for the Hitachi SH architecture.
   2
   3    Written by Steve Chamberlain of Cygnus Support.
   4    sac@cygnus.com
   5
   6    This file is part of SH sim
   7
   8
   9                 THIS SOFTWARE IS NOT COPYRIGHTED
  10
  11    Cygnus offers the following for use in the public domain.  Cygnus
  12    makes no warranty with regard to the software or it's performance
  13    and the user accepts the software "AS IS" with all faults.
  14
  15    CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
  16    THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  17    MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
  18
  19 */
  20
  21 #include <signal.h>
  22
  23 #include "sysdep.h"
  24 #include "bfd.h"
  25 #include "remote-sim.h"
  26
  27 #include "callback.h"
  28 /* This file is local - if newlib changes, then so should this.  */
  29 #include "syscall.h"
  30
  31 /* start-sanitize-sh3e */
  32 #include <math.h>
  33 /* end-sanitize-sh3e */
  34
  35 #ifndef SIGBUS
  36 #define SIGBUS SIGSEGV
  37 #endif
  38
  39 #ifndef SIGQUIT
  40 #define SIGQUIT SIGTERM
  41 #endif
  42
  43 #define O_RECOMPILE 85
  44 #define DEFINE_TABLE
  45 #define DISASSEMBLER_TABLE
  46
  47
  48
  49 #define SBIT(x) ((x)&sbit)
  50 #define R0      saved_state.asregs.regs[0]
  51 #define Rn      saved_state.asregs.regs[n]
  52 #define Rm      saved_state.asregs.regs[m]
  53 #define UR0     (unsigned int)(saved_state.asregs.regs[0])
  54 #define UR      (unsigned int)R
  55 #define UR      (unsigned int)R
  56 #define SR0     saved_state.asregs.regs[0]
  57 #define GBR     saved_state.asregs.gbr
  58 #define VBR     saved_state.asregs.vbr
  59 #define MACH    saved_state.asregs.mach
  60 #define MACL    saved_state.asregs.macl
  61 #define M       saved_state.asregs.sr.bits.m
  62 #define Q       saved_state.asregs.sr.bits.q
  63 #define S       saved_state.asregs.sr.bits.s
  64 /* start-sanitize-sh3e */
  65 #define FPSCR   saved_state.asregs.fpscr
  66 #define FPUL    saved_state.asregs.fpul
  67 /* end-sanitize-sh3e */
  68
  69 #define GET_SR() (saved_state.asregs.sr.bits.t = T, saved_state.asregs.sr.word)
  70 #define SET_SR(x) {saved_state.asregs.sr.word = (x); T =saved_state.asregs.sr.bits.t;}
  71
  72 #define PC pc
  73 #define C cycles
  74
  75 int
  76 fail ()
  77 {
  78   abort ();
  79 }
  80
  81 #define BUSERROR(addr, mask) \
  82   if (addr & ~mask)  { saved_state.asregs.exception = SIGBUS;}
  83
  84 /* Define this to enable register lifetime checking.
  85    The compiler generates "add #0,rn" insns to mark registers as invalid,
  86    the simulator uses this info to call fail if it finds a ref to an invalid
  87    register before a def
  88
  89    #define PARANOID
  90 */
  91
  92 #ifdef PARANOID
  93 int valid[16];
  94 #define CREF(x)  if(!valid[x]) fail();
  95 #define CDEF(x)  valid[x] = 1;
  96 #define UNDEF(x) valid[x] = 0;
  97 #else
  98 #define CREF(x)
  99 #define CDEF(x)
 100 #define UNDEF(x)
 101 #endif
 102
 103 static void parse_and_set_memory_size PARAMS ((char *str));
 104
 105 static int IOMEM PARAMS ((int addr, int write, int value));
 106
 107
 108 static host_callback *callback = &default_callback;
 109 /* These variables are at file scope so that functions other than
 110    sim_resume can use the fetch/store macros */
 111
 112 static int  little_endian;
 113
 114
 115
 116 #if 1
 117 static int maskl = ~0;
 118 static int maskw = ~0;
 119 #endif
 120 typedef union
 121 {
 122
 123   struct
 124   {
 125
 126     int regs[16];
 127     int pc;
 128     int pr;
 129
 130     int gbr;
 131     int vbr;
 132     int mach;
 133     int macl;
 134
 135     union
 136       {
 137         struct
 138           {
 139             unsigned int d0:22;
 140             unsigned int m:1;
 141             unsigned int q:1;
 142             unsigned int i:4;
 143             unsigned int d1:2;
 144             unsigned int s:1;
 145             unsigned int t:1;
 146           }
 147         bits;
 148         int word;
 149       }
 150     sr;
 151     int ticks;
 152     int stalls;
 153     int cycles;
 154     int insts;
 155
 156
 157     int prevlock;
 158     int thislock;
 159 /* start-sanitize-sh3e */
 160     float fregs[16];
 161     float fpscr;
 162     int fpul;
 163 /* end-sanitize-sh3e */
 164     int exception;
 165     int msize;
 166 #define PROFILE_FREQ 1
 167 #define PROFILE_SHIFT 2
 168     int profile;
 169     unsigned short *profile_hist;
 170     unsigned char *memory;
 171   }
 172   asregs;
 173   int asints[28];
 174 } saved_state_type;
 175 saved_state_type saved_state;
 176
 177 static void INLINE
 178 wlat_little (memory, x, value, maskl)
 179      unsigned char *memory;
 180 {
 181   int v = value;
 182   unsigned char *p = memory + ((x) & maskl);
 183   BUSERROR(x, maskl);
 184   p[3] = v >> 24;
 185   p[2] = v >> 16;
 186   p[1] = v >> 8;
 187   p[0] = v;
 188 }
 189
 190 static void INLINE
 191 wwat_little (memory, x, value, maskw)
 192      unsigned char *memory;
 193 {
 194   int v = value;
 195   unsigned char *p = memory + ((x) & maskw);
 196   BUSERROR(x, maskw);
 197
 198   p[1] = v >> 8;
 199   p[0] = v;
 200 }
 201
 202
 203 static void INLINE
 204 wbat_any (memory, x, value, maskb)
 205      unsigned char *memory;
 206 {
 207   unsigned char *p = memory + (x & maskb);
 208   if (x > 0x5000000)
 209     IOMEM (x, 1, value);
 210   BUSERROR(x, maskb);
 211
 212   p[0] = value;
 213 }
 214
 215
 216
 217 static void INLINE
 218 wlat_big (memory, x, value, maskl)
 219      unsigned char *memory;
 220 {
 221   int v = value;
 222   unsigned char *p = memory + ((x) & maskl);
 223   BUSERROR(x, maskl);
 224
 225   p[0] = v >> 24;
 226   p[1] = v >> 16;
 227   p[2] = v >> 8;
 228   p[3] = v;
 229 }
 230
 231 static void INLINE
 232 wwat_big (memory, x, value, maskw)
 233      unsigned char *memory;
 234 {
 235   int v = value;
 236   unsigned char *p = memory + ((x) & maskw);
 237   BUSERROR(x, maskw);
 238
 239   p[0] = v >> 8;
 240   p[1] = v;
 241 }
 242
 243
 244 static void INLINE
 245 wbat_big (memory, x, value, maskb)
 246      unsigned char *memory;
 247 {
 248   unsigned char *p = memory + (x & maskb);
 249   BUSERROR(x, maskb);
 250
 251   if (x > 0x5000000)
 252     IOMEM (x, 1, value);
 253   p[0] = value;
 254 }
 255
 256
 257
 258 /* Read functions */
 259 static int INLINE
 260 rlat_little (memory, x, maskl)
 261      unsigned char *memory;
 262 {
 263   unsigned char *p = memory + ((x) & maskl);
 264   BUSERROR(x, maskl);
 265
 266   return (p[3] << 24) | (p[2] << 16) | (p[1] << 8) | p[0];
 267
 268 }
 269
 270 static int INLINE
 271 rwat_little (memory, x, maskw)
 272      unsigned char *memory;
 273 {
 274   unsigned char *p = memory + ((x) & maskw);
 275   BUSERROR(x, maskw);
 276
 277   return (p[1] << 8) | p[0];
 278 }
 279
 280 static int INLINE
 281 rbat_any (memory, x, maskb)
 282      unsigned char *memory;
 283 {
 284   unsigned char *p = memory + ((x) & maskb);
 285   BUSERROR(x, maskb);
 286
 287   return p[0];
 288 }
 289
 290 static int INLINE
 291 rlat_big (memory, x, maskl)
 292      unsigned char *memory;
 293 {
 294   unsigned char *p = memory + ((x) & maskl);
 295   BUSERROR(x, maskl);
 296
 297   return (p[0] << 24) | (p[1] << 16) | (p[2] << 8) | p[3];
 298
 299 }
 300
 301 static int INLINE
 302 rwat_big (memory, x, maskw)
 303      unsigned char *memory;
 304 {
 305   unsigned char *p = memory + ((x) & maskw);
 306   BUSERROR(x, maskw);
 307
 308   return (p[0] << 8) | p[1];
 309 }
 310
 311
 312 #define RWAT(x)         (little_endian ? rwat_little(memory, x, maskw): rwat_big(memory, x, maskw))
 313 #define RLAT(x)         (little_endian ? rlat_little(memory, x, maskl): rlat_big(memory, x, maskl))
 314 #define RBAT(x)         (rbat_any (memory, x, maskb))
 315 #define WWAT(x,v)       (little_endian ? wwat_little(memory, x, v, maskw): wwat_big(memory, x, v, maskw))
 316 #define WLAT(x,v)       (little_endian ? wlat_little(memory, x, v, maskl): wlat_big(memory, x, v, maskl))
 317 #define WBAT(x,v)       (wbat_any (memory, x, v, maskb))
 318
 319 #define RUWAT(x)  (RWAT(x) & 0xffff)
 320 #define RSWAT(x)  ((short)(RWAT(x)))
 321 #define RSBAT(x)  (SEXT(RBAT(x)))
 322
 323 #define SEXT(x)         (((x&0xff) ^ (~0x7f))+0x80)
 324 #define SEXTW(y)        ((int)((short)y))
 325
 326 #define SL(TEMPPC)      iword= RUWAT(TEMPPC); goto top;
 327
 328
 329 int empty[16];
 330
 331 #define L(x)   thislock = x;
 332 #define TL(x)  if ((x) == prevlock) stalls++;
 333 #define TB(x,y)  if ((x) == prevlock || (y)==prevlock) stalls++;
 334
 335 #if defined(__GO32__) || defined(WIN32)
 336 int sim_memory_size = 19;
 337 #else
 338 int sim_memory_size = 24;
 339 #endif
 340
 341 static int sim_profile_size = 17;
 342 static int nsamples;
 343
 344 #undef TB
 345 #define TB(x,y)
 346
 347 #define SMR1 (0x05FFFEC8)       /* Channel 1  serial mode register */
 348 #define BRR1 (0x05FFFEC9)       /* Channel 1  bit rate register */
 349 #define SCR1 (0x05FFFECA)       /* Channel 1  serial control register */
 350 #define TDR1 (0x05FFFECB)       /* Channel 1  transmit data register */
 351 #define SSR1 (0x05FFFECC)       /* Channel 1  serial status register */
 352 #define RDR1 (0x05FFFECD)       /* Channel 1  receive data register */
 353
 354 #define SCI_RDRF         0x40   /* Recieve data register full */
 355 #define SCI_TDRE        0x80    /* Transmit data register empty */
 356
 357 static int
 358 IOMEM (addr, write, value)
 359      int addr;
 360      int write;
 361      int value;
 362 {
 363   static int io;
 364   static char ssr1;
 365   int x;
 366   static char lastchar;
 367
 368   if (write)
 369     {
 370       switch (addr)
 371         {
 372         case TDR1:
 373           if (value != '\r')
 374             {
 375               putchar (value);
 376               fflush (stdout);
 377             }
 378           break;
 379         }
 380     }
 381   else
 382     {
 383       switch (addr)
 384         {
 385         case RDR1:
 386           return getchar ();
 387         }
 388     }
 389 }
 390
 391
 392
 393 static int
 394 get_now ()
 395 {
 396   return time ((long *) 0);
 397 }
 398
 399 static int
 400 now_persec ()
 401 {
 402   return 1;
 403 }
 404
 405
 406
 407 static FILE *profile_file;
 408
 409 static void
 410 swap (memory, n)
 411      unsigned char *memory;
 412      int n;
 413 {
 414   WLAT (0, n);
 415 }
 416 static void
 417 swap16 (memory, n)
 418      unsigned char *memory;
 419      int n;
 420 {
 421   WWAT (0, n);
 422 }
 423
 424 static void
 425 swapout (n)
 426      int n;
 427 {
 428   if (profile_file)
 429     {
 430       char b[4];
 431       swap (b, n);
 432       fwrite (b, 4, 1, profile_file);
 433     }
 434 }
 435
 436 static void
 437 swapout16 (n)
 438      int n;
 439 {
 440   char b[4];
 441   swap16 (b, n);
 442   fwrite (b, 2, 1, profile_file);
 443 }
 444
 445
 446 /* Turn a pointer in a register into a pointer into real memory. */
 447
 448 static char *
 449 ptr (x)
 450      int x;
 451 {
 452   return (char *) (x + saved_state.asregs.memory);
 453 }
 454
 455
 456 /* Simulate a monitor trap, put the result into r0 and errno into r1 */
 457 static void
 458 trap (i, regs, memory, maskl, maskw, little_endian)
 459      int i;
 460      int *regs;
 461      unsigned char *memory;
 462 {
 463   switch (i)
 464     {
 465     case 1:
 466       printf ("%c", regs[0]);
 467       break;
 468     case 2:
 469       saved_state.asregs.exception = SIGQUIT;
 470       break;
 471     case 3:                     /* FIXME: for backwards compat, should be removed */
 472     case 34:
 473       {
 474         extern int errno;
 475         int perrno = errno;
 476         errno = 0;
 477
 478         switch (regs[4])
 479           {
 480
 481 #if !defined(__GO32__) && !defined(WIN32)
 482           case SYS_fork:
 483             regs[0] = fork ();
 484             break;
 485           case SYS_execve:
 486             regs[0] = execve (ptr (regs[5]), (char **)ptr (regs[6]), (char **)ptr (regs[7]));
 487             break;
 488           case SYS_execv:
 489             regs[0] = execve (ptr (regs[5]),(char **) ptr (regs[6]), 0);
 490             break;
 491           case SYS_pipe:
 492             {
 493               char *buf;
 494               int host_fd[2];
 495
 496               buf = ptr (regs[5]);
 497
 498               regs[0] = pipe (host_fd);
 499
 500               WLAT (buf, host_fd[0]);
 501               buf += 4;
 502               WLAT (buf, host_fd[1]);
 503             }
 504             break;
 505
 506           case SYS_wait:
 507             regs[0] = wait (ptr (regs[5]));
 508             break;
 509 #endif
 510
 511           case SYS_read:
 512             regs[0] = callback->read (callback, regs[5], ptr (regs[6]), regs[7]);
 513             break;
 514           case SYS_write:
 515             if (regs[5] == 1)
 516               regs[0] = (int)callback->write_stdout (callback, ptr(regs[6]), regs[7]);
 517             else
 518               regs[0] = (int)callback->write (callback, regs[5], ptr (regs[6]), regs[7]);
 519             break;
 520           case SYS_lseek:
 521             regs[0] = callback->lseek (callback,regs[5], regs[6], regs[7]);
 522             break;
 523           case SYS_close:
 524             regs[0] = callback->close (callback,regs[5]);
 525             break;
 526           case SYS_open:
 527             regs[0] = callback->open (callback,ptr (regs[5]), regs[6]);
 528             break;
 529           case SYS_exit:
 530             /* EXIT - caller can look in r5 to work out the
 531                reason */
 532             saved_state.asregs.exception = SIGQUIT;
 533             break;
 534
 535           case SYS_stat:        /* added at hmsi */
 536             /* stat system call */
 537             {
 538               struct stat host_stat;
 539               char *buf;
 540
 541               regs[0] = stat (ptr (regs[5]), &host_stat);
 542
 543               buf = ptr (regs[6]);
 544
 545               WWAT (buf, host_stat.st_dev);
 546               buf += 2;
 547               WWAT (buf, host_stat.st_ino);
 548               buf += 2;
 549               WLAT (buf, host_stat.st_mode);
 550               buf += 4;
 551               WWAT (buf, host_stat.st_nlink);
 552               buf += 2;
 553               WWAT (buf, host_stat.st_uid);
 554               buf += 2;
 555               WWAT (buf, host_stat.st_gid);
 556               buf += 2;
 557               WWAT (buf, host_stat.st_rdev);
 558               buf += 2;
 559               WLAT (buf, host_stat.st_size);
 560               buf += 4;
 561               WLAT (buf, host_stat.st_atime);
 562               buf += 4;
 563               WLAT (buf, 0);
 564               buf += 4;
 565               WLAT (buf, host_stat.st_mtime);
 566               buf += 4;
 567               WLAT (buf, 0);
 568               buf += 4;
 569               WLAT (buf, host_stat.st_ctime);
 570               buf += 4;
 571               WLAT (buf, 0);
 572               buf += 4;
 573               WLAT (buf, 0);
 574               buf += 4;
 575               WLAT (buf, 0);
 576               buf += 4;
 577             }
 578             break;
 579
 580           case SYS_chown:
 581             regs[0] = chown (ptr (regs[5]), regs[6], regs[7]);
 582             break;
 583           case SYS_chmod:
 584             regs[0] = chmod (ptr (regs[5]), regs[6]);
 585             break;
 586           case SYS_utime:
 587             /* Cast the second argument to void *, to avoid type mismatch
 588                if a prototype is present.  */
 589             regs[0] = utime (ptr (regs[5]), (void *) ptr (regs[6]));
 590             break;
 591           default:
 592             abort ();
 593           }
 594         regs[1] = errno;
 595         errno = perrno;
 596       }
 597       break;
 598
 599     case 0xc3:
 600     case 255:
 601       saved_state.asregs.exception = SIGTRAP;
 602       break;
 603     }
 604
 605 }
 606 void
 607 control_c (sig, code, scp, addr)
 608      int sig;
 609      int code;
 610      char *scp;
 611      char *addr;
 612 {
 613   saved_state.asregs.exception = SIGINT;
 614 }
 615
 616
 617 static int
 618 div1 (R, iRn2, iRn1, T)
 619      int *R;
 620      int iRn1;
 621      int iRn2;
 622      int T;
 623 {
 624   unsigned long tmp0;
 625   unsigned char old_q, tmp1;
 626
 627   old_q = Q;
 628   Q = (unsigned char) ((0x80000000 & R[iRn1]) != 0);
 629   R[iRn1] <<= 1;
 630   R[iRn1] |= (unsigned long) T;
 631
 632   switch (old_q)
 633     {
 634     case 0:
 635       switch (M)
 636         {
 637         case 0:
 638           tmp0 = R[iRn1];
 639           R[iRn1] -= R[iRn2];
 640           tmp1 = (R[iRn1] > tmp0);
 641           switch (Q)
 642             {
 643             case 0:
 644               Q = tmp1;
 645               break;
 646             case 1:
 647               Q = (unsigned char) (tmp1 == 0);
 648               break;
 649             }
 650           break;
 651         case 1:
 652           tmp0 = R[iRn1];
 653           R[iRn1] += R[iRn2];
 654           tmp1 = (R[iRn1] < tmp0);
 655           switch (Q)
 656             {
 657             case 0:
 658               Q = (unsigned char) (tmp1 == 0);
 659               break;
 660             case 1:
 661               Q = tmp1;
 662               break;
 663             }
 664           break;
 665         }
 666       break;
 667     case 1:
 668       switch (M)
 669         {
 670         case 0:
 671           tmp0 = R[iRn1];
 672           R[iRn1] += R[iRn2];
 673           tmp1 = (R[iRn1] < tmp0);
 674           switch (Q)
 675             {
 676             case 0:
 677               Q = tmp1;
 678               break;
 679             case 1:
 680               Q = (unsigned char) (tmp1 == 0);
 681               break;
 682             }
 683           break;
 684         case 1:
 685           tmp0 = R[iRn1];
 686           R[iRn1] -= R[iRn2];
 687           tmp1 = (R[iRn1] > tmp0);
 688           switch (Q)
 689             {
 690             case 0:
 691               Q = (unsigned char) (tmp1 == 0);
 692               break;
 693             case 1:
 694               Q = tmp1;
 695               break;
 696             }
 697           break;
 698         }
 699       break;
 700     }
 701   T = (Q == M);
 702   return T;
 703 }
 704
 705
 706 static void
 707 dmul (sign, rm, rn)
 708      int sign;
 709      unsigned int rm;
 710      unsigned int rn;
 711 {
 712   unsigned long RnL, RnH;
 713   unsigned long RmL, RmH;
 714   unsigned long temp0, temp1, temp2, temp3;
 715   unsigned long Res2, Res1, Res0;
 716
 717   RnL = rn & 0xffff;
 718   RnH = (rn >> 16) & 0xffff;
 719   RmL = rm & 0xffff;
 720   RmH = (rm >> 16) & 0xffff;
 721   temp0 = RmL * RnL;
 722   temp1 = RmH * RnL;
 723   temp2 = RmL * RnH;
 724   temp3 = RmH * RnH;
 725   Res2 = 0;
 726   Res1 = temp1 + temp2;
 727   if (Res1 < temp1)
 728     Res2 += 0x00010000;
 729   temp1 = (Res1 << 16) & 0xffff0000;
 730   Res0 = temp0 + temp1;
 731   if (Res0 < temp0)
 732     Res2 += 1;
 733   Res2 += ((Res1 >> 16) & 0xffff) + temp3;
 734
 735   if (sign)
 736     {
 737       if (rn & 0x80000000)
 738         Res2 -= rm;
 739       if (rm & 0x80000000)
 740         Res2 -= rn;
 741     }
 742
 743   MACH = Res2;
 744   MACL = Res0;
 745 }
 746
 747 static void
 748 macw (regs, memory, n, m)
 749      int *regs;
 750      unsigned char *memory;
 751      int m, n;
 752 {
 753   long tempm, tempn;
 754   long prod, macl, sum;
 755
 756   tempm=RSWAT(regs[m]); regs[m]+=2;
 757   tempn=RSWAT(regs[n]); regs[n]+=2;
 758
 759   macl = MACL;
 760   prod = (long)(short) tempm * (long)(short) tempn;
 761   sum = prod + macl;
 762   if (S)
 763     {
 764       if ((~(prod ^ macl) & (sum ^ prod)) < 0)
 765         {
 766           /* MACH's lsb is a sticky overflow bit.  */
 767           MACH |= 1;
 768           /* Store the smallest negative number in MACL if prod is
 769              negative, and the largest positive number otherwise.  */
 770           sum = 0x7fffffff + (prod < 0);
 771         }
 772     }
 773   else
 774     {
 775       long mach;
 776       /* Add to MACH the sign extended product, and carry from low sum.  */
 777       mach = MACH + (-(prod < 0)) + ((unsigned long) sum < prod);
 778       /* Sign extend at 10:th bit in MACH.  */
 779       MACH = (mach & 0x1ff) | -(mach & 0x200);
 780     }
 781   MACL = sum;
 782 }
 783
 784 /* Set the memory size to the power of two provided. */
 785
 786 void
 787 sim_size (power)
 788      int power;
 789
 790 {
 791   saved_state.asregs.msize = 1 << power;
 792
 793   sim_memory_size = power;
 794
 795
 796   if (saved_state.asregs.memory)
 797     {
 798       free (saved_state.asregs.memory);
 799     }
 800
 801   saved_state.asregs.memory =
 802     (unsigned char *) calloc (64, saved_state.asregs.msize / 64);
 803
 804   if (!saved_state.asregs.memory)
 805     {
 806       fprintf (stderr,
 807                "Not enough VM for simulation of %d bytes of RAM\n",
 808                saved_state.asregs.msize);
 809
 810       saved_state.asregs.msize = 1;
 811       saved_state.asregs.memory = (unsigned char *) calloc (1, 1);
 812     }
 813 }
 814
 815
 816 int target_byte_order;
 817
 818 static void
 819 set_static_little_endian(x)
 820 int x;
 821 {
 822   little_endian = x;
 823 }
 824
 825 static
 826 void
 827 init_pointers ()
 828 {
 829   register int little_endian = target_byte_order == 1234;
 830   set_static_little_endian (little_endian);
 831   if (saved_state.asregs.msize != 1 << sim_memory_size)
 832     {
 833       sim_size (sim_memory_size);
 834     }
 835
 836   if (saved_state.asregs.profile && !profile_file)
 837     {
 838       profile_file = fopen ("gmon.out", "wb");
 839       /* Seek to where to put the call arc data */
 840       nsamples = (1 << sim_profile_size);
 841
 842       fseek (profile_file, nsamples * 2 + 12, 0);
 843
 844       if (!profile_file)
 845         {
 846           fprintf (stderr, "Can't open gmon.out\n");
 847         }
 848       else
 849         {
 850           saved_state.asregs.profile_hist =
 851             (unsigned short *) calloc (64, (nsamples * sizeof (short) / 64));
 852         }
 853     }
 854 }
 855
 856 static void
 857 dump_profile ()
 858 {
 859   unsigned int minpc;
 860   unsigned int maxpc;
 861   unsigned short *p;
 862
 863   int thisshift;
 864
 865   unsigned short *first;
 866
 867   int i;
 868   p = saved_state.asregs.profile_hist;
 869   minpc = 0;
 870   maxpc = (1 << sim_profile_size);
 871
 872   fseek (profile_file, 0L, 0);
 873   swapout (minpc << PROFILE_SHIFT);
 874   swapout (maxpc << PROFILE_SHIFT);
 875   swapout (nsamples * 2 + 12);
 876   for (i = 0; i < nsamples; i++)
 877     swapout16 (saved_state.asregs.profile_hist[i]);
 878
 879 }
 880
 881 static int
 882 gotcall (from, to)
 883      int from;
 884      int to;
 885 {
 886   swapout (from);
 887   swapout (to);
 888   swapout (1);
 889 }
 890
 891 #define MMASKB ((saved_state.asregs.msize -1) & ~0)
 892
 893
 894 void
 895 sim_resume (step, siggnal)
 896      int step, siggnal;
 897 {
 898   register unsigned int pc;
 899   register int cycles = 0;
 900   register int stalls = 0;
 901   register int insts = 0;
 902   register int prevlock;
 903   register int thislock;
 904   register unsigned int doprofile;
 905 #if defined(__GO32__) || defined(WIN32)
 906   register int pollcount = 0;
 907 #endif
 908   register int little_endian = target_byte_order == 1234;
 909
 910
 911   int tick_start = get_now ();
 912   void (*prev) ();
 913   extern unsigned char sh_jump_table0[];
 914
 915   register unsigned char *jump_table = sh_jump_table0;
 916
 917   register int *R = &(saved_state.asregs.regs[0]);
 918 /* start-sanitize-sh3e */
 919   register float *F = &(saved_state.asregs.fregs[0]);
 920 /* end-sanitize-sh3e */
 921   register int T;
 922   register int PR;
 923
 924   register int maskb = ((saved_state.asregs.msize - 1) & ~0);
 925   register int maskw = ((saved_state.asregs.msize - 1) & ~1);
 926   register int maskl = ((saved_state.asregs.msize - 1) & ~3);
 927   register unsigned char *memory;
 928   register unsigned int sbit = ((unsigned int) 1 << 31);
 929
 930   prev = signal (SIGINT, control_c);
 931
 932   init_pointers ();
 933
 934   memory = saved_state.asregs.memory;
 935
 936   if (step)
 937     {
 938       saved_state.asregs.exception = SIGTRAP;
 939     }
 940   else
 941     {
 942       saved_state.asregs.exception = 0;
 943     }
 944
 945   pc = saved_state.asregs.pc;
 946   PR = saved_state.asregs.pr;
 947   T = saved_state.asregs.sr.bits.t;
 948   prevlock = saved_state.asregs.prevlock;
 949   thislock = saved_state.asregs.thislock;
 950   doprofile = saved_state.asregs.profile;
 951
 952   /* If profiling not enabled, disable it by asking for
 953      profiles infrequently. */
 954   if (doprofile == 0)
 955     doprofile = ~0;
 956
 957   do
 958     {
 959       register unsigned int iword = RUWAT (pc);
 960       register unsigned int ult;
 961 #ifndef ACE_FAST
 962       insts++;
 963 #endif
 964     top:
 965
 966 #include "code.c"
 967
 968
 969       pc += 2;
 970
 971 #ifdef __GO32__
 972       pollcount++;
 973       if (pollcount > 1000)
 974         {
 975           pollcount = 0;
 976           if (kbhit()) {
 977             int k = getkey();
 978             if (k == 1)
 979               saved_state.asregs.exception = SIGINT;
 980
 981           }
 982         }
 983 #endif
 984 #if defined (WIN32)
 985       pollcount++;
 986       if (pollcount > 1000)
 987         {
 988           pollcount = 0;
 989           if (win32pollquit())
 990             {
 991               control_c();
 992             }
 993         }
 994 #endif
 995
 996 #ifndef ACE_FAST
 997       prevlock = thislock;
 998       thislock = 30;
 999       cycles++;
1000
1001       if (cycles >= doprofile)
1002         {
1003
1004           saved_state.asregs.cycles += doprofile;
1005           cycles -= doprofile;
1006           if (saved_state.asregs.profile_hist)
1007             {
1008               int n = pc >> PROFILE_SHIFT;
1009               if (n < nsamples)
1010                 {
1011                   int i = saved_state.asregs.profile_hist[n];
1012                   if (i < 65000)
1013                     saved_state.asregs.profile_hist[n] = i + 1;
1014                 }
1015
1016             }
1017         }
1018 #endif
1019     }
1020   while (!saved_state.asregs.exception);
1021
1022   if (saved_state.asregs.exception == SIGILL
1023       || saved_state.asregs.exception == SIGBUS)
1024     {
1025       pc -= 2;
1026     }
1027
1028   saved_state.asregs.ticks += get_now () - tick_start;
1029   saved_state.asregs.cycles += cycles;
1030   saved_state.asregs.stalls += stalls;
1031   saved_state.asregs.insts += insts;
1032   saved_state.asregs.pc = pc;
1033   saved_state.asregs.sr.bits.t = T;
1034   saved_state.asregs.pr = PR;
1035
1036   saved_state.asregs.prevlock = prevlock;
1037   saved_state.asregs.thislock = thislock;
1038
1039
1040   if (profile_file)
1041     {
1042       dump_profile ();
1043     }
1044
1045   signal (SIGINT, prev);
1046 }
1047
1048
1049
1050
1051 int
1052 sim_write (addr, buffer, size)
1053      SIM_ADDR addr;
1054      unsigned char *buffer;
1055      int size;
1056 {
1057   int i;
1058   init_pointers ();
1059
1060   for (i = 0; i < size; i++)
1061     {
1062       saved_state.asregs.memory[MMASKB & (addr + i)] = buffer[i];
1063     }
1064   return size;
1065 }
1066
1067 int
1068 sim_read (addr, buffer, size)
1069      SIM_ADDR addr;
1070      unsigned char *buffer;
1071      int size;
1072 {
1073   int i;
1074
1075   init_pointers ();
1076
1077   for (i = 0; i < size; i++)
1078     {
1079       buffer[i] = saved_state.asregs.memory[MMASKB & (addr + i)];
1080     }
1081   return size;
1082 }
1083
1084
1085 void
1086 sim_store_register (rn, memory)
1087      int rn;
1088      unsigned char *memory;
1089 {
1090   init_pointers();
1091   saved_state.asregs.regs[rn]=RLAT(0);
1092 }
1093
1094 void
1095 sim_fetch_register (rn, memory)
1096      int rn;
1097      unsigned char *memory;
1098 {
1099   init_pointers();
1100   WLAT (0, saved_state.asregs.regs[rn]);
1101 }
1102
1103
1104 int
1105 sim_trace ()
1106 {
1107   return 0;
1108 }
1109
1110 void
1111 sim_stop_reason (reason, sigrc)
1112      enum sim_stop *reason;
1113      int *sigrc;
1114 {
1115   *reason = sim_stopped;
1116   *sigrc = saved_state.asregs.exception;
1117 }
1118
1119
1120 void
1121 sim_info (verbose)
1122      int verbose;
1123 {
1124   double timetaken = (double) saved_state.asregs.ticks / (double) now_persec ();
1125   double virttime = saved_state.asregs.cycles / 36.0e6;
1126
1127   callback->printf_filtered (callback,
1128                               "\n\n# instructions executed  %10d\n",
1129                               saved_state.asregs.insts);
1130   callback->  printf_filtered (callback, "# cycles                 %10d\n", saved_state.asregs.cycles);
1131   callback->  printf_filtered (callback, "# pipeline stalls        %10d\n", saved_state.asregs.stalls);
1132   callback->  printf_filtered (callback, "# real time taken        %10.4f\n", timetaken);
1133   callback->  printf_filtered (callback, "# virtual time taken     %10.4f\n", virttime);
1134   callback->  printf_filtered (callback, "# profiling size         %10d\n", sim_profile_size);
1135   callback->  printf_filtered (callback, "# profiling frequency    %10d\n", saved_state.asregs.profile);
1136   callback->  printf_filtered (callback, "# profile maxpc          %10x\n",
1137                                (1 << sim_profile_size) << PROFILE_SHIFT);
1138
1139   if (timetaken != 0)
1140     {
1141       callback->printf_filtered (callback, "# cycles/second          %10d\n",
1142                                  (int) (saved_state.asregs.cycles / timetaken));
1143       callback->printf_filtered (callback, "# simulation ratio       %10.4f\n",
1144                                  virttime / timetaken);
1145     }
1146 }
1147
1148
1149 void
1150 sim_set_profile (n)
1151      int n;
1152 {
1153   saved_state.asregs.profile = n;
1154 }
1155
1156 void
1157 sim_set_profile_size (n)
1158      int n;
1159 {
1160   sim_profile_size = n;
1161 }
1162
1163
1164 void
1165 sim_open (args)
1166      char *args;
1167 {
1168   int n;
1169
1170   if (args != NULL)
1171     {
1172       parse_and_set_memory_size (args);
1173     }
1174 }
1175
1176 static void
1177 parse_and_set_memory_size (str)
1178      char *str;
1179 {
1180   int n;
1181
1182   n = strtol (str, NULL, 10);
1183   if (n > 0 && n <= 24)
1184     sim_memory_size = n;
1185   else
1186     callback->printf_filtered (callback, "Bad memory size %d; must be 1 to 24, inclusive\n", n);
1187 }
1188
1189 void
1190 sim_close (quitting)
1191      int quitting;
1192 {
1193   /* nothing to do */
1194 }
1195
1196 int
1197 sim_load (prog, from_tty)
1198      char *prog;
1199      int from_tty;
1200 {
1201   /* Return nonzero so GDB will handle it.  */
1202   return 1;
1203 }
1204
1205 void
1206 sim_create_inferior (start_address, argv, env)
1207      SIM_ADDR start_address;
1208      char **argv;
1209      char **env;
1210 {
1211   saved_state.asregs.pc = start_address;
1212 }
1213
1214 void
1215 sim_kill ()
1216 {
1217   /* nothing to do */
1218 }
1219
1220 void
1221 sim_do_command (cmd)
1222      char *cmd;
1223 {
1224   int n;
1225   char *sms_cmd = "set-memory-size";
1226
1227   if (strncmp (cmd, sms_cmd, strlen (sms_cmd)) == 0
1228       && strchr ("      ", cmd[strlen(sms_cmd)]))
1229     parse_and_set_memory_size (cmd + strlen(sms_cmd) + 1);
1230
1231   else if (strcmp (cmd, "help") == 0)
1232     {
1233       callback->printf_filtered (callback,"List of SH simulator commands:\n\n");
1234       callback->printf_filtered (callback,"set-memory-size <n> -- Set the number of address bits to use\n");
1235       callback->printf_filtered (callback,"\n");
1236     }
1237   else
1238     fprintf (stderr, "Error: \"%s\" is not a valid SH simulator command.\n",
1239              cmd);
1240 }
1241
1242
1243 int
1244 sim_get_quit_code()
1245 {
1246   return saved_state.asregs.regs[5];
1247 }
1248
1249
1250
1251 void
1252 sim_set_callbacks(p)
1253      host_callback *p;
1254 {
1255   callback = p;
1256 }