sim/sh64/sh-desc.h

   1 /* CPU data header for sh.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #ifndef SH_CPU_H
  26 #define SH_CPU_H
  27
  28 #define CGEN_ARCH sh
  29
  30 /* Given symbol S, return sh_cgen_<S>.  */
  31 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
  32 #define CGEN_SYM(s) sh##_cgen_##s
  33 #else
  34 #define CGEN_SYM(s) sh/**/_cgen_/**/s
  35 #endif
  36
  37
  38 /* Selected cpu families.  */
  39 #define HAVE_CPU_SH64
  40
  41 #define CGEN_INSN_LSB0_P 1
  42
  43 /* Minimum size of any insn (in bytes).  */
  44 #define CGEN_MIN_INSN_SIZE 2
  45
  46 /* Maximum size of any insn (in bytes).  */
  47 #define CGEN_MAX_INSN_SIZE 4
  48
  49 #define CGEN_INT_INSN_P 1
  50
  51 /* Maximum nymber of syntax bytes in an instruction.  */
  52 #define CGEN_ACTUAL_MAX_SYNTAX_BYTES 22
  53
  54 /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
  55    e.g. In "b,a foo" the ",a" is an operand.  If mnemonics have operands
  56    we can't hash on everything up to the space.  */
  57 #define CGEN_MNEMONIC_OPERANDS
  58
  59 /* Maximum number of fields in an instruction.  */
  60 #define CGEN_ACTUAL_MAX_IFMT_OPERANDS 8
  61
  62 /* Enums.  */
  63
  64 /* Enum declaration for .  */
  65 typedef enum frc_names {
  66   H_FRC_FR0, H_FRC_FR1, H_FRC_FR2, H_FRC_FR3
  67  , H_FRC_FR4, H_FRC_FR5, H_FRC_FR6, H_FRC_FR7
  68  , H_FRC_FR8, H_FRC_FR9, H_FRC_FR10, H_FRC_FR11
  69  , H_FRC_FR12, H_FRC_FR13, H_FRC_FR14, H_FRC_FR15
  70 } FRC_NAMES;
  71
  72 /* Enum declaration for .  */
  73 typedef enum drc_names {
  74   H_DRC_DR0 = 0, H_DRC_DR2 = 2, H_DRC_DR4 = 4, H_DRC_DR6 = 6
  75  , H_DRC_DR8 = 8, H_DRC_DR10 = 10, H_DRC_DR12 = 12, H_DRC_DR14 = 14
  76 } DRC_NAMES;
  77
  78 /* Enum declaration for .  */
  79 typedef enum xf_names {
  80   H_XF_XF0, H_XF_XF1, H_XF_XF2, H_XF_XF3
  81  , H_XF_XF4, H_XF_XF5, H_XF_XF6, H_XF_XF7
  82  , H_XF_XF8, H_XF_XF9, H_XF_XF10, H_XF_XF11
  83  , H_XF_XF12, H_XF_XF13, H_XF_XF14, H_XF_XF15
  84 } XF_NAMES;
  85
  86 /* Attributes.  */
  87
  88 /* Enum declaration for machine type selection.  */
  89 typedef enum mach_attr {
  90   MACH_BASE, MACH_SH2, MACH_SH3, MACH_SH3E
  91  , MACH_SH4, MACH_SH5, MACH_MAX
  92 } MACH_ATTR;
  93
  94 /* Enum declaration for instruction set selection.  */
  95 typedef enum isa_attr {
  96   ISA_COMPACT, ISA_MEDIA, ISA_MAX
  97 } ISA_ATTR;
  98
  99 /* Number of architecture variants.  */
 100 #define MAX_ISAS  ((int) ISA_MAX)
 101 #define MAX_MACHS ((int) MACH_MAX)
 102
 103 /* Ifield support.  */
 104
 105 extern const struct cgen_ifld sh_cgen_ifld_table[];
 106
 107 /* Ifield attribute indices.  */
 108
 109 /* Enum declaration for cgen_ifld attrs.  */
 110 typedef enum cgen_ifld_attr {
 111   CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
 112  , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31
 113  , CGEN_IFLD_MACH, CGEN_IFLD_ISA, CGEN_IFLD_END_NBOOLS
 114 } CGEN_IFLD_ATTR;
 115
 116 /* Number of non-boolean elements in cgen_ifld_attr.  */
 117 #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
 118
 119 /* Enum declaration for sh ifield types.  */
 120 typedef enum ifield_type {
 121   SH_F_NIL, SH_F_ANYOF, SH_F_OP4, SH_F_OP8
 122  , SH_F_OP16, SH_F_SUB4, SH_F_SUB8, SH_F_SUB10
 123  , SH_F_RN, SH_F_RM, SH_F_8_1, SH_F_DISP8
 124  , SH_F_DISP12, SH_F_IMM8, SH_F_IMM4, SH_F_IMM4X2
 125  , SH_F_IMM4X4, SH_F_IMM8X2, SH_F_IMM8X4, SH_F_DN
 126  , SH_F_DM, SH_F_VN, SH_F_VM, SH_F_XN
 127  , SH_F_XM, SH_F_OP, SH_F_EXT, SH_F_RSVD
 128  , SH_F_LEFT, SH_F_RIGHT, SH_F_DEST, SH_F_LEFT_RIGHT
 129  , SH_F_TRA, SH_F_TRB, SH_F_LIKELY, SH_F_25
 130  , SH_F_8_2, SH_F_IMM6, SH_F_IMM10, SH_F_IMM16
 131  , SH_F_UIMM6, SH_F_UIMM16, SH_F_DISP6, SH_F_DISP6X32
 132  , SH_F_DISP10, SH_F_DISP10X8, SH_F_DISP10X4, SH_F_DISP10X2
 133  , SH_F_DISP16, SH_F_MAX
 134 } IFIELD_TYPE;
 135
 136 #define MAX_IFLD ((int) SH_F_MAX)
 137
 138 /* Hardware attribute indices.  */
 139
 140 /* Enum declaration for cgen_hw attrs.  */
 141 typedef enum cgen_hw_attr {
 142   CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
 143  , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
 144 } CGEN_HW_ATTR;
 145
 146 /* Number of non-boolean elements in cgen_hw_attr.  */
 147 #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
 148
 149 /* Enum declaration for sh hardware types.  */
 150 typedef enum cgen_hw_type {
 151   HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
 152  , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_GRC
 153  , HW_H_CR, HW_H_SR, HW_H_FPSCR, HW_H_FRBIT
 154  , HW_H_SZBIT, HW_H_PRBIT, HW_H_SBIT, HW_H_MBIT
 155  , HW_H_QBIT, HW_H_FR, HW_H_FP, HW_H_FV
 156  , HW_H_FMTX, HW_H_DR, HW_H_TR, HW_H_ENDIAN
 157  , HW_H_ISM, HW_H_FRC, HW_H_DRC, HW_H_XF
 158  , HW_H_XD, HW_H_FVC, HW_H_FPCCR, HW_H_GBR
 159  , HW_H_PR, HW_H_MACL, HW_H_MACH, HW_H_TBIT
 160  , HW_MAX
 161 } CGEN_HW_TYPE;
 162
 163 #define MAX_HW ((int) HW_MAX)
 164
 165 /* Operand attribute indices.  */
 166
 167 /* Enum declaration for cgen_operand attrs.  */
 168 typedef enum cgen_operand_attr {
 169   CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
 170  , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
 171  , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_ISA
 172  , CGEN_OPERAND_END_NBOOLS
 173 } CGEN_OPERAND_ATTR;
 174
 175 /* Number of non-boolean elements in cgen_operand_attr.  */
 176 #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
 177
 178 /* Enum declaration for sh operand types.  */
 179 typedef enum cgen_operand_type {
 180   SH_OPERAND_PC, SH_OPERAND_ENDIAN, SH_OPERAND_ISM, SH_OPERAND_RM
 181  , SH_OPERAND_RN, SH_OPERAND_R0, SH_OPERAND_FRN, SH_OPERAND_FRM
 182  , SH_OPERAND_FVN, SH_OPERAND_FVM, SH_OPERAND_DRN, SH_OPERAND_DRM
 183  , SH_OPERAND_IMM4, SH_OPERAND_IMM8, SH_OPERAND_UIMM8, SH_OPERAND_IMM4X2
 184  , SH_OPERAND_IMM4X4, SH_OPERAND_IMM8X2, SH_OPERAND_IMM8X4, SH_OPERAND_DISP8
 185  , SH_OPERAND_DISP12, SH_OPERAND_RM64, SH_OPERAND_RN64, SH_OPERAND_GBR
 186  , SH_OPERAND_PR, SH_OPERAND_FPSCR, SH_OPERAND_TBIT, SH_OPERAND_SBIT
 187  , SH_OPERAND_MBIT, SH_OPERAND_QBIT, SH_OPERAND_FPUL, SH_OPERAND_FRBIT
 188  , SH_OPERAND_SZBIT, SH_OPERAND_PRBIT, SH_OPERAND_MACL, SH_OPERAND_MACH
 189  , SH_OPERAND_FSDM, SH_OPERAND_FSDN, SH_OPERAND_RD, SH_OPERAND_FRG
 190  , SH_OPERAND_FRH, SH_OPERAND_FRF, SH_OPERAND_FRGH, SH_OPERAND_FPF
 191  , SH_OPERAND_FVG, SH_OPERAND_FVH, SH_OPERAND_FVF, SH_OPERAND_MTRXG
 192  , SH_OPERAND_DRG, SH_OPERAND_DRH, SH_OPERAND_DRF, SH_OPERAND_DRGH
 193  , SH_OPERAND_CRJ, SH_OPERAND_CRK, SH_OPERAND_TRA, SH_OPERAND_TRB
 194  , SH_OPERAND_DISP6, SH_OPERAND_DISP6X32, SH_OPERAND_DISP10, SH_OPERAND_DISP10X2
 195  , SH_OPERAND_DISP10X4, SH_OPERAND_DISP10X8, SH_OPERAND_DISP16, SH_OPERAND_IMM6
 196  , SH_OPERAND_IMM10, SH_OPERAND_IMM16, SH_OPERAND_UIMM6, SH_OPERAND_UIMM16
 197  , SH_OPERAND_LIKELY, SH_OPERAND_MAX
 198 } CGEN_OPERAND_TYPE;
 199
 200 /* Number of operands types.  */
 201 #define MAX_OPERANDS 72
 202
 203 /* Maximum number of operands referenced by any insn.  */
 204 #define MAX_OPERAND_INSTANCES 8
 205
 206 /* Insn attribute indices.  */
 207
 208 /* Enum declaration for cgen_insn attrs.  */
 209 typedef enum cgen_insn_attr {
 210   CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
 211  , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX
 212  , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_ILLSLOT, CGEN_INSN_FP_INSN
 213  , CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_ISA
 214  , CGEN_INSN_END_NBOOLS
 215 } CGEN_INSN_ATTR;
 216
 217 /* Number of non-boolean elements in cgen_insn_attr.  */
 218 #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
 219
 220 /* cgen.h uses things we just defined.  */
 221 #include "opcode/cgen.h"
 222
 223 /* Attributes.  */
 224 extern const CGEN_ATTR_TABLE sh_cgen_hardware_attr_table[];
 225 extern const CGEN_ATTR_TABLE sh_cgen_ifield_attr_table[];
 226 extern const CGEN_ATTR_TABLE sh_cgen_operand_attr_table[];
 227 extern const CGEN_ATTR_TABLE sh_cgen_insn_attr_table[];
 228
 229 /* Hardware decls.  */
 230
 231 extern CGEN_KEYWORD sh_cgen_opval_h_gr;
 232 extern CGEN_KEYWORD sh_cgen_opval_h_grc;
 233 extern CGEN_KEYWORD sh_cgen_opval_h_cr;
 234 extern CGEN_KEYWORD sh_cgen_opval_h_fr;
 235 extern CGEN_KEYWORD sh_cgen_opval_h_fp;
 236 extern CGEN_KEYWORD sh_cgen_opval_h_fv;
 237 extern CGEN_KEYWORD sh_cgen_opval_h_fmtx;
 238 extern CGEN_KEYWORD sh_cgen_opval_h_dr;
 239 extern CGEN_KEYWORD sh_cgen_opval_h_tr;
 240 extern CGEN_KEYWORD sh_cgen_opval_frc_names;
 241 extern CGEN_KEYWORD sh_cgen_opval_drc_names;
 242 extern CGEN_KEYWORD sh_cgen_opval_xf_names;
 243 extern CGEN_KEYWORD sh_cgen_opval_frc_names;
 244 extern CGEN_KEYWORD sh_cgen_opval_h_fvc;
 245
 246
 247
 248
 249 #endif /* SH_CPU_H */