1 /* Main simulator entry points specific to the SH5.
2 Copyright (C) 2000-2016 Free Software Foundation, Inc.
3 Contributed by Cygnus Solutions.
5 This file is part of the GNU simulators.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "libiberty.h"
27 #include "sim-options.h"
30 static void free_state (SIM_DESC
);
32 /* Since we don't build the cgen-opcode table, we use a wrapper around
33 the existing disassembler from libopcodes. */
34 static CGEN_DISASSEMBLER sh64_disassemble_insn
;
36 /* Cover function of sim_state_free to free the cpu buffers as well. */
39 free_state (SIM_DESC sd
)
41 if (STATE_MODULES (sd
) != NULL
)
42 sim_module_uninstall (sd
);
43 sim_cpu_free_all (sd
);
47 /* Create an instance of the simulator. */
50 sim_open (kind
, callback
, abfd
, argv
)
52 host_callback
*callback
;
58 SIM_DESC sd
= sim_state_alloc (kind
, callback
);
60 /* The cpu data is kept in a separately allocated chunk of memory. */
61 if (sim_cpu_alloc_all (sd
, 1, cgen_cpu_max_extra_bytes ()) != SIM_RC_OK
)
67 #if 0 /* FIXME: pc is in mach-specific struct */
68 /* FIXME: watchpoints code shouldn't need this */
70 SIM_CPU
*current_cpu
= STATE_CPU (sd
, 0);
71 STATE_WATCHPOINTS (sd
)->pc
= &(PC
);
72 STATE_WATCHPOINTS (sd
)->sizeof_pc
= sizeof (PC
);
76 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
82 #if 0 /* FIXME: 'twould be nice if we could do this */
83 /* These options override any module options.
84 Obviously ambiguity should be avoided, however the caller may wish to
85 augment the meaning of an option. */
86 if (extra_options
!= NULL
)
87 sim_add_option_table (sd
, extra_options
);
90 /* getopt will print the error message so we just have to exit if this fails.
91 FIXME: Hmmm... in the case of gdb we need getopt to call
93 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
99 /* Allocate core managed memory if none specified by user.
100 Use address 4 here in case the user wanted address 0 unmapped. */
101 if (sim_core_read_buffer (sd
, NULL
, read_map
, &c
, 4, 1) == 0)
102 sim_do_commandf (sd
, "memory region 0,0x%x", SH64_DEFAULT_MEM_SIZE
);
104 /* Add a small memory region way up in the address space to handle
105 writes to invalidate an instruction cache line. This is used for
106 trampolines. Since we don't simulate the cache, this memory just
107 avoids bus errors. 64K ought to do. */
108 sim_do_command (sd
," memory region 0xf0000000,0x10000");
110 /* check for/establish the reference program image */
111 if (sim_analyze_program (sd
,
112 (STATE_PROG_ARGV (sd
) != NULL
113 ? *STATE_PROG_ARGV (sd
)
121 /* Establish any remaining configuration options. */
122 if (sim_config (sd
) != SIM_RC_OK
)
128 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
134 /* Open a copy of the cpu descriptor table. */
136 CGEN_CPU_DESC cd
= sh_cgen_cpu_open_1 (STATE_ARCHITECTURE (sd
)->printable_name
,
139 for (i
= 0; i
< MAX_NR_PROCESSORS
; ++i
)
141 SIM_CPU
*cpu
= STATE_CPU (sd
, i
);
142 CPU_CPU_DESC (cpu
) = cd
;
143 CPU_DISASSEMBLER (cpu
) = sh64_disassemble_insn
;
147 /* Clear idesc table pointers for good measure. */
148 sh64_idesc_media
= sh64_idesc_compact
= NULL
;
150 /* Initialize various cgen things not done by common framework.
151 Must be done after sh_cgen_cpu_open. */
158 sim_create_inferior (sd
, abfd
, argv
, envp
)
164 SIM_CPU
*current_cpu
= STATE_CPU (sd
, 0);
168 addr
= bfd_get_start_address (abfd
);
171 sim_pc_set (current_cpu
, addr
);
173 /* Standalone mode (i.e. `run`) will take care of the argv for us in
174 sim_open() -> sim_parse_args(). But in debug mode (i.e. 'target sim'
175 with `gdb`), we need to handle it because the user can change the
176 argv on the fly via gdb's 'run'. */
177 if (STATE_PROG_ARGV (sd
) != argv
)
179 freeargv (STATE_PROG_ARGV (sd
));
180 STATE_PROG_ARGV (sd
) = dupargv (argv
);
186 /* Disassemble an instruction. */
189 sh64_disassemble_insn (SIM_CPU
*cpu
, const CGEN_INSN
*insn
,
190 const ARGBUF
*abuf
, IADDR pc
, char *buf
)
192 struct disassemble_info disasm_info
;
194 SIM_DESC sd
= CPU_STATE (cpu
);
196 sfile
.buffer
= sfile
.current
= buf
;
197 INIT_DISASSEMBLE_INFO (disasm_info
, (FILE *) &sfile
,
198 (fprintf_ftype
) sim_disasm_sprintf
);
200 disasm_info
.arch
= bfd_get_arch (STATE_PROG_BFD (sd
));
201 disasm_info
.mach
= bfd_get_mach (STATE_PROG_BFD (sd
));
203 (bfd_big_endian (STATE_PROG_BFD (sd
)) ? BFD_ENDIAN_BIG
204 : bfd_little_endian (STATE_PROG_BFD (sd
)) ? BFD_ENDIAN_LITTLE
205 : BFD_ENDIAN_UNKNOWN
);
206 disasm_info
.read_memory_func
= sim_disasm_read_memory
;
207 disasm_info
.memory_error_func
= sim_disasm_perror_memory
;
208 disasm_info
.application_data
= (PTR
) cpu
;
210 if (sh64_h_ism_get (cpu
) == ISM_MEDIA
)
211 print_insn_sh64x_media (pc
, &disasm_info
);
213 print_insn_sh (pc
, &disasm_info
);