sim/testsuite/d30v-elf/do-flags.S

   1         # Test macro
   2
   3         .macro assert reg,value
   4         cmpeq f0,\reg,\value
   5         bra/fx fail
   6         .endm
   7
   8
   9         # PR 15964 - a.s
  10
  11         add  r8,r0,0x7fff7fff         ;
  12         add  r9,r0,0x55555555         ;
  13         add  r12,r0,0x11111111         ;
  14         add  r1,r0,0x80000011   ; for psw
  15         mvtsys psw,r1 ||nop
  16         addhhhh r12,r8,r9 ||addhlll r13,r12,r12
  17         mvfsys r20,psw              ||nop
  18         mvtsys psw,r1 || add r2,r8, r9
  19         mvfsys r21,psw              ||nop
  20
  21         assert r20, 0x80000000
  22         assert r21, 0x80000014
  23
  24
  25         # PR 15964 - b.s
  26
  27         add  r40,r0,0x7fffffff
  28         add  r41,r0,0x7fffffff
  29         add  r1,r0,0x80000000       ; for psw
  30         mvtsys psw,r1,||nop
  31         cmpeq f1,r40,r41,||cmpeq f0,r40,r41,;
  32         mvfsys r42,psw
  33
  34         assert r42, 0x80005000
  35
  36
  37         # PR 16993 - a.s
  38
  39         add  r8,r0,0x80005555  ; for psw
  40         add  r9,r0,0x80000000  ; for psw
  41         add  r40,r0,0x11111111  ;
  42         add  r41,r0,0x22222222  ;
  43         add  r42,r0,0x00000000  ;
  44         mvtsys psw,r8 ||nop
  45         mvtsys psw,r9 ||add r42,r40,r41,;
  46
  47         mvfsys r10,psw
  48         assert r10, 0x80000000
  49
  50
  51         # PR 16995 - b.s
  52
  53         add  r8,r0,0x80000000  ; for psw
  54         add  r9,r0,0x80005555  ; for psw
  55         add  r10,r0,0x00000000  ;
  56         add  r40,r0,0x11111111  ;
  57         add  r41,r0,0x22222222  ;
  58         add  r42,r0,0x00000000  ;
  59         mvtsys psw,r8 ||nop
  60         mvtsys psw,r9 ||add r42,r40,r41,;
  61
  62         mvfsys r10,psw
  63         assert r10, 0x80005544
  64
  65
  66         # PR 17006 - c.s
  67
  68         add  r8,r0,0x80005555  ; for psw
  69         add  r9,r0,0x80000000  ; for psw
  70         add  r10,r0,0x00000000  ;
  71         add  r40,r0,0x00000011  ;
  72         add  r41,r0,0x00000011  ;
  73         mvtsys psw,r8 ||nop
  74         mvtsys psw,r9 ||cmpeq f5,r40,r41,;
  75
  76         mvfsys r10,psw
  77         assert r10, 0x80000010
  78
  79
  80         # PR 17006 - d.s
  81
  82         add  r9,r0,0x80000000  ; for psw
  83         add  r40,r0,0x00000011  ;
  84         add  r41,r0,0x00000011  ;
  85         nop  ||nop
  86         mvtsys psw, r9 || nop
  87         nop  ||nop
  88         nop ||cmpeq f5,r40,r41,;
  89
  90         mvfsys r10,psw
  91         assert r10, 0x80000010
  92
  93
  94         # PR 17106 - a.s
  95
  96         ; test 000     ;  mvtsys(s=0) || sathl(s=0) prallel execution test
  97         add  r8,r0,0x80005555  ; for psw
  98         add  r9,r0,0x80000000  ; for psw
  99         add  r40,r0,0x00000044  ;
 100         add  r41,r0,0x00000008  ;
 101         mvtsys psw,r8 ||nop
 102         mvtsys psw,r9 ||sathl r30,r40,r41,;
 103         mvfsys r20, psw ||nop
 104         ;-------------------------------
 105         ; test 001     ;  mvtsys(s=0) || sathl(s=1) prallel execution test
 106         _test_001:
 107         add  r40,r0,0x00004444  ;
 108         add  r41,r0,0x00000008  ;
 109         mvtsys psw,r8 ||nop
 110         mvtsys psw,r9 ||sathl r31,r40,r41,;
 111         mvfsys r21,psw ||nop
 112         ;-------------------------------
 113         ; test 002     ;  mvtsys(s=1) || sathl(s=0) prallel execution test
 114         add  r8,r0,0x80000000  ; for psw
 115         add  r9,r0,0x80005555  ; for psw
 116         add  r40,r0,0x00000044  ;
 117         add  r41,r0,0x00000008  ;
 118         mvtsys psw,r8 ||nop
 119         mvtsys psw,r9 ||sathl r32,r40,r41,;
 120         mvfsys r22,psw             ||nop
 121         ;-------------------------------
 122         ; test 003     ;  mvtsys(s=1) || sathl(s=1) prallel execution test
 123         ;   init-reg
 124         add  r40,r0,0x00004444  ;
 125         add  r41,r0,0x00000008  ;
 126         mvtsys psw,r8 ||nop
 127         mvtsys psw,r9 ||sathl r33,r40,r41,;
 128         mvfsys r23,psw             ||nop
 129
 130         assert r20, 0x80000000
 131         assert r21, 0x80000040
 132         assert r22, 0x80005555
 133         assert r23, 0x80005515
 134
 135
 136         # PR 18288 - a.s
 137
 138         ;------------------------------------------------------------------------
 139         ; mvtsys (C =1, V= VA = 0) ||  addc (C= V= VA =0)
 140         ;------------------------------------------------------------------------
 141         test_000b:
 142         add r1,r0,1   ||nop  ; set C bit
 143         mvtsys psw r0 ||nop
 144         mvtsys psw r1 ||addc r20,r0,1
 145         mvfsys r10,psw ||nop
 146         ; C changed in MU is not used in IU.
 147         ; IU prevail for resulting C.
 148         ;------------------------------------------------------------------------
 149         ; mvtsys (V =1, C = VA = 0) ||  add (C= V= VA =0)
 150         ;------------------------------------------------------------------------
 151         test_001b:
 152         add r1,r0,0x10 ||nop  ; set V bit
 153         mvtsys psw r0 ||nop
 154         mvtsys psw r1 ||add r0,r0,r0
 155         mvfsys r11,psw ||nop
 156         ; IU prevail for resulting V.
 157         ;------------------------------------------------------------------------
 158         ; mvtsys (V = C= VA = 0) ||  add (C=0,V= VA =1)
 159         ;------------------------------------------------------------------------
 160         test_002b:
 161         add r1,r0,0x70000000
 162         add r2,r0,0x30000000
 163         mvtsys psw r0 ||nop
 164         mvtsys psw r0 ||add r0,r1,r2
 165         mvfsys r12,psw ||nop
 166         ; IU prevail for resulting V.
 167         ; VA is set(OR'ed)
 168         ;------------------------------------------------------------------------
 169         ; mvtsys (C= 0 V = VA = 1) ||  add (C= V= VA =0)
 170         ;------------------------------------------------------------------------
 171         test_003b:
 172         add r1,r0,0x14 ||nop  ; set V and VA bit
 173         mvtsys psw r0 ||nop
 174         mvtsys psw r1 ||add r0,r0,r0
 175         mvfsys r13,psw ||nop
 176         ; IU prevail for resulging V
 177         ; VA is set(OR'ed)
 178         ;------------------------------------------------------------------------
 179         ; mvtsys (f3 =1) ||  orfg (f3) : GROUP_B
 180         ;------------------------------------------------------------------------
 181         test_004b:
 182         add r1,r0,0x100 ; set f3
 183         mvtsys psw r0 ||nop
 184         mvtsys psw,r1 ||orfg f3,f3,0
 185         mvfsys r14,psw ||nop
 186         ; results of IU prevail.
 187         ;------------------------------------------------------------------------
 188         ; mvtsys (f4 =1) ||  sathp
 189         ;------------------------------------------------------------------------
 190         test_005b:
 191         add r1,r0,0x40 ; set f4
 192         mvtsys psw r0 ||nop
 193         mvtsys psw r1 ||sathl r2,r1,3
 194         mvfsys r15,psw ||nop
 195         ; results of MU is used in IU
 196
 197         assert r20, 0x1
 198         assert r10, 0x0
 199         assert r11, 0x0
 200         assert r12, 0x14
 201         assert r13, 0x4
 202         assert r14, 0x0
 203         assert r15, 0x0
 204
 205
 206         # PR 18288 - b.s
 207         add r7,r0,0x80000000
 208         mvtsys psw,r7 || nop
 209
 210         add r8,r0,0x7fff7fff         ;
 211         add r9,r0,0x55555555         ;
 212         add r12,r0,0x11111111         ;
 213         add r13,r0,0x00000000         ;
 214         addhhhh r12,r8,r9 ||addhlll r13,r12,r12
 215         mvfsys r60,psw              ||nop
 216         ;------------------------------------------
 217         add r20,r0,0x66666666  ;
 218         add r21,r0,0x77777777  ;
 219         add r40,r0,0x22222222  ;
 220         add r41,r0,0x55555555  ;
 221         add r22,r20,r21 ||add r42,r40,r41,;
 222         mvfsys r61,psw              ||nop
 223
 224         assert r60, 0x80000000
 225         assert r61, 0x80000000
 226
 227
 228
 229         # all okay
 230
 231         bra     ok
 232
 233 ok:
 234         add r2, r0, 0
 235         .long 0x0e000004
 236         nop
 237
 238 fail:
 239         add r2, r0, 47
 240         .long 0x0e000004
 241         nop