sim/testsuite/sim/bfin/c_cc2stat_cc_av1.S

   1 //Original:/testcases/core/c_cc2stat_cc_av1/c_cc2stat_cc_av1.dsp
   2 // Spec Reference: cc2stat cc av1
   3 # mach: bfin
   4
   5 #include "test.h"
   6 .include "testutils.inc"
   7         start
   8
   9         imm32 r0, 0x00000000;
  10         imm32 r1, 0x00000000;
  11         imm32 r2, 0x00000000;
  12         imm32 r3, 0x00000000;
  13         imm32 r4, 0x00000000;
  14         imm32 r5, 0x00000000;
  15         imm32 r6, 0x00000000;
  16         imm32 r7, 0x00000000;
  17
  18 // test CC = AV1      0-0, 0-1, 1-0, 1-1
  19         R7 = 0x00;
  20         ASTAT = R7;     // cc = 0, AV1 = 0
  21         CC = AV1;       //
  22         R0 = CC;        //
  23
  24         imm32 R7, _AV1;
  25         ASTAT = R7;     // cc = 0, AV1 = 1
  26         CC = AV1;       //
  27         R1 = CC;        //
  28
  29         imm32 R7, _CC;
  30         ASTAT = R7;     // cc = 1, AV1 = 0
  31         CC = AV1;       //
  32         R2 = CC;        //
  33
  34         imm32 R7, (_CC|_AV1);
  35         ASTAT = R7;     // cc = 1, AV1 = 1
  36         CC = AV1;       //
  37         R3 = CC;        //
  38
  39 // test cc |= AV1 (0-0,  0-1,  1-0,  1-1)
  40         R7 = 0x00;
  41         ASTAT = R7;     // cc = 0, AV1 = 0
  42         CC |= AV1;      //
  43         R4 = CC;        //
  44
  45         imm32 R7, _AV1;
  46         ASTAT = R7;     // cc = 0, AV1 = 1
  47         CC |= AV1;      //
  48         R5 = CC;        //
  49
  50         imm32 R7, _CC;
  51         ASTAT = R7;     // cc = 1, AV1 = 0
  52         CC |= AV1;      //
  53         R6 = CC;        //
  54
  55         imm32 R7, (_CC|_AV1);
  56         ASTAT = R7;     // cc = 1, AV1 = 1
  57         CC |= AV1;      //
  58         R7 = CC;        //
  59
  60         CHECKREG r0, _UNSET;
  61         CHECKREG r1,   _SET;
  62         CHECKREG r2, _UNSET;
  63         CHECKREG r3,   _SET;
  64         CHECKREG r4, _UNSET;
  65         CHECKREG r5,   _SET;
  66         CHECKREG r6,   _SET;
  67         CHECKREG r7,   _SET;
  68
  69 // test CC &= AV1 (0-0,  0-1,  1-0,  1-1)
  70         R7 = 0x00;
  71         ASTAT = R7;     // cc = 0, AV1 = 0
  72         CC &= AV1;      //
  73         R4 = CC;        //
  74
  75         imm32 R7, _AV1;
  76         ASTAT = R7;     // cc = 0, AV1 = 1
  77         CC &= AV1;      //
  78         R5 = CC;        //
  79
  80         imm32 R7, _CC;
  81         ASTAT = R7;     // cc = 1, AV1 = 0
  82         CC &= AV1;      //
  83         R6 = CC;        //
  84
  85         imm32 R7, (_CC|_AV1);
  86         ASTAT = R7;     // cc = 1, AV1 = 1
  87         CC &= AV1;      //
  88         R7 = CC;        //
  89
  90         CHECKREG r0, _UNSET;
  91         CHECKREG r1, _SET;
  92         CHECKREG r2, _UNSET;
  93         CHECKREG r3, _SET;
  94         CHECKREG r4, _UNSET;
  95         CHECKREG r5, _UNSET;
  96         CHECKREG r6, _UNSET;
  97         CHECKREG r7, _SET;
  98
  99 // test CC ^= AV1 (0-0,  0-1,  1-0,  1-1)
 100         R7 = 0x00;
 101         ASTAT = R7;     // cc = 0, AV1 = 0
 102         CC ^= AV1;      //
 103         R4 = CC;        //
 104
 105         imm32 R7, _AV1;
 106         ASTAT = R7;     // cc = 0, AV1 = 1
 107         CC ^= AV1;      //
 108         R5 = CC;        //
 109
 110         imm32 R7, _CC;
 111         ASTAT = R7;     // cc = 1, AV1 = 0
 112         CC ^= AV1;      //
 113         R6 = CC;        //
 114
 115         imm32 R7, (_CC|_AV1);
 116         ASTAT = R7;     // cc = 1, AV1 = 1
 117         CC ^= AV1;      //
 118         R7 = CC;        //
 119
 120         CHECKREG r0, _UNSET;
 121         CHECKREG r1, _SET;
 122         CHECKREG r2, _UNSET;
 123         CHECKREG r3, _SET;
 124         CHECKREG r4, _UNSET;
 125         CHECKREG r5, _SET;
 126         CHECKREG r6, _SET;
 127         CHECKREG r7, _UNSET;
 128
 129 // test AV1 = CC      0-0, 0-1, 1-0, 1-1
 130         R7 = 0x00;
 131         ASTAT = R7;     // cc = 0, AV1 = 0
 132         AV1 = CC;       //
 133         R0 = ASTAT;     //
 134
 135         imm32 R7, _AV1;
 136         ASTAT = R7;     // cc = 0, AV1 = 1
 137         AV1 = CC;       //
 138         R1 = ASTAT;     //
 139
 140         imm32 R7, _CC;
 141         ASTAT = R7;     // cc = 1, AV1 = 0
 142         AV1 = CC;       //
 143         R2 = ASTAT;     //
 144
 145         imm32 R7, (_CC|_AV1);
 146         ASTAT = R7;     // cc = 1, AV1 = 1
 147         AV1 = CC;       //
 148         R3 = ASTAT;     //
 149
 150 // test AV1 |= CC (0-0,  0-1,  1-0,  1-1)
 151         R7 = 0x00;
 152         ASTAT = R7;     // cc = 0, AV1 = 0
 153         AV1 |= CC;      //
 154         R4 = ASTAT;     //
 155
 156         imm32 R7, _AV1;
 157         ASTAT = R7;     // cc = 0, AV1 = 1
 158         AV1 |= CC;      //
 159         R5 = ASTAT;     //
 160
 161         imm32 R7, _CC;
 162         ASTAT = R7;     // cc = 1, AV1 = 0
 163         AV1 |= CC;      //
 164         R6 = ASTAT;     //
 165
 166         imm32 R7, (_CC|_AV1);
 167         ASTAT = R7;     // cc = 1, AV1 = 1
 168         AV1 |= CC;      //
 169         R7 = ASTAT;     //
 170
 171         CHECKREG r0, _UNSET;
 172         CHECKREG r1, _UNSET;
 173         CHECKREG r2, (_CC|_AV1);
 174         CHECKREG r3, (_CC|_AV1);
 175         CHECKREG r4, _UNSET;
 176         CHECKREG r5, _AV1;
 177         CHECKREG r6, (_CC|_AV1);
 178         CHECKREG r7, (_CC|_AV1);
 179
 180 // test AV1 &= CC (0-0,  0-1,  1-0,  1-1)
 181         R7 = 0x00;
 182         ASTAT = R7;     // cc = 0, AV1 = 0
 183         AV1 &= CC;      //
 184         R4 = ASTAT;     //
 185
 186         imm32 R7, _AV1;
 187         ASTAT = R7;     // cc = 0, AV1 = 1
 188         AV1 &= CC;      //
 189         R5 = ASTAT;     //
 190
 191         imm32 R7, _CC;
 192         ASTAT = R7;     // cc = 1, AV1 = 0
 193         AV1 &= CC;      //
 194         R6 = ASTAT;     //
 195
 196         imm32 R7, (_CC|_AV1);
 197         ASTAT = R7;     // cc = 1, AV1 = 1
 198         AV1 &= CC;      //
 199         R7 = ASTAT;     //
 200
 201         CHECKREG r0, _UNSET;
 202         CHECKREG r1, _UNSET;
 203         CHECKREG r2, (_CC|_AV1);
 204         CHECKREG r3, (_CC|_AV1);
 205         CHECKREG r4, _UNSET;
 206         CHECKREG r5, _UNSET;
 207         CHECKREG r6, _CC;
 208         CHECKREG r7, (_CC|_AV1);
 209
 210 // test AV1 ^= CC (0-0,  0-1,  1-0,  1-1)
 211         R7 = 0x00;
 212         ASTAT = R7;     // cc = 0, AV1 = 0
 213         AV1 ^= CC;      //
 214         R4 = ASTAT;     //
 215
 216         imm32 R7, _AV1;
 217         ASTAT = R7;     // cc = 0, AV1 = 1
 218         AV1 ^= CC;      //
 219         R5 = ASTAT;     //
 220
 221         imm32 R7, _CC;
 222         ASTAT = R7;     // cc = 1, AV1 = 0
 223         AV1 ^= CC;      //
 224         R6 = ASTAT;     //
 225
 226         imm32 R7, (_CC|_AV1);
 227         ASTAT = R7;     // cc = 1, AV1 = 1
 228         AV1 ^= CC;      //
 229         R7 = ASTAT;     //
 230
 231         CHECKREG r0, _UNSET;
 232         CHECKREG r1, _UNSET;
 233         CHECKREG r2, (_CC|_AV1);
 234         CHECKREG r3, (_CC|_AV1);
 235         CHECKREG r4, _UNSET;
 236         CHECKREG r5, _AV1;
 237         CHECKREG r6, (_CC|_AV1);
 238         CHECKREG r7, _CC;
 239
 240         pass