sim/testsuite/sim/bfin/c_cc_flagdreg_mvbrsft.s

   1 //Original:/testcases/core/c_cc_flagdreg_mvbrsft/c_cc_flagdreg_mvbrsft.dsp
   2 // Spec Reference: cc: set (ccflag & cc2dreg) used (ccmv & brcc & dsp32sft)
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8
   9
  10
  11 imm32 r0, 0xa08d2311;
  12 imm32 r1, 0x10120040;
  13 imm32 r2, 0x62b61557;
  14 imm32 r3, 0x07300007;
  15 imm32 r4, 0x00740088;
  16 imm32 r5, 0x609950aa;
  17 imm32 r6, 0x20bb06cc;
  18 imm32 r7, 0xd90e108f;
  19
  20         ASTAT = R0;
  21
  22         CC = R1;                        // cc2dreg
  23         IF CC R1 = R3;                  // ccmov
  24         CC = ! CC;                      // cc2dreg
  25         IF CC R3 = R2;                  // ccmov
  26         CC = R0 < R1;                   // ccflag
  27         IF CC R4 = R5;                  // ccmov
  28         CC = R2 == R3;
  29         IF CC R4 = R5;                  // ccmov
  30         CC = R0;                        // cc2dreg
  31         IF !CC JUMP LABEL1;             // branch on
  32         CC = ! CC;
  33         IF !CC JUMP LABEL2 (BP);        // branch on
  34 LABEL1:
  35         R6 = R0 + R2;
  36         JUMP.S END;
  37 LABEL2:
  38         R7 = R5 - R3;
  39         CC = R0 < R1;                   // ccflag
  40         IF CC JUMP END (BP);            // branch on
  41         R4 = R5 + R7;
  42
  43 END:
  44
  45 CHECKREG r0, 0xA08D2311;
  46 CHECKREG r1, 0x07300007;
  47 CHECKREG r2, 0x62B61557;
  48 CHECKREG r3, 0x07300007;
  49 CHECKREG r4, 0x609950AA;
  50 CHECKREG r5, 0x609950AA;
  51 CHECKREG r6, 0x20BB06CC;
  52 CHECKREG r7, 0x596950A3;
  53
  54 imm32 r0, 0x408d2711;
  55 imm32 r1, 0x15124040;
  56 imm32 r2, 0x62661557;
  57 imm32 r3, 0x073b0007;
  58 imm32 r4, 0x01f49088;
  59 imm32 r5, 0x6e2959aa;
  60 imm32 r6, 0xa0b506cc;
  61 imm32 r7, 0x00000002;
  62
  63
  64         CC = R1;                // cc2dreg
  65         R2 = ROT R2 BY 1;       // dsp32shiftim_rot
  66         CC = ! CC;              // cc2dreg
  67         R3 = ROT R0 BY -3;      // dsp32shiftim_rot
  68         CC = R0 < R1;           // ccflag
  69         R6 = ROT R4 BY 5;       // dsp32shiftim_rot
  70         CC = R2 == R3;
  71         IF CC R4 = R5;          // ccmov
  72         CC = R0;                // cc2dreg
  73         R7 = ROT R6 BY R7.L;
  74
  75 CHECKREG r0, 0x408D2711;
  76 CHECKREG r1, 0x15124040;
  77 CHECKREG r2, 0xC4CC2AAF;
  78 CHECKREG r3, 0x6811A4E2;
  79 CHECKREG r4, 0x01F49088;
  80 CHECKREG r5, 0x6E2959AA;
  81 CHECKREG r6, 0x3E921100;
  82 CHECKREG r7, 0xFA484402;
  83
  84
  85
  86
  87 pass