sim/testsuite/sim/bfin/c_ccmv_ncc_dr_pr.s

   1 //Original:/proj/frio/dv/testcases/core/c_ccmv_ncc_dr_pr/c_ccmv_ncc_dr_pr.dsp
   2 // Spec Reference: ccmv !cc dpreg = dpreg
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8         R0 = 0;
   9         ASTAT = R0;
  10
  11         imm32 r0, 0x138d2301;
  12         imm32 r1, 0x20421053;
  13         imm32 r2, 0x3f051405;
  14         imm32 r3, 0x40b66507;
  15         imm32 r4, 0x50487709;
  16         imm32 r5, 0x6005908b;
  17         imm32 r6, 0x7a0c6609;
  18         imm32 r7, 0x890e108f;
  19         imm32 p1, 0x9d021053;
  20         imm32 p2, 0xafb41405;
  21         imm32 p3, 0xb0bf1507;
  22         imm32 p4, 0xd0483609;
  23         imm32 p5, 0xe005d00b;
  24         imm32 sp, 0xfa0c667d;
  25         imm32 fp, 0xc90e108f;
  26         IF !CC R0 = P0;
  27         CC = ! CC;
  28         IF !CC P1 = R3;
  29         IF !CC R2 = P5;
  30         IF !CC P2 = R2;
  31         IF !CC P3 = R6;
  32         IF !CC R5 = P1;
  33         CC = ! CC;
  34         IF !CC P4 = R7;
  35         IF !CC R7 = P4;
  36         IF !CC P5 = R3;
  37         IF !CC R6 = SP;
  38         CC = ! CC;
  39         IF !CC R3 = P2;
  40         IF !CC SP = R6;
  41         IF !CC R1 = P5;
  42         CC = ! CC;
  43         IF !CC FP = R4;
  44         IF !CC R3 = P3;
  45         CHECKREG r1, 0x20421053;
  46         CHECKREG r2, 0x3F051405;
  47         CHECKREG r3, 0xB0BF1507;
  48         CHECKREG r4, 0x50487709;
  49         CHECKREG r5, 0x6005908B;
  50         CHECKREG r6, 0xFA0C667D;
  51         CHECKREG r7, 0x890E108F;
  52         CHECKREG p1, 0x9D021053;
  53         CHECKREG p2, 0xAFB41405;
  54         CHECKREG p3, 0xB0BF1507;
  55         CHECKREG p4, 0x890E108F;
  56         CHECKREG p5, 0x40B66507;
  57         CHECKREG sp, 0xFA0C667D;
  58         CHECKREG fp, 0x50487709;
  59
  60         pass