sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_s.s

   1 //Original:/testcases/core/c_dsp32mac_dr_a1_s/c_dsp32mac_dr_a1_s.dsp
   2 // Spec Reference: dsp32mac dr_a1 s (scale by 2 signed fraction with round)
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8
   9
  10
  11 A1 = A0 = 0;
  12
  13 // The result accumulated in A1 , and stored to a reg half
  14 imm32 r0, 0xa3545abd;
  15 imm32 r1, 0xbabcfec7;
  16 imm32 r2, 0xc1a48679;
  17 imm32 r3, 0xd00a9007;
  18 imm32 r4, 0xefbca569;
  19 imm32 r5, 0xcd355a0b;
  20 imm32 r6, 0xe00c80ad;
  21 imm32 r7, 0xf78e900a;
  22 R0.H = ( A1 -= R1.L * R0.L ), A0 += R1.L * R0.L (S2RND);
  23 R1 = A1.w;
  24 R2.H = ( A1 += R2.L * R3.H ), A0 -= R2.H * R3.L (S2RND);
  25 R3 = A1.w;
  26 R4.H = ( A1 = R4.H * R5.L ), A0 = R4.H * R5.H (S2RND);
  27 R5 = A1.w;
  28 R6.H = ( A1 += R6.H * R7.H ), A0 -= R6.L * R7.H (S2RND);
  29 R7 = A1.w;
  30 CHECKREG r0, 0x01BC5ABD;
  31 CHECKREG r1, 0x00DDE22A;
  32 CHECKREG r2, 0x5CCE8679;
  33 CHECKREG r3, 0x2E67039E;
  34 CHECKREG r4, 0xE91EA569;
  35 CHECKREG r5, 0xF48ECA28;
  36 CHECKREG r6, 0xED5580AD;
  37 CHECKREG r7, 0xF6AA7F78;
  38
  39 // The result accumulated in A1, and stored to a reg half (MNOP)
  40 imm32 r0, 0x63bb8abd;
  41 imm32 r1, 0xbdbcfec7;
  42 imm32 r2, 0xab245679;
  43 imm32 r3, 0xb0b69007;
  44 imm32 r4, 0xcfbb4569;
  45 imm32 r5, 0xd235b00b;
  46 imm32 r6, 0xe00cab0d;
  47 imm32 r7, 0x678e70bf;
  48 R0.H = ( A1 += R1.L * R0.L ) (S2RND);
  49 R1 = A1.w;
  50 R2.H = ( A1 -= R2.L * R3.H ) (S2RND);
  51 R3 = A1.w;
  52 R4.H = ( A1 += R4.H * R5.L ) (S2RND);
  53 R5 = A1.w;
  54 R6.H = ( A1 = R6.H * R7.H ) (S2RND);
  55 R7 = A1.w;
  56 CHECKREG r0, 0xEF928ABD;
  57 CHECKREG r1, 0xF7C93D4E;
  58 CHECKREG r2, 0x5AB45679;
  59 CHECKREG r3, 0x2D59E942;
  60 CHECKREG r4, 0x7FFF4569;
  61 CHECKREG r5, 0x4B80E354;
  62 CHECKREG r6, 0xCC4CAB0D;
  63 CHECKREG r7, 0xE6263550;
  64
  65 // The result accumulated in A1 , and stored to a reg half (MNOP)
  66 imm32 r0, 0x5c54babd;
  67 imm32 r1, 0x6dccdec7;
  68 imm32 r2, 0xc12ce679;
  69 imm32 r3, 0x8c06c007;
  70 imm32 r4, 0x9fcc4c69;
  71 imm32 r5, 0xa23c90cb;
  72 imm32 r6, 0xb00cc00c;
  73 imm32 r7, 0xc78eac0f;
  74  R0.H = A1 , A0 -= R1.L * R0.L (S2RND);
  75 R1 = A1.w;
  76  R2.H = A1 , A0 += R2.H * R3.L (S2RND);
  77 R3 = A1.w;
  78  R4.H = A1 , A0 = R4.H * R5.H (S2RND);
  79 R5 = A1.w;
  80  R6.H = A1 , A0 += R6.L * R7.H (S2RND);
  81 R7 = A1.w;
  82 CHECKREG r0, 0xCC4CBABD;
  83 CHECKREG r1, 0xE6263550;
  84 CHECKREG r2, 0xCC4CE679;
  85 CHECKREG r3, 0xE6263550;
  86 CHECKREG r4, 0xCC4C4C69;
  87 CHECKREG r5, 0xE6263550;
  88 CHECKREG r6, 0xCC4CC00C;
  89 CHECKREG r7, 0xE6263550;
  90
  91 // The result accumulated in A1 , and stored to a reg half
  92 imm32 r0, 0x3d545abd;
  93 imm32 r1, 0x5ddcfec7;
  94 imm32 r2, 0x712d5679;
  95 imm32 r3, 0x9006d007;
  96 imm32 r4, 0xafbc4d69;
  97 imm32 r5, 0xd23590db;
  98 imm32 r6, 0xd00ca00d;
  99 imm32 r7, 0x6d8ed00f;
 100 R0.H = ( A1 = R1.L * R0.L ) (M), A0 += R1.L * R0.L (S2RND);
 101 R1 = A1.w;
 102 R2.H = ( A1 = R2.L * R3.H ) (M), A0 -= R2.H * R3.L (S2RND);
 103 R3 = A1.w;
 104 R4.H = ( A1 += R4.H * R5.L ) (M), A0 = R4.H * R5.H (S2RND);
 105 R5 = A1.w;
 106 R6.H = ( A1 += R6.H * R7.H ) (M), A0 += R6.L * R7.H (S2RND);
 107 R7 = A1.w;
 108 CHECKREG r0, 0xFF225ABD;
 109 CHECKREG r1, 0xFF910EEB;
 110 CHECKREG r2, 0x614C5679;
 111 CHECKREG r3, 0x30A616D6;
 112 CHECKREG r4, 0x06764D69;
 113 CHECKREG r5, 0x033B2CAA;
 114 CHECKREG r6, 0xDD6BA00D;
 115 CHECKREG r7, 0xEEB5AF52;
 116
 117 // The result accumulated in A1 MM=0, and stored to a reg half (MNOP)
 118 imm32 r0, 0x83e45abd;
 119 imm32 r1, 0xe8befec7;
 120 imm32 r2, 0xce84e679;
 121 imm32 r3, 0x1ce80e07;
 122 imm32 r4, 0xe1ce85e9;
 123 imm32 r5, 0x921ce80e;
 124 imm32 r6, 0x79019e8d;
 125 imm32 r7, 0x679e90e8;
 126 R0.H = ( A1 += R1.L * R0.L ) (M,S2RND);
 127 R1 = A1.w;
 128 R2.H = ( A1 = R2.L * R3.H ) (M,S2RND);
 129 R3 = A1.w;
 130 R4.H = ( A1 += R4.H * R5.L ) (M,S2RND);
 131 R5 = A1.w;
 132 R6.H = ( A1 -= R6.H * R7.H ) (M,S2RND);
 133 R7 = A1.w;
 134 CHECKREG r0, 0xDC8D5ABD;
 135 CHECKREG r1, 0xEE46BE3D;
 136 CHECKREG r2, 0xFA3CE679;
 137 CHECKREG r3, 0xFD1E19A8;
 138 CHECKREG r4, 0xC37E85E9;
 139 CHECKREG r5, 0xE1BF22EC;
 140 CHECKREG r6, 0x80009E8D;
 141 CHECKREG r7, 0xB0C50D4E;
 142
 143
 144
 145 pass