sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_tu.s

   1 //Original:/testcases/core/c_dsp32mac_dr_a1_tu/c_dsp32mac_dr_a1_tu.dsp
   2 // Spec Reference: dsp32mac dr_a1 tu (truncate signed fraction)
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8
   9
  10
  11 A1 = A0 = 0;
  12
  13 // The result accumulated in A1 , and stored to a reg half
  14 imm32 r0, 0xa3545abd;
  15 imm32 r1, 0xbdbcfec7;
  16 imm32 r2, 0xc1248679;
  17 imm32 r3, 0xd0069007;
  18 imm32 r4, 0xefbc4569;
  19 imm32 r5, 0xcd35500b;
  20 imm32 r6, 0xe00c800d;
  21 imm32 r7, 0xf78e900f;
  22 R0.H = ( A1 = R1.L * R0.L ), A0 = R1.L * R0.L (TFU);
  23 R1 = A1.w;
  24 R2.H = ( A1 -= R2.L * R3.H ), A0 = R2.H * R3.L (TFU);
  25 R3 = A1.w;
  26 R4.H = ( A1 += R4.H * R5.L ), A0 -= R4.H * R5.H (TFU);
  27 R5 = A1.w;
  28 R6.H = ( A1 += R6.H * R7.H ), A0 += R6.L * R7.H (TFU);
  29 R7 = A1.w;
  30 CHECKREG r0, 0x5A4E5ABD;
  31 CHECKREG r1, 0x5A4E0EEB;
  32 CHECKREG r2, 0x00008679;
  33 CHECKREG r3, 0x00000000;
  34 CHECKREG r4, 0x4AF54569;
  35 CHECKREG r5, 0x4AF50D14;
  36 CHECKREG r6, 0xFFFF800D;
  37 CHECKREG r7, 0x239CE7BC;
  38
  39 // The result accumulated in A1, and stored to a reg half (MNOP)
  40 imm32 r0, 0x63548abd;
  41 imm32 r1, 0x7dbcfec7;
  42 imm32 r2, 0xC5885679;
  43 imm32 r3, 0xC5880000;
  44 imm32 r4, 0xcfbc4569;
  45 imm32 r5, 0xd235c00b;
  46 imm32 r6, 0xe00ca00d;
  47 imm32 r7, 0x678e700f;
  48 R0.H = ( A1 = R1.L * R0.L ) (TFU);
  49 R1 = A1.w;
  50 R2.H = ( A1 += R2.L * R3.H ) (TFU);
  51 R3 = A1.w;
  52 R4.H = ( A1 -= R4.H * R5.L ) (TFU);
  53 R5 = A1.w;
  54 R6.H = ( A1 = R6.H * R7.H ) (TFU);
  55 R7 = A1.w;
  56 CHECKREG r0, 0x8A138ABD;
  57 CHECKREG r1, 0x8A135EEB;
  58 CHECKREG r2, 0xCCCC5679;
  59 CHECKREG r3, 0xCCCC6C33;
  60 CHECKREG r4, 0x30F64569;
  61 CHECKREG r5, 0x30F67F1F;
  62 CHECKREG r6, 0x5AA1A00D;
  63 CHECKREG r7, 0x5AA11AA8;
  64
  65 // The result accumulated in A1 , and stored to a reg half (MNOP)
  66 imm32 r0, 0x5354babd;
  67 imm32 r1, 0x6dbcdec7;
  68 imm32 r2, 0x7124e679;
  69 imm32 r3, 0x80067007;
  70 imm32 r4, 0x9fbc4569;
  71 imm32 r5, 0xa235900b;
  72 imm32 r6, 0xb00c300d;
  73 imm32 r7, 0xc78ea00f;
  74  R0.H = A1 , A0 -= R1.L * R0.L (TFU);
  75 R1 = A1.w;
  76  R2.H = A1 , A0 += R2.H * R3.L (TFU);
  77 R3 = A1.w;
  78  R4.H = A1 , A0 -= R4.H * R5.H (TFU);
  79 R5 = A1.w;
  80  R6.H = A1 , A0 = R6.L * R7.H (TFU);
  81 R7 = A1.w;
  82 CHECKREG r0, 0x5AA1BABD;
  83 CHECKREG r1, 0x5AA11AA8;
  84 CHECKREG r2, 0x5AA1E679;
  85 CHECKREG r3, 0x5AA11AA8;
  86 CHECKREG r4, 0x5AA14569;
  87 CHECKREG r5, 0x5AA11AA8;
  88 CHECKREG r6, 0x5AA1300D;
  89 CHECKREG r7, 0x5AA11AA8;
  90
  91 // The result accumulated in A1 , and stored to a reg half
  92 imm32 r0, 0x33545abd;
  93 imm32 r1, 0x5dbcfec7;
  94 imm32 r2, 0x71245679;
  95 imm32 r3, 0x90060007;
  96 imm32 r4, 0xafbc4569;
  97 imm32 r5, 0xd235900b;
  98 imm32 r6, 0xc00ca00d;
  99 imm32 r7, 0x678ed00f;
 100 R0.H = ( A1 = R1.L * R0.L ) (M), A0 -= R1.L * R0.L (TFU);
 101 R1 = A1.w;
 102 R2.H = ( A1 += R2.L * R3.H ) (M), A0 -= R2.H * R3.L (TFU);
 103 R3 = A1.w;
 104 R4.H = ( A1 -= R4.H * R5.L ) (M), A0 += R4.H * R5.H (TFU);
 105 R5 = A1.w;
 106 R6.H = ( A1 += R6.H * R7.H ) (M), A0 += R6.L * R7.H (TFU);
 107 R7 = A1.w;
 108 CHECKREG r0, 0xFF915ABD;
 109 CHECKREG r1, 0xFF910EEB;
 110 CHECKREG r2, 0x30375679;
 111 CHECKREG r3, 0x303725C1;
 112 CHECKREG r4, 0x5D604569;
 113 CHECKREG r5, 0x5D60D8AD;
 114 CHECKREG r6, 0x4382A00D;
 115 CHECKREG r7, 0x43823355;
 116
 117 // The result accumulated in A1 MM=0, and stored to a reg half (MNOP)
 118 imm32 r0, 0x92005ABD;
 119 imm32 r1, 0x09300000;
 120 imm32 r2, 0x56749679;
 121 imm32 r3, 0x30A95000;
 122 imm32 r4, 0xa0009669;
 123 imm32 r5, 0x01000970;
 124 imm32 r6, 0xdf45609D;
 125 imm32 r7, 0x12345679;
 126 R0.H = ( A1 += R1.L * R0.L ) (M,TFU);
 127 R1 = A1.w;
 128 R2.H = ( A1 -= R2.L * R3.H ) (M,TFU);
 129 R3 = A1.w;
 130 R4.H = ( A1 = R4.H * R5.L ) (M,TFU);
 131 R5 = A1.w;
 132 R6.H = ( A1 -= R6.H * R7.H ) (M,TFU);
 133 R7 = A1.w;
 134 CHECKREG r0, 0x43825ABD;
 135 CHECKREG r1, 0x43823355;
 136 CHECKREG r2, 0x57919679;
 137 CHECKREG r3, 0x57912D74;
 138 CHECKREG r4, 0xFC769669;
 139 CHECKREG r5, 0xFC760000;
 140 CHECKREG r6, 0xFEC9609D;
 141 CHECKREG r7, 0xFEC9CBFC;
 142
 143
 144
 145 pass