sim/testsuite/sim/bfin/c_dsp32shift_fdepx.s

   1 //Original:/testcases/core/c_dsp32shift_fdepx/c_dsp32shift_fdepx.dsp
   2 // Spec Reference: dsp32shift fdep x
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8 imm32 r0, 0x00000001;
   9 imm32 r1, 0x01000801;
  10 imm32 r2, 0x08200802;
  11 imm32 r3, 0x08030803;
  12 imm32 r4, 0x08004804;
  13 imm32 r5, 0x08000505;
  14 imm32 r6, 0x08000866;
  15 imm32 r7, 0x08000807;
  16 R1 = DEPOSIT( R1, R0 );
  17 R2 = DEPOSIT( R2, R0 );
  18 R3 = DEPOSIT( R3, R0 );
  19 R4 = DEPOSIT( R4, R0 ) (X);
  20 R5 = DEPOSIT( R5, R0 );
  21 R6 = DEPOSIT( R6, R0 );
  22 R7 = DEPOSIT( R7, R0 ) (X);
  23 R0 = DEPOSIT( R0, R0 );
  24 CHECKREG r0, 0x00000000;
  25 CHECKREG r1, 0x01000800;
  26 CHECKREG r2, 0x08200802;
  27 CHECKREG r3, 0x08030802;
  28 CHECKREG r4, 0x00000000;
  29 CHECKREG r5, 0x08000504;
  30 CHECKREG r6, 0x08000866;
  31 CHECKREG r7, 0x00000000;
  32
  33 imm32 r0, 0x0900d001;
  34 imm32 r1, 0x09000002;
  35 imm32 r2, 0x09000002;
  36 imm32 r3, 0x09100003;
  37 imm32 r4, 0x09020004;
  38 imm32 r5, 0x09003005;
  39 imm32 r6, 0x09000406;
  40 imm32 r7, 0x09000057;
  41 R0 = DEPOSIT( R0, R1 );
  42 R2 = DEPOSIT( R2, R1 );
  43 R3 = DEPOSIT( R3, R1 );
  44 R4 = DEPOSIT( R4, R1 );
  45 R5 = DEPOSIT( R5, R1 ) (X);
  46 R6 = DEPOSIT( R6, R1 );
  47 R7 = DEPOSIT( R7, R1 ) (X);
  48 R1 = DEPOSIT( R1, R1 );
  49 CHECKREG r0, 0x0900D000;
  50 CHECKREG r1, 0x09000000;
  51 CHECKREG r2, 0x09000000;
  52 CHECKREG r3, 0x09100000;
  53 CHECKREG r4, 0x09020004;
  54 CHECKREG r5, 0x00000000;
  55 CHECKREG r6, 0x09000404;
  56 CHECKREG r7, 0x00000000;
  57
  58
  59 imm32 r0, 0x0a00e001;
  60 imm32 r1, 0x0a00e001;
  61 imm32 r2, 0x0a00000f;
  62 imm32 r3, 0x0a000010;
  63 imm32 r4, 0x0a00e004;
  64 imm32 r5, 0x0a00e005;
  65 imm32 r6, 0x0a00e006;
  66 imm32 r7, 0x0a00e007;
  67 R0 = DEPOSIT( R0, R2 );
  68 R1 = DEPOSIT( R1, R2 );
  69 R3 = DEPOSIT( R3, R2 );
  70 R4 = DEPOSIT( R4, R2 );
  71 R5 = DEPOSIT( R5, R2 );
  72 R6 = DEPOSIT( R6, R2 );
  73 R7 = DEPOSIT( R7, R2 );
  74 R2 = DEPOSIT( R2, R2 );
  75 CHECKREG r0, 0x0A008A00;
  76 CHECKREG r1, 0x0A008A00;
  77 CHECKREG r2, 0x0A000A00;
  78 CHECKREG r3, 0x0A000A00;
  79 CHECKREG r4, 0x0A008A00;
  80 CHECKREG r5, 0x0A008A00;
  81 CHECKREG r6, 0x0A008A00;
  82 CHECKREG r7, 0x0A008A00;
  83
  84 imm32 r0, 0x4b00f001;
  85 imm32 r1, 0x5b00f001;
  86 imm32 r2, 0x6b00f002;
  87 imm32 r3, 0x9f000010;
  88 imm32 r4, 0x8b00f004;
  89 imm32 r5, 0x0900f005;
  90 imm32 r6, 0x0b00f006;
  91 imm32 r7, 0x0b0af007;
  92 R0 = DEPOSIT( R0, R3 );
  93 R1 = DEPOSIT( R1, R3 );
  94 R2 = DEPOSIT( R2, R3 ) (X);
  95 R4 = DEPOSIT( R4, R3 );
  96 R5 = DEPOSIT( R5, R3 );
  97 R6 = DEPOSIT( R6, R3 ) (X);
  98 R7 = DEPOSIT( R7, R3 );
  99 R3 = DEPOSIT( R3, R3 );
 100 CHECKREG r0, 0x4B009F00;
 101 CHECKREG r1, 0x5B009F00;
 102 CHECKREG r2, 0xFFFF9F00;
 103 CHECKREG r3, 0x9F009F00;
 104 CHECKREG r4, 0x8B009F00;
 105 CHECKREG r5, 0x09009F00;
 106 CHECKREG r6, 0xFFFF9F00;
 107 CHECKREG r7, 0x0B0A9F00;
 108
 109 imm32 r0, 0x0c0000c0;
 110 imm32 r1, 0x0c0100c0;
 111 imm32 r2, 0x0c0200c0;
 112 imm32 r3, 0x0c0300c0;
 113 imm32 r4, 0x0c04000c;
 114 imm32 r5, 0x0c0500c0;
 115 imm32 r6, 0x0c0600c0;
 116 imm32 r7, 0x0c0700c0;
 117 R0 = DEPOSIT( R0, R4 );
 118 R1 = DEPOSIT( R1, R4 );
 119 R2 = DEPOSIT( R2, R4 );
 120 R3 = DEPOSIT( R3, R4 );
 121 R5 = DEPOSIT( R5, R4 ) (X);
 122 R6 = DEPOSIT( R6, R4 );
 123 R7 = DEPOSIT( R7, R4 );
 124 R4 = DEPOSIT( R4, R4 );
 125 CHECKREG r0, 0x0C000C04;
 126 CHECKREG r1, 0x0C010C04;
 127 CHECKREG r2, 0x0C020C04;
 128 CHECKREG r3, 0x0C030C04;
 129 CHECKREG r4, 0x0C040C04;
 130 CHECKREG r5, 0xFFFFFC04;
 131 CHECKREG r6, 0x0C060C04;
 132 CHECKREG r7, 0x0C070C04;
 133
 134 imm32 r0, 0xa00100d0;
 135 imm32 r1, 0xa00100d1;
 136 imm32 r2, 0xa00200d0;
 137 imm32 r3, 0xa00300d0;
 138 imm32 r4, 0xa00400d0;
 139 imm32 r5, 0xa0050007;
 140 imm32 r6, 0xa00600d0;
 141 imm32 r7, 0xa00700d0;
 142 R5 = DEPOSIT( R0, R5 );
 143 R6 = DEPOSIT( R1, R5 ) (X);
 144 R7 = DEPOSIT( R2, R5 );
 145 R0 = DEPOSIT( R3, R5 );
 146 R1 = DEPOSIT( R4, R5 ) (X);
 147 R2 = DEPOSIT( R6, R5 );
 148 R3 = DEPOSIT( R7, R5 );
 149 R4 = DEPOSIT( R5, R5 );
 150 CHECKREG r0, 0xA00300C1;
 151 CHECKREG r1, 0x00000001;
 152 CHECKREG r2, 0x00000001;
 153 CHECKREG r3, 0xA00200C1;
 154 CHECKREG r4, 0xA0010081;
 155 CHECKREG r5, 0xA0010085;
 156 CHECKREG r6, 0x00000001;
 157 CHECKREG r7, 0xA00200C1;
 158
 159 imm32 r0, 0xb0010000;
 160 imm32 r1, 0xb0010000;
 161 imm32 r2, 0xb002000f;
 162 imm32 r3, 0xb0030000;
 163 imm32 r4, 0xb0040000;
 164 imm32 r5, 0xb0050000;
 165 imm32 r6, 0x00237809;
 166 imm32 r7, 0xb0070000;
 167 R0 = DEPOSIT( R0, R6 );
 168 R1 = DEPOSIT( R1, R6 );
 169 R2 = DEPOSIT( R2, R6 );
 170 R3 = DEPOSIT( R3, R6 ) (X);
 171 R4 = DEPOSIT( R4, R6 );
 172 R5 = DEPOSIT( R5, R6 );
 173 R6 = DEPOSIT( R6, R6 );
 174 R7 = DEPOSIT( R7, R6 );
 175 CHECKREG r0, 0x23010000;
 176 CHECKREG r1, 0x23010000;
 177 CHECKREG r2, 0x2302000F;
 178 CHECKREG r3, 0x23030000;
 179 CHECKREG r4, 0x23040000;
 180 CHECKREG r5, 0x23050000;
 181 CHECKREG r6, 0x23237809;
 182 CHECKREG r7, 0x23070000;
 183
 184 imm32 r0, 0xd00100e0;
 185 imm32 r1, 0xd00100e0;
 186 imm32 r2, 0xd00200e0;
 187 imm32 r3, 0xd00300e0;
 188 imm32 r4, 0xd00400e0;
 189 imm32 r5, 0xd00500e0;
 190 imm32 r6, 0xd00600e0;
 191 imm32 r7, 0x00012345;
 192 R1 = DEPOSIT( R0, R7 );
 193 R2 = DEPOSIT( R1, R7 );
 194 R3 = DEPOSIT( R2, R7 );
 195 R4 = DEPOSIT( R3, R7 );
 196 R5 = DEPOSIT( R4, R7 ) (X);
 197 R6 = DEPOSIT( R5, R7 );
 198 R7 = DEPOSIT( R6, R7 ) (X);
 199 R0 = DEPOSIT( R7, R7 );
 200 CHECKREG r0, 0x00000000;
 201 CHECKREG r1, 0xD0010008;
 202 CHECKREG r2, 0xD0010008;
 203 CHECKREG r3, 0xD0010008;
 204 CHECKREG r4, 0xD0010008;
 205 CHECKREG r5, 0x00000008;
 206 CHECKREG r6, 0x00000008;
 207 CHECKREG r7, 0x00000008;
 208
 209
 210 pass