sim/testsuite/sim/bfin/c_dsp32shift_ones.s

   1 //Original:/testcases/core/c_dsp32shift_ones/c_dsp32shift_ones.dsp
   2 // Spec Reference: dsp32shift ones
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8
   9
  10
  11 imm32 r0, 0x88880000;
  12 imm32 r1, 0x34560001;
  13 imm32 r2, 0x08000002;
  14 imm32 r3, 0x08000003;
  15 imm32 r4, 0x08000004;
  16 imm32 r5, 0x08000005;
  17 imm32 r6, 0x08000006;
  18 imm32 r7, 0x08000007;
  19 R7.L = ONES R0;
  20 R1.L = ONES R0;
  21 R2.L = ONES R0;
  22 R3.L = ONES R0;
  23 R4.L = ONES R0;
  24 R5.L = ONES R0;
  25 R6.L = ONES R0;
  26 R0.L = ONES R0;
  27 CHECKREG r1, 0x34560004;
  28 CHECKREG r0, 0x88880004;
  29 CHECKREG r2, 0x08000004;
  30 CHECKREG r3, 0x08000004;
  31 CHECKREG r4, 0x08000004;
  32 CHECKREG r5, 0x08000004;
  33 CHECKREG r6, 0x08000004;
  34 CHECKREG r7, 0x08000004;
  35
  36 imm32 r0, 0x9999d001;
  37 imm32 r1, 0x00000001;
  38 imm32 r2, 0x0000d002;
  39 imm32 r3, 0x0000d003;
  40 imm32 r4, 0x0000d004;
  41 imm32 r5, 0x0000d005;
  42 imm32 r6, 0x0000d006;
  43 imm32 r7, 0x0000d007;
  44 R0.L = ONES R1;
  45 R7.L = ONES R1;
  46 R2.L = ONES R1;
  47 R3.L = ONES R1;
  48 R4.L = ONES R1;
  49 R5.L = ONES R1;
  50 R6.L = ONES R1;
  51 R1.L = ONES R1;
  52 CHECKREG r0, 0x99990001;
  53 CHECKREG r1, 0x00000001;
  54 CHECKREG r2, 0x00000001;
  55 CHECKREG r3, 0x00000001;
  56 CHECKREG r4, 0x00000001;
  57 CHECKREG r5, 0x00000001;
  58 CHECKREG r6, 0x00000001;
  59 CHECKREG r7, 0x00000001;
  60
  61
  62 imm32 r0, 0xaaaae001;
  63 imm32 r1, 0x0000e001;
  64 imm32 r2, 0xaaaa000f;
  65 imm32 r3, 0x0000e003;
  66 imm32 r4, 0x0000e004;
  67 imm32 r5, 0x0000e005;
  68 imm32 r6, 0x0000e006;
  69 imm32 r7, 0x0000e007;
  70 R0.L = ONES R2;
  71 R1.L = ONES R2;
  72 R7.L = ONES R2;
  73 R3.L = ONES R2;
  74 R4.L = ONES R2;
  75 R5.L = ONES R2;
  76 R6.L = ONES R2;
  77 R2.L = ONES R2;
  78 CHECKREG r0, 0xAAAA000C;
  79 CHECKREG r1, 0x0000000C;
  80 CHECKREG r2, 0xAAAA000C;
  81 CHECKREG r3, 0x0000000C;
  82 CHECKREG r4, 0x0000000C;
  83 CHECKREG r5, 0x0000000C;
  84 CHECKREG r6, 0x0000000C;
  85 CHECKREG r7, 0x0000000C;
  86
  87 imm32 r0, 0x0000f001;
  88 imm32 r1, 0x0000f001;
  89 imm32 r2, 0x0000f002;
  90 imm32 r3, 0xbbbb0010;
  91 imm32 r4, 0x0000f004;
  92 imm32 r5, 0x0000f005;
  93 imm32 r6, 0x0000f006;
  94 imm32 r7, 0x0000f007;
  95 R0.L = ONES R3;
  96 R1.L = ONES R3;
  97 R2.L = ONES R3;
  98 R7.L = ONES R3;
  99 R4.L = ONES R3;
 100 R5.L = ONES R3;
 101 R6.L = ONES R3;
 102 R3.L = ONES R3;
 103 CHECKREG r0, 0x0000000D;
 104 CHECKREG r1, 0x0000000D;
 105 CHECKREG r2, 0x0000000D;
 106 CHECKREG r3, 0xBBBB000D;
 107 CHECKREG r4, 0x0000000D;
 108 CHECKREG r5, 0x0000000D;
 109 CHECKREG r6, 0x0000000D;
 110 CHECKREG r7, 0x0000000D;
 111
 112 imm32 r0, 0x00000000;
 113 imm32 r1, 0x00010000;
 114 imm32 r2, 0x00020000;
 115 imm32 r3, 0x00030000;
 116 imm32 r4, 0xcccc0000;
 117 imm32 r5, 0x00050000;
 118 imm32 r6, 0x00060000;
 119 imm32 r7, 0x00070000;
 120 R0.L = ONES R4;
 121 R1.L = ONES R4;
 122 R2.L = ONES R4;
 123 R3.L = ONES R4;
 124 R7.L = ONES R4;
 125 R5.L = ONES R4;
 126 R6.L = ONES R4;
 127 R4.L = ONES R4;
 128 CHECKREG r0, 0x00000008;
 129 CHECKREG r1, 0x00010008;
 130 CHECKREG r2, 0x00020008;
 131 CHECKREG r3, 0x00030008;
 132 CHECKREG r4, 0xCCCC0008;
 133 CHECKREG r5, 0x00050008;
 134 CHECKREG r6, 0x00060008;
 135 CHECKREG r7, 0x00070008;
 136
 137 imm32 r0, 0xa0010000;
 138 imm32 r1, 0xa0010001;
 139 imm32 r2, 0xa0020000;
 140 imm32 r3, 0xa0030000;
 141 imm32 r4, 0xa0040000;
 142 imm32 r5, 0xaddd0000;
 143 imm32 r6, 0xa0060000;
 144 imm32 r7, 0xa0070000;
 145 R0.L = ONES R5;
 146 R1.L = ONES R5;
 147 R2.L = ONES R5;
 148 R3.L = ONES R5;
 149 R4.L = ONES R5;
 150 R7.L = ONES R5;
 151 R6.L = ONES R5;
 152 R5.L = ONES R5;
 153 CHECKREG r0, 0xA001000B;
 154 CHECKREG r1, 0xA001000B;
 155 CHECKREG r2, 0xA002000B;
 156 CHECKREG r3, 0xA003000B;
 157 CHECKREG r4, 0xA004000B;
 158 CHECKREG r5, 0xADDD000B;
 159 CHECKREG r6, 0xA006000B;
 160 CHECKREG r7, 0xA007000B;
 161
 162
 163 imm32 r0, 0xb0010000;
 164 imm32 r1, 0xb0010000;
 165 imm32 r2, 0xb002000f;
 166 imm32 r3, 0xb0030000;
 167 imm32 r4, 0xb0040000;
 168 imm32 r5, 0xb0050000;
 169 imm32 r6, 0xeeee0000;
 170 imm32 r7, 0xb0070000;
 171 R0.L = ONES R6;
 172 R1.L = ONES R6;
 173 R2.L = ONES R6;
 174 R3.L = ONES R6;
 175 R4.L = ONES R6;
 176 R5.L = ONES R6;
 177 R7.L = ONES R6;
 178 R6.L = ONES R6;
 179 CHECKREG r0, 0xB001000C;
 180 CHECKREG r1, 0xB001000C;
 181 CHECKREG r2, 0xB002000C;
 182 CHECKREG r3, 0xB003000C;
 183 CHECKREG r4, 0xB004000C;
 184 CHECKREG r5, 0xB005000C;
 185 CHECKREG r6, 0xEEEE000C;
 186 CHECKREG r7, 0xB007000C;
 187
 188 imm32 r0, 0xd0010001;
 189 imm32 r1, 0xd0010002;
 190 imm32 r2, 0xd0020003;
 191 imm32 r3, 0xd0030014;
 192 imm32 r4, 0xd0040005;
 193 imm32 r5, 0xd0050000;
 194 imm32 r6, 0xd0060007;
 195 imm32 r7, 0xffff0000;
 196 R0.L = ONES R7;
 197 R1.L = ONES R7;
 198 R2.L = ONES R7;
 199 R3.L = ONES R7;
 200 R4.L = ONES R7;
 201 R5.L = ONES R7;
 202 R6.L = ONES R7;
 203 R7.L = ONES R7;
 204
 205 CHECKREG r0, 0xD0010010;
 206 CHECKREG r1, 0xD0010010;
 207 CHECKREG r2, 0xD0020010;
 208 CHECKREG r3, 0xD0030010;
 209 CHECKREG r4, 0xD0040010;
 210 CHECKREG r5, 0xD0050010;
 211 CHECKREG r6, 0xD0060010;
 212 CHECKREG r7, 0xFFFF0010;
 213
 214 pass