sim/testsuite/sim/bfin/c_dsp32shiftim_ahalf_rn_s.s

   1 //Original:/testcases/core/c_dsp32shiftim_ahalf_rn_s/c_dsp32shiftim_ahalf_rn_s.dsp
   2 // Spec Reference: dsp32shift ashift
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8
   9
  10 imm32 r0, 0x00000000;
  11 R0.L = -1;
  12 imm32 r1, 0x00008001;
  13 imm32 r2, 0x00008002;
  14 imm32 r3, 0x00008003;
  15 imm32 r4, 0x00008004;
  16 imm32 r5, 0x00008005;
  17 imm32 r6, 0x00008006;
  18 imm32 r7, 0x00008007;
  19 R0.L = R0.L >>> 10;
  20 R1.L = R1.L >>> 10;
  21 R2.L = R2.L >>> 10;
  22 R3.L = R3.L >>> 10;
  23 R4.L = R4.L >>> 10;
  24 R5.L = R5.L >>> 10;
  25 R6.L = R6.L >>> 10;
  26 R7.L = R7.L >>> 10;
  27 CHECKREG r0, 0x0000FFFF;
  28 CHECKREG r1, 0x0000FFE0;
  29 CHECKREG r2, 0x0000FFE0;
  30 CHECKREG r3, 0x0000FFE0;
  31 CHECKREG r4, 0x0000FFE0;
  32 CHECKREG r5, 0x0000FFE0;
  33 CHECKREG r6, 0x0000FFE0;
  34 CHECKREG r7, 0x0000FFE0;
  35
  36 imm32 r0, 0x02008020;
  37 imm32 r0, 0x02008021;
  38 imm32 r2, 0x02008022;
  39 imm32 r3, 0x02008023;
  40 imm32 r4, 0x02008024;
  41 imm32 r5, 0x02008025;
  42 imm32 r6, 0x02008026;
  43 imm32 r7, 0x02008027;
  44 R0.L = R0.L >>> 11;
  45 R1.L = R1.L >>> 11;
  46 R2.L = R2.L >>> 11;
  47 R3.L = R3.L >>> 11;
  48 R4.L = R4.L >>> 11;
  49 R5.L = R5.L >>> 11;
  50 R6.L = R6.L >>> 11;
  51 R7.L = R7.L >>> 11;
  52 CHECKREG r0, 0x0200FFF0;
  53 CHECKREG r1, 0x0000FFFF;
  54 CHECKREG r2, 0x0200FFF0;
  55 CHECKREG r3, 0x0200FFF0;
  56 CHECKREG r4, 0x0200FFF0;
  57 CHECKREG r5, 0x0200FFF0;
  58 CHECKREG r6, 0x0200FFF0;
  59 CHECKREG r7, 0x0200FFF0;
  60
  61
  62 imm32 r0, 0x00308001;
  63 imm32 r1, 0x00308001;
  64 R2.L = -15;
  65 imm32 r3, 0x00308003;
  66 imm32 r4, 0x00308004;
  67 imm32 r5, 0x00308005;
  68 imm32 r6, 0x00308006;
  69 imm32 r7, 0x00308007;
  70 R0.L = R0.L >>> 12;
  71 R1.L = R1.L >>> 12;
  72 R2.L = R2.L >>> 12;
  73 R3.L = R3.L >>> 12;
  74 R4.L = R4.L >>> 12;
  75 R5.L = R5.L >>> 12;
  76 R6.L = R6.L >>> 12;
  77 R7.L = R7.L >>> 12;
  78 CHECKREG r0, 0x0030FFF8;
  79 CHECKREG r1, 0x0030FFF8;
  80 CHECKREG r2, 0x0200FFFF;
  81 CHECKREG r3, 0x0030FFF8;
  82 CHECKREG r4, 0x0030FFF8;
  83 CHECKREG r5, 0x0030FFF8;
  84 CHECKREG r6, 0x0030FFF8;
  85 CHECKREG r7, 0x0030FFF8;
  86
  87 imm32 r0, 0x00008401;
  88 imm32 r1, 0x00008401;
  89 imm32 r2, 0x00008402;
  90 R3.L = -16;
  91 imm32 r4, 0x00008404;
  92 imm32 r5, 0x00008405;
  93 imm32 r6, 0x00008406;
  94 imm32 r7, 0x00008407;
  95 R0.L = R0.L >>> 3;
  96 R1.L = R1.L >>> 3;
  97 R2.L = R2.L >>> 3;
  98 R3.L = R3.L >>> 3;
  99 R4.L = R4.L >>> 3;
 100 R5.L = R5.L >>> 3;
 101 R6.L = R6.L >>> 3;
 102 R7.L = R7.L >>> 3;
 103 CHECKREG r0, 0x0000F080;
 104 CHECKREG r1, 0x0000F080;
 105 CHECKREG r2, 0x0000F080;
 106 CHECKREG r3, 0x0030FFFE;
 107 CHECKREG r4, 0x0000F080;
 108 CHECKREG r5, 0x0000F080;
 109 CHECKREG r6, 0x0000F080;
 110 CHECKREG r7, 0x0000F080;
 111
 112 // d_lo = ashift (d_hi BY d_lo)
 113 // RHx by RLx
 114 imm32 r0, 0x05000500;
 115 imm32 r1, 0x85010500;
 116 imm32 r2, 0x85020500;
 117 imm32 r3, 0x85030500;
 118 imm32 r4, 0x85040500;
 119 imm32 r5, 0x85050500;
 120 imm32 r6, 0x85060500;
 121 imm32 r7, 0x85070500;
 122 R0.L = R0.H >>> 10;
 123 R1.L = R1.H >>> 10;
 124 R2.L = R2.H >>> 10;
 125 R3.L = R3.H >>> 10;
 126 R4.L = R4.H >>> 10;
 127 R5.L = R5.H >>> 10;
 128 R6.L = R6.H >>> 10;
 129 R7.L = R7.H >>> 10;
 130 CHECKREG r0, 0x05000001;
 131 CHECKREG r1, 0x8501FFE1;
 132 CHECKREG r2, 0x8502FFE1;
 133 CHECKREG r3, 0x8503FFE1;
 134 CHECKREG r4, 0x8504FFE1;
 135 CHECKREG r5, 0x8505FFE1;
 136 CHECKREG r6, 0x8506FFE1;
 137 CHECKREG r7, 0x8507FFE1;
 138
 139 imm32 r0, 0x80610000;
 140 R1.L = -1;
 141 imm32 r2, 0x80620000;
 142 imm32 r3, 0x80630000;
 143 imm32 r4, 0x80640000;
 144 imm32 r5, 0x80650000;
 145 imm32 r6, 0x80660000;
 146 imm32 r7, 0x80670000;
 147 R0.L = R0.H >>> 11;
 148 R1.L = R1.H >>> 11;
 149 R2.L = R2.H >>> 11;
 150 R3.L = R3.H >>> 11;
 151 R4.L = R4.H >>> 11;
 152 R5.L = R5.H >>> 11;
 153 R6.L = R6.H >>> 11;
 154 R7.L = R7.H >>> 11;
 155 CHECKREG r0, 0x8061FFF0;
 156 CHECKREG r1, 0x8501FFF0;
 157 CHECKREG r2, 0x8062FFF0;
 158 CHECKREG r3, 0x8063FFF0;
 159 CHECKREG r4, 0x8064FFF0;
 160 CHECKREG r5, 0x8065FFF0;
 161 CHECKREG r6, 0x8066FFF0;
 162 CHECKREG r7, 0x8067FFF0;
 163
 164
 165 imm32 r0, 0xa0010070;
 166 imm32 r1, 0xa0010070;
 167 R2.L = -15;
 168 imm32 r3, 0xa0030070;
 169 imm32 r4, 0xa0040070;
 170 imm32 r5, 0xa0050070;
 171 imm32 r6, 0xa0060070;
 172 imm32 r7, 0xa0070070;
 173 R0.L = R0.H >>> 12;
 174 R1.L = R1.H >>> 12;
 175 R2.L = R2.H >>> 12;
 176 R3.L = R3.H >>> 12;
 177 R4.L = R4.H >>> 12;
 178 R5.L = R5.H >>> 12;
 179 R6.L = R6.H >>> 12;
 180 R7.L = R7.H >>> 12;
 181 CHECKREG r0, 0xA001FFFA;
 182 CHECKREG r1, 0xA001FFFA;
 183 CHECKREG r2, 0x8062FFF8;
 184 CHECKREG r3, 0xA003FFFA;
 185 CHECKREG r4, 0xA004FFFA;
 186 CHECKREG r5, 0xA005FFFA;
 187 CHECKREG r6, 0xA006FFFA;
 188 CHECKREG r7, 0xA007FFFA;
 189
 190 imm32 r0, 0xb8010001;
 191 imm32 r1, 0xb8010001;
 192 imm32 r2, 0xb8020002;
 193 R3.L = -16;
 194 imm32 r4, 0xb8040004;
 195 imm32 r5, 0xb8050005;
 196 imm32 r6, 0xb8060006;
 197 imm32 r7, 0xb8070007;
 198 R0.L = R0.H >>> 13;
 199 R1.L = R1.H >>> 13;
 200 R2.L = R2.H >>> 13;
 201 R3.L = R3.H >>> 13;
 202 R4.L = R4.H >>> 13;
 203 R5.L = R5.H >>> 13;
 204 R6.L = R6.H >>> 13;
 205 R7.L = R7.H >>> 13;
 206 CHECKREG r0, 0xB801FFFD;
 207 CHECKREG r1, 0xB801FFFD;
 208 CHECKREG r2, 0xB802FFFD;
 209 CHECKREG r3, 0xA003FFFD;
 210 CHECKREG r4, 0xB804FFFD;
 211 CHECKREG r5, 0xB805FFFD;
 212 CHECKREG r6, 0xB806FFFD;
 213 CHECKREG r7, 0xB807FFFD;
 214
 215 // d_hi = ashft (d_lo BY d_lo)
 216 // RLx by RLx
 217 imm32 r0, 0x00009001;
 218 imm32 r1, 0x00009001;
 219 imm32 r2, 0x00009002;
 220 imm32 r3, 0x00009003;
 221 imm32 r4, 0x00009000;
 222 imm32 r5, 0x00009005;
 223 imm32 r6, 0x00009006;
 224 imm32 r7, 0x00009007;
 225 R0.H = R0.L >>> 14;
 226 R1.H = R1.L >>> 14;
 227 R2.H = R2.L >>> 14;
 228 R3.H = R3.L >>> 14;
 229 R4.H = R4.L >>> 14;
 230 R5.H = R5.L >>> 14;
 231 R6.H = R6.L >>> 14;
 232 R7.H = R7.L >>> 14;
 233 CHECKREG r0, 0xFFFE9001;
 234 CHECKREG r1, 0xFFFE9001;
 235 CHECKREG r2, 0xFFFE9002;
 236 CHECKREG r3, 0xFFFE9003;
 237 CHECKREG r4, 0xFFFE9000;
 238 CHECKREG r5, 0xFFFE9005;
 239 CHECKREG r6, 0xFFFE9006;
 240 CHECKREG r7, 0xFFFE9007;
 241
 242 imm32 r0, 0xa0008001;
 243 imm32 r1, 0xa0008001;
 244 imm32 r2, 0xa0008002;
 245 imm32 r3, 0xa0008003;
 246 imm32 r4, 0xa0008004;
 247 R5.L = -1;
 248 imm32 r6, 0xa0008006;
 249 imm32 r7, 0xa0008007;
 250 R0.H = R0.L >>> 5;
 251 R1.H = R1.L >>> 5;
 252 R2.H = R2.L >>> 5;
 253 R3.H = R3.L >>> 5;
 254 R4.H = R4.L >>> 5;
 255 R5.H = R5.L >>> 5;
 256 R6.H = R6.L >>> 5;
 257 R7.H = R7.L >>> 5;
 258 CHECKREG r0, 0xFC008001;
 259 CHECKREG r1, 0xFC008001;
 260 CHECKREG r2, 0xFC008002;
 261 CHECKREG r3, 0xFC008003;
 262 CHECKREG r4, 0xFC008004;
 263 CHECKREG r5, 0xFFFFFFFF;
 264 CHECKREG r6, 0xFC008006;
 265 CHECKREG r7, 0xFC008007;
 266
 267
 268 imm32 r0, 0x00009b01;
 269 imm32 r1, 0x00009b01;
 270 imm32 r2, 0x00009b02;
 271 imm32 r3, 0x00009b03;
 272 imm32 r4, 0x00009b04;
 273 imm32 r5, 0x00009b05;
 274 R6.L = -15;
 275 imm32 r7, 0x00009007;
 276 R0.H = R0.L >>> 6;
 277 R1.H = R1.L >>> 6;
 278 R2.H = R2.L >>> 6;
 279 R3.H = R3.L >>> 6;
 280 R4.H = R4.L >>> 6;
 281 R5.H = R5.L >>> 6;
 282 R6.H = R6.L >>> 6;
 283 R7.H = R7.L >>> 6;
 284 CHECKREG r0, 0xFE6C9B01;
 285 CHECKREG r1, 0xFE6C9B01;
 286 CHECKREG r2, 0xFE6C9B02;
 287 CHECKREG r3, 0xFE6C9B03;
 288 CHECKREG r4, 0xFE6C9B04;
 289 CHECKREG r5, 0xFE6C9B05;
 290 CHECKREG r6, 0xFFFFFFF1;
 291 CHECKREG r7, 0xFE409007;
 292
 293 imm32 r0, 0x0000a0c1;
 294 imm32 r1, 0x0000a0c1;
 295 imm32 r2, 0x0000a0c2;
 296 imm32 r3, 0x0000a0c3;
 297 imm32 r4, 0x0000a0c4;
 298 imm32 r5, 0x0000a0c5;
 299 imm32 r6, 0x0000a0c6;
 300 R7.L = -16;
 301 R0.H = R0.L >>> 7;
 302 R1.H = R1.L >>> 7;
 303 R2.H = R2.L >>> 7;
 304 R3.H = R3.L >>> 7;
 305 R4.H = R4.L >>> 7;
 306 R5.H = R5.L >>> 7;
 307 R6.H = R6.L >>> 7;
 308 R7.H = R7.L >>> 7;
 309 CHECKREG r0, 0xFF41A0C1;
 310 CHECKREG r1, 0xFF41A0C1;
 311 CHECKREG r2, 0xFF41A0C2;
 312 CHECKREG r3, 0xFF41A0C3;
 313 CHECKREG r4, 0xFF41A0C4;
 314 CHECKREG r5, 0xFF41A0C5;
 315 CHECKREG r6, 0xFF41A0C6;
 316 CHECKREG r7, 0xFFFFFFF0;
 317
 318 imm32 r0, 0x80010d00;
 319 imm32 r1, 0x80010d00;
 320 imm32 r2, 0x80020d00;
 321 imm32 r3, 0x80030d00;
 322 R4.L = -1;
 323 imm32 r5, 0x80050d00;
 324 imm32 r6, 0x80060d00;
 325 imm32 r7, 0x80070d00;
 326 R0.H = R0.H >>> 14;
 327 R1.H = R1.H >>> 14;
 328 R2.H = R2.H >>> 14;
 329 R3.H = R3.H >>> 14;
 330 R4.H = R4.H >>> 14;
 331 R5.H = R5.H >>> 14;
 332 R6.H = R6.H >>> 14;
 333 R7.H = R7.H >>> 14;
 334 CHECKREG r0, 0xFFFE0D00;
 335 CHECKREG r1, 0xFFFE0D00;
 336 CHECKREG r2, 0xFFFE0D00;
 337 CHECKREG r3, 0xFFFE0D00;
 338 CHECKREG r4, 0xFFFFFFFF;
 339 CHECKREG r5, 0xFFFE0D00;
 340 CHECKREG r6, 0xFFFE0D00;
 341 CHECKREG r7, 0xFFFE0D00;
 342
 343 imm32 r0, 0x8d010000;
 344 imm32 r1, 0x8d010000;
 345 imm32 r2, 0x8d020000;
 346 imm32 r3, 0x8d030000;
 347 imm32 r4, 0x8d040000;
 348 R5.L = -1;
 349 imm32 r6, 0x8d060000;
 350 imm32 r7, 0x8d070000;
 351 R0.H = R0.H >>> 15;
 352 R1.H = R1.H >>> 15;
 353 R2.H = R2.H >>> 15;
 354 R3.H = R3.H >>> 15;
 355 R4.H = R4.H >>> 15;
 356 R5.H = R5.H >>> 15;
 357 R6.H = R6.H >>> 15;
 358 R7.H = R7.H >>> 15;
 359 CHECKREG r0, 0xFFFF0000;
 360 CHECKREG r1, 0xFFFF0000;
 361 CHECKREG r2, 0xFFFF0000;
 362 CHECKREG r3, 0xFFFF0000;
 363 CHECKREG r4, 0xFFFF0000;
 364 CHECKREG r5, 0xFFFFFFFF;
 365 CHECKREG r6, 0xFFFF0000;
 366 CHECKREG r7, 0xFFFF0000;
 367
 368
 369 imm32 r0, 0xde010000;
 370 imm32 r1, 0xde010000;
 371 imm32 r2, 0xde020000;
 372 imm32 r3, 0xde030000;
 373 imm32 r4, 0xde040000;
 374 imm32 r5, 0xde050000;
 375 R6.L = -15;
 376 imm32 r7, 0xd0070000;
 377 R0.L = R0.H >>> 10;
 378 R1.L = R1.H >>> 10;
 379 R2.L = R2.H >>> 10;
 380 R3.L = R3.H >>> 10;
 381 R4.L = R4.H >>> 10;
 382 R5.L = R5.H >>> 10;
 383 R6.L = R6.H >>> 10;
 384 R7.L = R7.H >>> 10;
 385 CHECKREG r0, 0xDE01FFF7;
 386 CHECKREG r1, 0xDE01FFF7;
 387 CHECKREG r2, 0xDE02FFF7;
 388 CHECKREG r3, 0xDE03FFF7;
 389 CHECKREG r4, 0xDE04FFF7;
 390 CHECKREG r5, 0xDE05FFF7;
 391 CHECKREG r6, 0xFFFFFFFF;
 392 CHECKREG r7, 0xD007FFF4;
 393
 394 imm32 r0, 0x9f010c00;
 395 imm32 r1, 0xaf010c00;
 396 imm32 r2, 0xbf020c00;
 397 imm32 r3, 0xcf030c00;
 398 imm32 r4, 0xdf040c00;
 399 imm32 r5, 0xef050c00;
 400 imm32 r6, 0xff060c00;
 401 R7.L = -16;
 402 R0.H = R0.H >>> 5;
 403 R1.H = R1.H >>> 5;
 404 R2.H = R2.H >>> 5;
 405 R3.H = R3.H >>> 5;
 406 R4.H = R4.H >>> 5;
 407 R5.H = R5.H >>> 5;
 408 R6.H = R6.H >>> 5;
 409 R7.H = R7.H >>> 5;
 410 CHECKREG r0, 0xFCF80C00;
 411 CHECKREG r1, 0xFD780C00;
 412 CHECKREG r2, 0xFDF80C00;
 413 CHECKREG r3, 0xFE780C00;
 414 CHECKREG r4, 0xFEF80C00;
 415 CHECKREG r5, 0xFF780C00;
 416 CHECKREG r6, 0xFFF80C00;
 417 CHECKREG r7, 0xFE80FFF0;
 418 pass