sim/testsuite/sim/bfin/c_interr_excpt.S

   1 //Original:/proj/frio/dv/testcases/core/c_interr_excpt/c_interr_excpt.dsp
   2 // Spec Reference: interr excpt
   3 # mach: bfin
   4 # sim: --environment operating
   5
   6 #include "test.h"
   7 .include "testutils.inc"
   8 start
   9
  10 include(std.inc)
  11 include(selfcheck.inc)
  12 include(gen_int.inc)
  13 INIT_R_REGS(0);
  14 INIT_P_REGS(0);
  15 INIT_I_REGS(0);     // initialize the dsp address regs
  16 INIT_M_REGS(0);
  17 INIT_L_REGS(0);
  18 INIT_B_REGS(0);
  19 //CHECK_INIT(p5, 0xe0000000);
  20 include(symtable.inc)
  21 CHECK_INIT_DEF(p5);
  22
  23
  24 #ifndef STACKSIZE
  25 #define STACKSIZE 0x10
  26 #endif
  27 #ifndef EVT
  28 #define EVT  0xFFE02000
  29 #endif
  30 #ifndef EVT15
  31 #define EVT15  0xFFE0203C
  32 #endif
  33 #ifndef EVT_OVERRIDE
  34 #define EVT_OVERRIDE 0xFFE02100
  35 #endif
  36 #ifndef ITABLE
  37 #define ITABLE 0xF0000000
  38 #endif
  39
  40 GEN_INT_INIT(ITABLE) // set location for interrupt table
  41
  42 //
  43 // Reset/Bootstrap Code
  44 //   (Here we should set the processor operating modes, initialize registers,
  45 //    etc.)
  46 //
  47
  48 BOOT:
  49
  50
  51 LD32_LABEL(sp, KSTACK);   // setup the stack pointer
  52 FP = SP;        // and frame pointer
  53
  54 LD32(p0, EVT);      // Setup Event Vectors and Handlers
  55 LD32_LABEL(r0, EHANDLE);  // Emulation Handler (Int0)
  56     [ P0 ++ ] = R0;
  57
  58 LD32_LABEL(r0, RHANDLE);  // Reset Handler (Int1)
  59     [ P0 ++ ] = R0;
  60
  61 LD32_LABEL(r0, NHANDLE);  // NMI Handler (Int2)
  62     [ P0 ++ ] = R0;
  63
  64 LD32_LABEL(r0, XHANDLE);  // Exception Handler (Int3)
  65     [ P0 ++ ] = R0;
  66
  67     [ P0 ++ ] = R0;        // IVT4 not used
  68
  69 LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
  70     [ P0 ++ ] = R0;
  71
  72 LD32_LABEL(r0, THANDLE);  // Timer Handler (Int6)
  73     [ P0 ++ ] = R0;
  74
  75 LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
  76     [ P0 ++ ] = R0;
  77
  78 LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
  79     [ P0 ++ ] = R0;
  80
  81 LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
  82     [ P0 ++ ] = R0;
  83
  84 LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
  85     [ P0 ++ ] = R0;
  86
  87 LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
  88     [ P0 ++ ] = R0;
  89
  90 LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
  91     [ P0 ++ ] = R0;
  92
  93 LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
  94     [ P0 ++ ] = R0;
  95
  96 LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
  97     [ P0 ++ ] = R0;
  98
  99 LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
 100     [ P0 ++ ] = R0;
 101
 102 LD32(p0, EVT_OVERRIDE);
 103     R0 = 0;
 104     [ P0 ++ ] = R0;
 105     R0 = -1;     // Change this to mask interrupts (*)
 106     [ P0 ] = R0;   // IMASK
 107
 108 DUMMY:
 109
 110     R0 = 0 (Z);
 111
 112 LT0 = r0;       // set loop counters to something deterministic
 113 LB0 = r0;
 114 LC0 = r0;
 115 LT1 = r0;
 116 LB1 = r0;
 117 LC1 = r0;
 118
 119 ASTAT = r0;     // reset other internal regs
 120 SYSCFG = r0;
 121 RETS = r0;      // prevent X's breaking LINK instruction
 122
 123
 124 // The following code sets up the test for running in USER mode
 125
 126 LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
 127                         // ReturnFromInterrupt (RTI)
 128 RETI = r0;      // We need to load the return address
 129
 130 // Comment the following line for a USER Mode test
 131
 132 JUMP    STARTSUP;   // jump to code start for SUPERVISOR mode
 133
 134 RTI;
 135
 136 STARTSUP:
 137 LD32_LABEL(p1, BEGIN);
 138
 139 LD32(p0, EVT15);
 140     [ P0 ] = P1;   // IVG15 (General) handler (Int 15) load with start
 141 CSYNC;
 142 RAISE 15;       // after we RTI, INT 15 should be taken
 143
 144 RTI;
 145
 146 //
 147 // The Main Program
 148 //
 149 STARTUSER:
 150 LD32_LABEL(sp, USTACK);   // setup the stack pointer
 151 FP = SP;            // set frame pointer
 152 JUMP BEGIN;
 153
 154 //*********************************************************************
 155
 156 BEGIN:
 157
 158                 // COMMENT the following line for USER MODE tests
 159     [ -- SP ] = RETI;  // enable interrupts in supervisor mode
 160
 161                 // **** YOUR CODE GOES HERE ****
 162
 163
 164
 165     // PUT YOUR TEST HERE!
 166                 // Can't Raise 0, 3, or 4
 167                 // Raise 1 requires some intelligence so the test
 168                 //  doesn't loop forever - use SFTRESET bit in SEQSTAT (TBD)
 169
 170     R0 = 1;
 171     R1 = 2;
 172     R2 = 3;
 173     R3 = 4;
 174
 175
 176 EXCPT 1;    // RTX
 177 EXCPT 2;    // RTX
 178 EXCPT 3;    // RTX
 179 EXCPT 4;    // RTX
 180 EXCPT 5;    // RTX
 181 EXCPT 5;    // RTX
 182 EXCPT 6;    // RTX
 183 EXCPT 7;    // RTX
 184 EXCPT 8;    // RTX
 185 EXCPT 9;    // RTX
 186 EXCPT 10;    // RTX
 187 EXCPT 11;    // RTX
 188 EXCPT 12;    // RTX
 189 EXCPT 13;    // RTX
 190 EXCPT 14;    // RTX
 191 EXCPT 15;    // RTX
 192
 193 CHECKREG(r0, 0x33333333);
 194 CHECKREG(r1, 0xCCCCCCCD);
 195 CHECKREG(r2, 0x00000000);
 196 CHECKREG(r3, 0x33333333);
 197 CHECKREG(r4, 0x00000000);
 198 CHECKREG(r5, 0x00000000);
 199 CHECKREG(r6, 0x00000000);
 200 CHECKREG(r7, 0x00000000);
 201
 202
 203 END:
 204 dbg_pass;            // End the test
 205
 206 //*********************************************************************
 207
 208 //
 209 // Handlers for Events
 210 //
 211
 212 EHANDLE:            // Emulation Handler 0
 213 RTE;
 214
 215 RHANDLE:            // Reset Handler 1
 216 RTI;
 217
 218 NHANDLE:            // NMI Handler 2
 219     R0 = 2;
 220 RTN;
 221
 222 XHANDLE:            // Exception Handler 3
 223     R0 = R1 + R2;
 224     R1 = R2 + R3;
 225     R2 = R0 + R1;
 226     R3 = R0 + R2;
 227 RTX;
 228
 229 HWHANDLE:           // HW Error Handler 5
 230     R2 = 5;
 231 RTI;
 232
 233 THANDLE:            // Timer Handler 6
 234     R3 = 6;
 235 RTI;
 236
 237 I7HANDLE:           // IVG 7 Handler
 238     R4 = 7;
 239 RTI;
 240
 241 I8HANDLE:           // IVG 8 Handler
 242     R5 = 8;
 243 RTI;
 244
 245 I9HANDLE:           // IVG 9 Handler
 246     R6 = 9;
 247 RTI;
 248
 249 I10HANDLE:          // IVG 10 Handler
 250     R7 = 10;
 251 RTI;
 252
 253 I11HANDLE:          // IVG 11 Handler
 254     R0 = 11;
 255 RTI;
 256
 257 I12HANDLE:          // IVG 12 Handler
 258     R1 = 12;
 259 RTI;
 260
 261 I13HANDLE:          // IVG 13 Handler
 262     R2 = 13;
 263 RTI;
 264
 265 I14HANDLE:          // IVG 14 Handler
 266     R3 = 14;
 267 RTI;
 268
 269 I15HANDLE:          // IVG 15 Handler
 270     R4 = 15;
 271 RTI;
 272
 273 NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
 274
 275 //
 276 // Data Segment
 277 //
 278
 279 //.data 0xF0000000
 280 .data
 281 DATA:
 282     .space (0x10);
 283
 284 // Stack Segments (Both Kernel and User)
 285
 286     .space (STACKSIZE);
 287 KSTACK:
 288
 289     .space (STACKSIZE);
 290 USTACK: