sim/testsuite/sim/bfin/c_interr_timer.S

   1 //Original:/proj/frio/dv/testcases/core/c_interr_timer/c_interr_timer.dsp
   2 // Spec Reference: interrupt on HW TIMER
   3 # mach: bfin
   4 # sim: --environment operating
   5
   6 #include "test.h"
   7 .include "testutils.inc"
   8 start
   9
  10 //
  11 // Include Files
  12 //
  13
  14 include(std.inc)
  15 include(selfcheck.inc)
  16
  17 // Defines
  18
  19 #ifndef TCNTL
  20 #define TCNTL            0xFFE03000
  21 #endif
  22 #ifndef TPERIOD
  23 #define TPERIOD          0xFFE03004
  24 #endif
  25 #ifndef TSCALE
  26 #define TSCALE           0xFFE03008
  27 #endif
  28 #ifndef TCOUNT
  29 #define TCOUNT           0xFFE0300c
  30 #endif
  31 #ifndef EVT
  32 #define EVT              0xFFE02000
  33 #endif
  34 #ifndef EVT15
  35 #define EVT15            0xFFE0203c
  36 #endif
  37 #ifndef EVT_OVERRIDE
  38 #define EVT_OVERRIDE     0xFFE02100
  39 #endif
  40 #ifndef ITABLE
  41 #define ITABLE           0x000FF000
  42 #endif
  43 #ifndef PROGRAM_STACK
  44 #define PROGRAM_STACK    0x000FF100
  45 #endif
  46 #ifndef STACKSIZE
  47 #define STACKSIZE        0x00000300
  48 #endif
  49
  50 // Boot code
  51
  52  BOOT :
  53 INIT_R_REGS(0);                             // Initialize Dregs
  54 INIT_P_REGS(0);                             // Initialize Pregs
  55
  56      // CHECK_INIT(p5,   0xE0000000);
  57 include(symtable.inc)
  58 CHECK_INIT_DEF(p5);
  59
  60
  61 LD32(sp, 0x000FF200);
  62 LD32(p0, EVT);              // Setup Event Vectors and Handlers
  63
  64 LD32_LABEL(r0, EHANDLE);    // Emulation Handler (Int0)
  65         [ P0 ++ ] = R0;
  66
  67 LD32_LABEL(r0, RHANDLE);    // Reset Handler (Int1)
  68         [ P0 ++ ] = R0;
  69
  70 LD32_LABEL(r0, NHANDLE);    // NMI Handler (Int2)
  71         [ P0 ++ ] = R0;
  72
  73 LD32_LABEL(r0, XHANDLE);    // Exception Handler (Int3)
  74         [ P0 ++ ] = R0;
  75
  76         [ P0 ++ ] = R0;                // IVT4 not used
  77
  78 LD32_LABEL(r0, HWHANDLE);   // HW Error Handler (Int5)
  79         [ P0 ++ ] = R0;
  80
  81 LD32_LABEL(r0, THANDLE);    // Timer Handler (Int6)
  82         [ P0 ++ ] = R0;
  83
  84 LD32_LABEL(r0, I7HANDLE);   // IVG7 Handler
  85         [ P0 ++ ] = R0;
  86
  87 LD32_LABEL(r0, I8HANDLE);   // IVG8 Handler
  88         [ P0 ++ ] = R0;
  89
  90 LD32_LABEL(r0, I9HANDLE);   // IVG9 Handler
  91         [ P0 ++ ] = R0;
  92
  93 LD32_LABEL(r0, I10HANDLE);  // IVG10 Handler
  94         [ P0 ++ ] = R0;
  95
  96 LD32_LABEL(r0, I11HANDLE);  // IVG11 Handler
  97         [ P0 ++ ] = R0;
  98
  99 LD32_LABEL(r0, I12HANDLE);  // IVG12 Handler
 100         [ P0 ++ ] = R0;
 101
 102 LD32_LABEL(r0, I13HANDLE);  // IVG13 Handler
 103         [ P0 ++ ] = R0;
 104
 105 LD32_LABEL(r0, I14HANDLE);  // IVG14 Handler
 106         [ P0 ++ ] = R0;
 107
 108 LD32_LABEL(r0, I15HANDLE);  // IVG15 Handler
 109         [ P0 ++ ] = R0;
 110
 111 LD32(p0, EVT_OVERRIDE);
 112         R0 = 0;
 113         [ P0 ++ ] = R0;
 114         R0 = -1;     // Change this to mask interrupts (*)
 115         [ P0 ] = R0;   // IMASK
 116
 117 LD32_LABEL(p1, START);
 118
 119 LD32(p0, EVT15);
 120         [ P0 ] = P1;   // IVG15 (General) handler (Int 15) load with start
 121 CSYNC;
 122 RAISE 15;    // after we RTI, INT 15 should be taken
 123
 124 LD32_LABEL(r7, START);
 125 RETI = r7;
 126 NOP;        // Workaround for Bug 217
 127 RTI;
 128 NOP;
 129 NOP;
 130 NOP;
 131 NOP;
 132 NOP;
 133 NOP;
 134 NOP;
 135 NOP;
 136 DUMMY:
 137           NOP;
 138 NOP;
 139 NOP;
 140 NOP;
 141 NOP;
 142 NOP;
 143 NOP;
 144 NOP;
 145 NOP;
 146 NOP;
 147
 148 //.code 0x200
 149  START :
 150         R7 = 0x0;
 151         R6 = 0x1;
 152         [ -- SP ] = RETI;        // Enable Nested Interrupts
 153
 154 WR_MMR(TCNTL,   0x00000001, p0, r0);        // Turn ON TMPWR(0) (active state)
 155 WR_MMR(TPERIOD, 0x00000050, p0, r0);
 156     //  WR_MMR(TCOUNT,  0x00000013, p0, r0);
 157 WR_MMR(TCOUNT,  0x00000000, p0, r0);
 158 WR_MMR(TSCALE,  0x00000000, p0, r0);
 159 CSYNC;
 160         // Read the contents of the Timer
 161
 162 RD_MMR(TPERIOD, p0, r2);
 163 CHECKREG(r2,    0x00000050);
 164
 165
 166 WR_MMR(TCNTL,   0x00000003, p0, r0);    // enable Timer (TMPWR(0), TMREN(1))
 167 CSYNC;                                  // TIMER interrupt
 168
 169 RD_MMR(TCOUNT, p0, r3);
 170 CSYNC;
 171 CHECKREG(r3,    0x00000000);
 172 CHECKREG(r7,    0x00000001);
 173 WR_MMR(TCNTL,   0x00000001, p0, r0);    // enable Timer (TMPWR(0), TMREN(1)=0)
 174 WR_MMR(TCOUNT,  0x00000013, p0, r0);
 175 WR_MMR(TCNTL,   0x00000003, p0, r0);    // enable Timer (TMPWR(0), TMREN(1))
 176 CSYNC;
 177 NOP; NOP; NOP;
 178 NOP; NOP; NOP;
 179 NOP; NOP; NOP;
 180 NOP; NOP; NOP;
 181 NOP; NOP; NOP;
 182 NOP; NOP; NOP;
 183 NOP; NOP; NOP;
 184 NOP; NOP; NOP;
 185 RD_MMR(TCOUNT, p0, r4);
 186 CHECKREG(r4,    0x00000000);
 187
 188 RD_MMR(TCNTL, p0, r5);
 189 CHECKREG(r5,    0x0000000B);
 190
 191 WR_MMR(TCNTL,   0x00000000, p0, r0);        // Turn OFF Timer
 192 CSYNC;
 193 NOP;
 194 WR_MMR(TCNTL,   0x00000001, p0, r0);        // Turn ON Timer Power
 195 WR_MMR(TCNTL,   0x00000003, p0, r0);        // Turn ON Power, EN -> interr
 196 CSYNC;
 197 CHECKREG(r7,    0x00000003);              // 3 interr already happened
 198         R7 = 0;                                     // reset r7
 199 WR_MMR(TPERIOD, 0x00000040, p0, r0);
 200 WR_MMR(TCOUNT,  0x00000013, p0, r0);
 201 WR_MMR(TSCALE,  0x00000002, p0, r0);
 202 WR_MMR(TCNTL,   0x00000007, p0, r0);        // Turn ON Timer auto load
 203 CSYNC;
 204 NOP;
 205 NOP;
 206 NOP;
 207 NOP;
 208 NOP;
 209 NOP;
 210 NOP;
 211 NOP;
 212 NOP;
 213 NOP;
 214 NOP;
 215 NOP;
 216 NOP;
 217 NOP;
 218 NOP;
 219 JUMP.S label4;
 220         R4.L = 0x1111;                             // Will be killed
 221         R4.H = 0x1111;                             // Will be killed
 222 NOP;
 223 NOP;
 224 NOP;
 225 label5: R5.H = 0x7777;
 226         R5.L = 0x7888;
 227 JUMP.S label6;
 228         R5.L = 0x1111;                             // Will be killed
 229         R5.H = 0x1111;                             // Will be killed
 230 NOP;
 231 NOP;
 232 NOP;
 233 NOP;
 234 NOP;
 235 NOP;
 236 label4: R4.H = 0x5555;
 237         R4.L = 0x6666;
 238 NOP;
 239 JUMP.S label5;
 240         R5.L = 0x2222;     // Will be killed
 241         R5.H = 0x2222;     // Will be killed
 242 NOP;
 243 NOP;
 244 NOP;
 245 NOP;
 246 label6: R3.H = 0x7999;
 247         R3.L = 0x7aaa;
 248 NOP;
 249 NOP;
 250 NOP;
 251 NOP;
 252 NOP;
 253 NOP;
 254 NOP;
 255                                                     // With auto reload
 256         // Read the contents of the Timer
 257
 258 RD_MMR(TPERIOD, p0, r2);
 259 CHECKREG(r2,    0x00000040);
 260
 261 //      CHECKREG(r7,    0x00000002);
 262 CC = R7 == 0;
 263 IF !CC JUMP LABEL1;
 264 WR_MMR(TPERIOD, 0x00000030, p0, r0);   // SHOULD NOT EXECUTE
 265
 266 LABEL1:
 267
 268 NOP; NOP; NOP; NOP; NOP;
 269 NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
 270 NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
 271 NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
 272 NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
 273 NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
 274
 275
 276 RD_MMR(TCNTL , p0, r3);
 277 CHECKREG(r3,    0x0000000F);
 278
 279
 280 WR_MMR(TCNTL,   0x00000003, p0, r0);        // Turn ON Timer
 281 CSYNC;
 282 RD_MMR(TPERIOD, p0, r2);
 283 CHECKREG(r2,    0x00000040);
 284
 285
 286 NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
 287 NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
 288 NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
 289 NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
 290 NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
 291 NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
 292 NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
 293 NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
 294 NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
 295 NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
 296 NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
 297 NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
 298 NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
 299 NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
 300 NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
 301 NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
 302 NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
 303 RD_MMR(TCOUNT, p0, r4);
 304 CHECKREG(r4,    0x00000000);
 305
 306 RD_MMR(TCNTL, p0, r5);
 307 CHECKREG(r5,    0x0000000B);
 308
 309 WR_MMR(TCNTL,   0x00000000, p0, r0);        // Turn OFF Timer
 310 CSYNC;
 311 NOP; NOP; NOP;
 312
 313 WR_MMR(TPERIOD, 0x00000060, p0, r0);
 314 CSYNC;
 315 NOP;
 316 RD_MMR(TPERIOD, p0, r6);
 317 CHECKREG(r6,    0x00000060);
 318
 319
 320
 321
 322 dbg_pass;        // Call Endtest Macro
 323
 324
 325
 326 //*********************************************************************
 327 //
 328 // Handlers for Events
 329 //
 330
 331 EHANDLE:            // Emulation Handler 0
 332 RTE;
 333
 334 RHANDLE:            // Reset Handler 1
 335 RTI;
 336
 337 NHANDLE:            // NMI Handler 2
 338 RTN;
 339
 340 XHANDLE:            // Exception Handler 3
 341 RTX;
 342
 343 HWHANDLE:           // HW Error Handler 5
 344 RTI;
 345
 346 THANDLE:            // Timer Handler 6
 347         R7 = R7 + R6;
 348 RTI;
 349
 350 I7HANDLE:           // IVG 7 Handler
 351 RTI;
 352
 353 I8HANDLE:           // IVG 8 Handler
 354 RTI;
 355
 356 I9HANDLE:           // IVG 9 Handler
 357 RTI;
 358
 359 I10HANDLE:          // IVG 10 Handler
 360 RTI;
 361
 362 I11HANDLE:          // IVG 11 Handler
 363 RTI;
 364
 365 I12HANDLE:          // IVG 12 Handler
 366 RTI;
 367
 368 I13HANDLE:          // IVG 13 Handler
 369 RTI;
 370
 371 I14HANDLE:          // IVG 14 Handler
 372 RTI;
 373
 374 I15HANDLE:          // IVG 15 Handler
 375         R5 = RETI;
 376         P0 = R5;
 377 JUMP ( P0 );
 378 RTI;
 379
 380 .section MEM_DATA_ADDR_1,"aw"
 381
 382 .space (STACKSIZE);
 383 STACK:
 384 NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug