sim/testsuite/sim/bfin/c_ldimmhalf_drhi.s

   1 //Original:/testcases/core/c_ldimmhalf_drhi/c_ldimmhalf_drhi.dsp
   2 // Spec Reference: ldimmhalf dreg hi
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8
   9
  10 INIT_R_REGS -1;
  11
  12 // test Dreg
  13 R0.H = 0x0001;
  14 R1.H = 0x0003;
  15 R2.H = 0x0005;
  16 R3.H = 0x0007;
  17 R4.H = 0x0009;
  18 R5.H = 0x000b;
  19 R6.H = 0x000d;
  20 R7.H = 0x000f;
  21 CHECKREG r0, 0x0001FFFF;
  22 CHECKREG r1, 0x0003FFFF;
  23 CHECKREG r2, 0x0005FFFF;
  24 CHECKREG r3, 0x0007FFFF;
  25 CHECKREG r4, 0x0009FFFF;
  26 CHECKREG r5, 0x000bFFFF;
  27 CHECKREG r6, 0x000dFFFF;
  28 CHECKREG r7, 0x000fFFFF;
  29
  30 R0.H = 0x0020;
  31 R1.H = 0x0040;
  32 R2.H = 0x0060;
  33 R3.H = 0x0080;
  34 R4.H = 0x00a0;
  35 R5.H = 0x00b0;
  36 R6.H = 0x00c0;
  37 R7.H = 0x00d0;
  38 CHECKREG r0, 0x0020FFFF;
  39 CHECKREG r1, 0x0040FFFF;
  40 CHECKREG r2, 0x0060FFFF;
  41 CHECKREG r3, 0x0080FFFF;
  42 CHECKREG r4, 0x00a0FFFF;
  43 CHECKREG r5, 0x00b0FFFF;
  44 CHECKREG r6, 0x00c0FFFF;
  45 CHECKREG r7, 0x00d0FFFF;
  46
  47 R0.H = 0x0100;
  48 R1.H = 0x0200;
  49 R2.H = 0x0300;
  50 R3.H = 0x0400;
  51 R4.H = 0x0500;
  52 R5.H = 0x0600;
  53 R6.H = 0x0700;
  54 R7.H = 0x0800;
  55 CHECKREG r0, 0x0100FFFF;
  56 CHECKREG r1, 0x0200FFFF;
  57 CHECKREG r2, 0x0300FFFF;
  58 CHECKREG r3, 0x0400FFFF;
  59 CHECKREG r4, 0x0500FFFF;
  60 CHECKREG r5, 0x0600FFFF;
  61 CHECKREG r6, 0x0700FFFF;
  62 CHECKREG r7, 0x0800FFFF;
  63
  64 R0 = 0;
  65 R1 = 0;
  66 R2 = 0;
  67 R3 = 0;
  68 R4 = 0;
  69 R5 = 0;
  70 R6 = 0;
  71 R7 = 0;
  72 R0.H = 0x7fff;
  73 R1.H = 0x7ffe;
  74 R2.H = 32767;
  75 R3.H = 32766;
  76 R4.H = -32768;
  77 R5.H = -32767;
  78 CHECKREG r0, 0x7fff0000;
  79 CHECKREG r1, 0x7ffe0000;
  80 CHECKREG r2, 0x7fff0000;
  81 CHECKREG r3, 0x7ffe0000;
  82 CHECKREG r4, 0x80000000;
  83 CHECKREG r5, 0x80010000;
  84
  85 pass