sim: bfin: import testsuite
[deliverable/binutils-gdb.git] / sim / testsuite / sim / bfin / c_ldimmhalf_l_pr.s
1 //Original:/proj/frio/dv/testcases/core/c_ldimmhalf_l_pr/c_ldimmhalf_l_pr.dsp
2 // Spec Reference: ldimmhalf l preg
3 # mach: bfin
4
5 .include "testutils.inc"
6 start
7
8 INIT_R_REGS -1;
9 INIT_P_REGS -1;
10
11 imm32 sp, 0xffffffff;
12 imm32 fp, 0xffffffff;
13
14 // test Preg
15 P1.L = 0x0003;
16 P2.L = 0x0005;
17 P3.L = 0x0007;
18 P4.L = 0x0009;
19 P5.L = 0x000b;
20 FP.L = 0x000d;
21 SP.L = 0x000f;
22 CHECKREG p1, 0xffff0003;
23 CHECKREG p2, 0xffff0005;
24 CHECKREG p3, 0xffff0007;
25 CHECKREG p4, 0xffff0009;
26 CHECKREG p5, 0xffff000b;
27 CHECKREG fp, 0xffff000d;
28 CHECKREG sp, 0xffff000f;
29
30 P1.L = 0x0030;
31 P2.L = 0x0050;
32 P3.L = 0x0070;
33 P4.L = 0x0090;
34 P5.L = 0x00b0;
35 FP.L = 0x00d0;
36 SP.L = 0x00f0;
37 //CHECKREG p0, 0x00000010;
38 CHECKREG p1, 0xffff0030;
39 CHECKREG p2, 0xffff0050;
40 CHECKREG p3, 0xffff0070;
41 CHECKREG p4, 0xffff0090;
42 CHECKREG p5, 0xffff00b0;
43 CHECKREG fp, 0xffff00d0;
44 CHECKREG sp, 0xffff00f0;
45
46 P1.L = 0x0300;
47 P2.L = 0x0500;
48 P3.L = 0x0700;
49 P4.L = 0x0900;
50 P5.L = 0x0b00;
51 FP.L = 0x0d00;
52 SP.L = 0x0f00;
53 CHECKREG p1, 0xffff0300;
54 CHECKREG p2, 0xffff0500;
55 CHECKREG p3, 0xffff0700;
56 CHECKREG p4, 0xffff0900;
57 CHECKREG p5, 0xffff0b00;
58 CHECKREG fp, 0xffff0d00;
59 CHECKREG sp, 0xffff0f00;
60
61 P1.L = 0x3000;
62 P2.L = 0x5000;
63 P3.L = 0x7000;
64 P4.L = 0x9000;
65 P5.L = 0xb000;
66 FP.L = 0xd000;
67 SP.L = 0xf000;
68 CHECKREG p1, 0xffff3000;
69 CHECKREG p2, 0xffff5000;
70 CHECKREG p3, 0xffff7000;
71 CHECKREG p4, 0xffff9000;
72 CHECKREG p5, 0xffffb000;
73 CHECKREG fp, 0xffffd000;
74 CHECKREG sp, 0xfffff000;
75
76 pass
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