1 //Original:testcases/core/c_ldst_ld_d_p_pp_xb/c_ldst_ld_d_p_pp_xb.dsp
2 // Spec Reference: c_ldst ld d [p++] xb
5 .include "testutils.inc"
18 I1 = P3; P3 = I0; I3 = SP; SP = I2;
19 loadsym p5, DATA_ADDR_1, 0x04;
20 loadsym p1, DATA_ADDR_2, 0x04;
21 loadsym p2, DATA_ADDR_3, 0x04;
22 loadsym i1, DATA_ADDR_4, 0x04;
23 loadsym p4, DATA_ADDR_5, 0x04;
24 loadsym fp, DATA_ADDR_6, 0x04;
25 loadsym i3, DATA_ADDR_7, 0x04;
35 CHECKREG r0, 0xFFFFFF87;
36 CHECKREG r1, 0x00000007;
37 CHECKREG r2, 0xFFFFFF87;
38 CHECKREG r3, 0x00000000;
39 CHECKREG r4, 0x00000007;
40 CHECKREG r5, 0x00000027;
41 CHECKREG r6, 0x00000047;
42 CHECKREG r7, 0x00000067;
51 CHECKREG r0, 0x00000066;
52 CHECKREG r1, 0xFFFFFF86;
53 CHECKREG r2, 0x00000006;
54 CHECKREG r3, 0xFFFFFF86;
55 CHECKREG r4, 0x00000007;
56 CHECKREG r5, 0x00000006;
57 CHECKREG r6, 0x00000026;
58 CHECKREG r7, 0x00000046;
67 CHECKREG r0, 0x00000045;
68 CHECKREG r1, 0x00000065;
69 CHECKREG r2, 0xFFFFFF85;
70 CHECKREG r3, 0x00000005;
71 CHECKREG r4, 0xFFFFFF85;
72 CHECKREG r5, 0x00000006;
73 CHECKREG r6, 0x00000005;
74 CHECKREG r7, 0x00000025;
83 CHECKREG r0, 0x00000024;
84 CHECKREG r1, 0x00000044;
85 CHECKREG r2, 0x00000064;
86 CHECKREG r3, 0xFFFFFF84;
87 CHECKREG r4, 0x00000004;
88 CHECKREG r5, 0xFFFFFF84;
89 CHECKREG r6, 0x00000005;
90 CHECKREG r7, 0x00000004;
95 // Pre-load memory with known data
96 // More data is defined than will actually be used