1 //Original:testcases/core/c_ldstpmod_ld_h_xh/c_ldstpmod_ld_h_xh.dsp
2 // Spec Reference: c_ldstpmod load dreg h & xh
5 .include "testutils.inc"
24 I1 = P3; P3 = I0; I3 = SP; SP = I2;
25 loadsym p5, DATA_ADDR_1, 0x00;
27 R0 = W [ P5 ++ P1 ] (Z);
28 R1 = W [ P5 ++ P1 ] (Z);
29 R2 = W [ P5 ++ P2 ] (Z);
30 R3 = W [ P5 ++ P3 ] (Z);
31 R4 = W [ P5 ++ P4 ] (Z);
32 R5 = W [ P5 ++ SP ] (Z);
33 R6 = W [ P5 ++ FP ] (Z);
34 CHECKREG r0, 0x0000A203;
35 CHECKREG r1, 0x00000001;
36 CHECKREG r2, 0x0000B607;
37 CHECKREG r3, 0x00009405;
38 CHECKREG r4, 0x00000A0B;
39 CHECKREG r5, 0x00000809;
40 CHECKREG r6, 0x0000CE0F;
49 I1 = P3; P3 = I0; I3 = SP; SP = I2;
50 loadsym p1, DATA_ADDR_1, 0x00;
52 R0 = W [ P1 ++ P5 ] (X);
53 R1 = W [ P1 ++ P2 ] (X);
54 R2 = W [ P1 ++ P2 ] (X);
55 R3 = W [ P1 ++ P3 ] (X);
56 R4 = W [ P1 ++ P4 ] (X);
57 R5 = W [ P1 ++ SP ] (X);
58 R6 = W [ P1 ++ FP ] (X);
59 CHECKREG r0, 0xFFFFA203;
60 CHECKREG r1, 0x00000001;
61 CHECKREG r2, 0xFFFFB607;
62 CHECKREG r3, 0xFFFF9405;
63 CHECKREG r4, 0x00000809;
64 CHECKREG r5, 0xFFFFAC0D;
65 CHECKREG r6, 0x00001011;
74 I1 = P3; P3 = I0; I3 = SP; SP = I2;
75 loadsym p2, DATA_ADDR_3, 0x06;
77 R0 = W [ P2 ++ P5 ] (Z);
78 R1 = W [ P2 ++ P1 ] (Z);
79 R2 = W [ P2 ++ P2 ] (Z);
80 R3 = W [ P2 ++ P3 ] (Z);
81 R4 = W [ P2 ++ P4 ] (Z);
82 R5 = W [ P2 ++ SP ] (Z);
83 R6 = W [ P2 ++ FP ] (Z);
84 CHECKREG r0, 0x00008445;
85 CHECKREG r1, 0x00004A4B;
86 CHECKREG r2, 0x00004849;
87 CHECKREG r3, 0x00004849;
88 CHECKREG r4, 0x00004E4F;
89 CHECKREG r5, 0x00005253;
90 CHECKREG r6, 0x00005051;
99 I1 = P3; P3 = I0; I3 = SP; SP = I2;
100 loadsym i1, DATA_ADDR_1, 0x02;
102 R0 = W [ P3 ++ P5 ] (X);
103 R1 = W [ P3 ++ P1 ] (X);
104 R2 = W [ P3 ++ P2 ] (X);
105 R3 = W [ P3 ++ P3 ] (X);
106 R4 = W [ P3 ++ P4 ] (X);
107 R5 = W [ P3 ++ SP ] (X);
108 R6 = W [ P3 ++ FP ] (X);
109 CHECKREG r0, 0x00000001;
110 CHECKREG r1, 0xFFFF9405;
111 CHECKREG r2, 0x00000A0B;
112 CHECKREG r3, 0x00000809;
113 CHECKREG r4, 0x00000809;
114 CHECKREG r5, 0xFFFFAC0D;
115 CHECKREG r6, 0x00001213;
124 I1 = P3; P3 = I0; I3 = SP; SP = I2;
125 loadsym p4, DATA_ADDR_2, 0x00;
127 R0 = W [ P4 ++ P5 ] (Z);
128 R1 = W [ P4 ++ P1 ] (X);
129 R2 = W [ P4 ++ P2 ] (X);
130 R3 = W [ P4 ++ P3 ] (Z);
131 R4 = W [ P4 ++ P4 ] (Z);
132 R5 = W [ P4 ++ SP ] (X);
133 R6 = W [ P4 ++ FP ] (X);
134 CHECKREG r0, 0x00002223;
135 CHECKREG r1, 0x00002021;
136 CHECKREG r2, 0x00002627;
137 CHECKREG r3, 0x0000A425;
138 CHECKREG r4, 0x00002A2B;
139 CHECKREG r5, 0x00002A2B;
140 CHECKREG r6, 0xFFFF8829;
149 I1 = P3; P3 = I0; I3 = SP; SP = I2;
150 loadsym fp, DATA_ADDR_1, 0x02;
152 R0 = W [ FP ++ P5 ] (X);
153 R1 = W [ FP ++ P1 ] (X);
154 R2 = W [ FP ++ P2 ] (X);
155 R3 = W [ FP ++ P3 ] (X);
156 R4 = W [ FP ++ P4 ] (Z);
157 R5 = W [ FP ++ SP ] (Z);
158 R6 = W [ FP ++ FP ] (X);
159 CHECKREG r0, 0x00000001;
160 CHECKREG r1, 0x00000001;
161 CHECKREG r2, 0xFFFFB607;
162 CHECKREG r3, 0xFFFF9405;
163 CHECKREG r4, 0x00000A0B;
164 CHECKREG r5, 0x00000809;
165 CHECKREG r6, 0xFFFFAC0D;
174 I1 = P3; P3 = I0; I3 = SP; SP = I2;
175 loadsym i3, DATA_ADDR_1, 0x04;
178 R0 = W [ SP ++ P5 ] (Z);
179 R1 = W [ SP ++ P1 ] (X);
180 R2 = W [ SP ++ P2 ] (Z);
181 R3 = W [ SP ++ P3 ] (X);
182 R4 = W [ SP ++ P4 ] (Z);
183 R5 = W [ SP ++ P1 ] (X);
184 R6 = W [ SP ++ FP ] (Z);
185 CHECKREG r0, 0x0000B607;
186 CHECKREG r1, 0xFFFFB607;
187 CHECKREG r2, 0x00009405;
188 CHECKREG r3, 0x00000A0B;
189 CHECKREG r4, 0x00000809;
190 CHECKREG r5, 0xFFFFCE0F;
191 CHECKREG r6, 0x0000AC0D;
196 // Pre-load memory with known data
197 // More data is defined than will actually be used