sim: bfin: import testsuite
[deliverable/binutils-gdb.git] / sim / testsuite / sim / bfin / c_progctrl_except_rtx.S
1 //Original:/proj/frio/dv/testcases/core/c_progctrl_except_rtx/c_progctrl_except_rtx.dsp
2 // Spec Reference: c_progctrl_except_rtx
3 # mach: bfin
4 # sim: --environment operating
5
6 #include "test.h"
7 .include "testutils.inc"
8 start
9
10 include(std.inc)
11 include(selfcheck.inc)
12 INIT_R_REGS(0);
13 INIT_P_REGS(0);
14 //CHECK_INIT(p5, 0xe0000000);
15 include(symtable.inc)
16 CHECK_INIT_DEF(p5);
17 // load address of exception handler
18
19 P0 = 0x200C (Z); // 0xFFE0200C EVT3 EXCEPTION
20 P0.H = 0xFFE0;
21 R0 = exception_handler (Z); // wr address of exception handler to MMR EVT3
22 R0.H = exception_handler;
23 [ P0 ] = R0;
24
25 // Jump to User mode and enable exceptions
26
27 R0 = MidUserCode (Z);
28 R0.H = MidUserCode;
29 RETI = R0;
30 RTI; // cause it to go to Midusercode, .dd cause exception
31
32 BeginUserCode:
33 P1 = 1;
34 P2 = 2;
35 P3 = 3;
36 P4 = 4;
37
38 CHECKREG(r0, 0x00000000);
39 CHECKREG(r1, 0x00000001);
40 CHECKREG(r2, 0x00000002);
41 CHECKREG(r3, 0x00000003);
42 CHECKREG(r5, 0x00000000);
43 CHECKREG(r6, 0x00000000);
44 CHECKREG(r7, 0x00000000);
45 CHECKREG(p1, 0x00000001);
46 CHECKREG(p2, 0x00000002);
47 CHECKREG(p3, 0x00000003);
48 CHECKREG(p4, 0x00000004);
49
50 dbg_pass;
51 //jump 2;
52 //jump -2;
53 .dd 0xFFFFFFFF
54 .dd 0xFFFFFFFF
55 .dd 0xFFFFFFFF
56 .dd 0xFFFFFFFF
57 .dd 0xFFFFFFFF
58 .dd 0xFFFFFFFF
59 .dd 0xFFFFFFFF
60 .dd 0xFFFFFFFF
61
62 //dbg_pass;
63
64 MidUserCode:
65 .dd 0xFFFFFFFF
66 R0 = 0;
67 R1 = 1;
68 R2 = 2;
69 R3 = 3;
70 CC = R0;
71 IF !CC JUMP BeginUserCode;
72
73 .dd 0xFFFFFFFF
74 .dd 0xFFFFFFFF
75 .dd 0xFFFFFFFF
76 .dd 0xFFFFFFFF
77 .dd 0xFFFFFFFF
78 .dd 0xFFFFFFFF
79 .dd 0xFFFFFFFF
80 .dd 0xFFFFFFFF
81
82
83 exception_handler:
84 R4 = RETX; // error handler: RETX has the address of the same Illegal instr
85 R1 += 1;
86 R2 += 2;
87 R3 += 3;
88 R1 += 1;
89 R4 += 4; // we have to add 4 to point to next instr after return
90 RETX = R4;
91
92 RTX; // return from exception
93
94 .section MEM_DATA_ADDR_1,"aw"
95 .dd 0xDEADBEEF
96 .dd 0xBAD00BAD
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