sim/testsuite/sim/bfin/dbg_tr_umode.S

   1 //Original:/proj/frio/dv/testcases/debug/dbg_tr_umode/dbg_tr_umode.dsp
   2 // Description: Verify the basic functionality of TBUFPWR and TBUFEN in
   3 //              Supervisor mode
   4 # mach: bfin
   5 # sim: --environment operating
   6
   7 #include "test.h"
   8 .include "testutils.inc"
   9 start
  10
  11 include(std.inc)
  12 include(mmrs.inc)
  13 include(selfcheck.inc)
  14
  15 #ifndef ITABLE
  16 #define ITABLE           0xF0000000
  17 #endif
  18 #ifndef STACKSIZE
  19 #define STACKSIZE 0x20
  20 #endif
  21
  22 // This test embeds .text offsets, so pad our test so it lines up.
  23 .space 0x64
  24
  25 // Boot code
  26
  27  BOOT :
  28 INIT_R_REGS(0);                             // Initialize Dregs
  29 INIT_P_REGS(0);                             // Initialize Pregs
  30
  31 CHECK_INIT(p5,   0x00BFFFFC);
  32
  33 LD32(p0, EVT0);              // Setup Event Vectors and Handlers
  34
  35 LD32_LABEL(r0, EHANDLE);    // Emulation Handler (Int0)
  36         [ P0 ++ ] = R0;
  37
  38 LD32_LABEL(r0, RHANDLE);    // Reset Handler (Int1)
  39         [ P0 ++ ] = R0;
  40
  41 LD32_LABEL(r0, NHANDLE);    // NMI Handler (Int2)
  42         [ P0 ++ ] = R0;
  43
  44 LD32_LABEL(r0, XHANDLE);    // Exception Handler (Int3)
  45         [ P0 ++ ] = R0;
  46
  47         [ P0 ++ ] = R0;                // IVT4 not used
  48
  49 LD32_LABEL(r0, HWHANDLE);   // HW Error Handler (Int5)
  50         [ P0 ++ ] = R0;
  51
  52 LD32_LABEL(r0, THANDLE);    // Timer Handler (Int6)
  53         [ P0 ++ ] = R0;
  54
  55 LD32_LABEL(r0, I7HANDLE);   // IVG7 Handler
  56         [ P0 ++ ] = R0;
  57
  58 LD32_LABEL(r0, I8HANDLE);   // IVG8 Handler
  59         [ P0 ++ ] = R0;
  60
  61 LD32_LABEL(r0, I9HANDLE);   // IVG9 Handler
  62         [ P0 ++ ] = R0;
  63
  64 LD32_LABEL(r0, I10HANDLE);  // IVG10 Handler
  65         [ P0 ++ ] = R0;
  66
  67 LD32_LABEL(r0, I11HANDLE);  // IVG11 Handler
  68         [ P0 ++ ] = R0;
  69
  70 LD32_LABEL(r0, I12HANDLE);  // IVG12 Handler
  71         [ P0 ++ ] = R0;
  72
  73 LD32_LABEL(r0, I13HANDLE);  // IVG13 Handler
  74         [ P0 ++ ] = R0;
  75
  76 LD32_LABEL(r0, I14HANDLE);  // IVG14 Handler
  77         [ P0 ++ ] = R0;
  78
  79 LD32_LABEL(r0, I15HANDLE);  // IVG15 Handler
  80         [ P0 ++ ] = R0;
  81
  82 LD32(p0, EVT_OVERRIDE);
  83         R0 = 0;
  84         [ P0 ++ ] = R0;
  85         R0 = -1;     // Change this to mask interrupts (*)
  86         [ P0 ] = R0;   // IMASK
  87
  88 LD32_LABEL(p1, START);
  89
  90 LD32(p0, EVT15);
  91         [ P0 ] = P1;   // IVG15 (General) handler (Int 15) load with start
  92
  93 LD32_LABEL(r7, DUMMY);
  94 RETI = r7;
  95 RAISE 15;    // after we RTI, INT 15 should be taken
  96
  97 NOP;        // Workaround for Bug 217
  98 RTI;
  99 NOP;
 100 NOP;
 101 NOP;
 102 DUMMY:
 103           NOP;
 104 NOP;
 105 NOP;
 106 NOP;
 107
 108 // .code 0x200
 109 START:
 110 WR_MMR(TBUFCTL, 0x00000001, p0, r0);        // Turn ON trace Buffer
 111 WR_MMR(TBUFCTL, 0x00000003, p0, r0);        // Turn ON trace Buffer
 112                                                     //   TBUFPWR   = 1
 113                                                     //   TBUFEN    = 1
 114                                                     //   TBUFOVF   = 0
 115                                                     //   CMPLP     = 0
 116 NOP;
 117 NOP;
 118 NOP;
 119 NOP;
 120
 121 // The following code sets up the test for running in USER mode
 122
 123 LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
 124                         // ReturnFromInterrupt (RTI)
 125 RETI = r0;      // We need to load the return address
 126
 127 RTI;
 128
 129 STARTUSER:
 130 LD32_LABEL(sp, USTACK);   // setup the stack pointer
 131 FP = SP;            // set frame pointer
 132 JUMP BEGIN;
 133
 134 //*********************************************************************
 135
 136 BEGIN:
 137
 138
 139 NOP;
 140             NOP;
 141 NOP;
 142 JUMP.S label1;
 143         R4.L = 0x1111;
 144         R4.H = 0x1111;
 145 NOP;
 146 NOP;
 147 NOP;
 148 label2: R5.H = 0x7777;
 149         R5.L = 0x7888;
 150 JUMP.S label3;
 151         R6.L = 0x1111;
 152         R6.H = 0x1111;
 153 NOP;
 154 NOP;
 155 NOP;
 156 NOP;
 157 NOP;
 158 label1: R4.H = 0x5555;
 159         R4.L = 0x6666;
 160 NOP;
 161 NOP;
 162 NOP;
 163 NOP;
 164 NOP;
 165 JUMP.S label2;
 166         R5.L = 0x1111;
 167         R5.H = 0x1111;
 168 NOP;
 169 NOP;
 170 NOP;
 171 NOP;
 172 label3:
 173                 NOP;
 174 NOP;
 175 NOP;
 176                 NOP;
 177                 NOP;
 178                 NOP;
 179 NOP;
 180 NOP;
 181         // Checks the contents of the Trace Buffer
 182
 183             EXCPT 0;
 184                 NOP; NOP; NOP; NOP;
 185 CHECKREG(r2,    0x00000006);
 186 CHECKREG(r1,    0x00000416);
 187 CHECKREG(r0,    0x000002aa);
 188 CHECKREG(r3,    0x0000029a);
 189 CHECKREG(r4,    0x00000262);
 190 CHECKREG(r5,    0x00000004);
 191 CHECKREG(r6,    0x0000025a);
 192 CHECKREG(r7,    0x00000288);
 193                 NOP; NOP; NOP; NOP;
 194                 NOP; NOP; NOP; NOP;
 195
 196                 EXCPT 1;
 197                 NOP; NOP; NOP; NOP;
 198                 CHECKREG(r2,    0x00000005);
 199 CHECKREG(r1,    0x00000416);
 200 CHECKREG(r0,    0x00000304);
 201 CHECKREG(r3,    0x000002ac);
 202 CHECKREG(r4,    0x00000470);
 203 CHECKREG(r5,    0x00000003);
 204 CHECKREG(r6,    0x00000276);
 205 CHECKREG(r7,    0x0000024a);
 206                 NOP; NOP; NOP; NOP;
 207                 NOP; NOP; NOP; NOP;
 208
 209                 EXCPT 2;
 210                 NOP; NOP; NOP; NOP;
 211                 CHECKREG(r2,    0x00000004);
 212 CHECKREG(r1,    0x00000416);
 213 CHECKREG(r0,    0x0000035e);
 214 CHECKREG(r3,    0x00000306);
 215 CHECKREG(r4,    0x00000470);
 216 CHECKREG(r5,    0x00000002);
 217 CHECKREG(r6,    0x00000244);
 218 CHECKREG(r7,    0x00000242);
 219                 NOP; NOP; NOP; NOP;
 220
 221                 EXCPT 3;
 222                 NOP; NOP; NOP; NOP;
 223                 CHECKREG(r2,    0x00000003);
 224 CHECKREG(r1,    0x00000416);
 225 CHECKREG(r0,    0x000003b0);
 226 CHECKREG(r3,    0x00000360);
 227 CHECKREG(r4,    0x00000470);
 228 CHECKREG(r5,    0x00000001);
 229 CHECKREG(r6,    0x00000238);
 230 CHECKREG(r7,    0x00000236);
 231
 232
 233
 234 NOP;
 235 NOP;
 236 NOP;
 237 NOP;
 238 NOP;
 239 dbg_pass;        // Call Endtest Macro
 240
 241
 242
 243 //*********************************************************************
 244 //
 245 // Handlers for Events
 246 //
 247
 248 EHANDLE:            // Emulation Handler 0
 249 RTE;
 250
 251 RHANDLE:            // Reset Handler 1
 252 RTI;
 253
 254 NHANDLE:            // NMI Handler 2
 255 RTN;
 256
 257 XHANDLE:            // Exception Handler 3
 258         R7 = SEQSTAT;
 259
 260 RD_MMR(TBUFSTAT, p0,    r2);
 261 RD_MMR(TBUF,    p0,     r1);
 262 RD_MMR(TBUF,    p0,     r0);
 263 RD_MMR(TBUF,    p0,     r3);
 264 RD_MMR(TBUF,    p0,     r4);
 265 RD_MMR(TBUFSTAT, p0,    r5);
 266 RD_MMR(TBUF,    p0,     r6);
 267 RD_MMR(TBUF,    p0,     r7);
 268
 269                 NOP; NOP; NOP; NOP;
 270
 271 RTX;
 272
 273                 NOP; NOP; NOP; NOP;
 274                 NOP; NOP; NOP; NOP;
 275
 276 HWHANDLE:           // HW Error Handler 5
 277 RTI;
 278
 279 THANDLE:            // Timer Handler 6
 280 RTI;
 281
 282 I7HANDLE:           // IVG 7 Handler
 283 RTI;
 284
 285 I8HANDLE:           // IVG 8 Handler
 286 RTI;
 287
 288 I9HANDLE:           // IVG 9 Handler
 289 RTI;
 290
 291 I10HANDLE:          // IVG 10 Handler
 292 RTI;
 293
 294 I11HANDLE:          // IVG 11 Handler
 295 RTI;
 296
 297 I12HANDLE:          // IVG 12 Handler
 298 RTI;
 299
 300 I13HANDLE:          // IVG 13 Handler
 301 RTI;
 302
 303 I14HANDLE:          // IVG 14 Handler
 304 RTI;
 305
 306 I15HANDLE:          // IVG 15 Handler
 307 RTI;
 308
 309
 310     .space (STACKSIZE);
 311 KSTACK:
 312
 313     .space (STACKSIZE);
 314 USTACK: