1 # Verify ASTAT bits are set correctly during dsp mac insns
4 .include "testutils.inc"
8 dmm32 ASTAT, (0x4450cc90 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN);
9 dmm32 A0.w, 0x16ba2677;
10 dmm32 A0.x, 0x00000000;
12 A0 -= R4.H * R4.H (W32);
13 checkreg A0.w, 0x96ba2678;
14 checkreg A0.x, 0xffffffff;
15 checkreg ASTAT, (0x4450cc90 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN);
17 dmm32 ASTAT, (0x3c30c800 | _VS | _AV0S | _AC1 | _CC);
18 dmm32 A0.w, 0xf170d0c7;
19 dmm32 A0.x, 0xffffffff;
21 A0 -= R2.H * R2.L (W32);
22 checkreg A0.w, 0x80000000;
23 checkreg A0.x, 0xffffffff;
24 checkreg ASTAT, (0x3c30c800 | _VS | _AV0S | _AV0 | _AC1 | _CC);
26 dmm32 ASTAT, (0x6c200880 | _VS | _AV1S | _AC1 | _AC0 | _CC | _AN);
27 dmm32 A0.x, 0x560a1c52;
28 dmm32 A0.x, 0xffffffbb;
30 A0 = R5.H * R5.H (W32);
31 checkreg A0.w, 0x7fffffff;
32 checkreg A0.x, 0x00000000;
33 checkreg ASTAT, (0x6c200880 | _VS | _AV1S | _AV0S | _AV0 | _AC1 | _AC0 | _CC | _AN);
35 dmm32 ASTAT, (0x58908a90 | _VS | _AC1 | _AC0 | _AQ);
36 dmm32 A0.w, 0x00c5a4e0;
37 dmm32 A0.x, 0x00000000;
41 R2 = (A0 -= R0.L * R3.H) (FU);
42 checkreg R2, 0x00000000;
43 checkreg A0.w, 0x00000000;
44 checkreg A0.x, 0x00000000;
45 checkreg ASTAT, (0x58908a90 | _VS | _V | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _V_COPY);
47 dmm32 ASTAT, (0x2cc00c90 | _VS | _AC1 | _AC0 | _AQ | _AC0_COPY);
48 dmm32 A0.w, 0x00a38000;
49 dmm32 A0.x, 0x00000000;
53 R0 = (A0 -= R4.L * R1.L) (IU);
54 checkreg R0, 0x00000000;
55 checkreg A0.w, 0x00000000;
56 checkreg A0.x, 0x00000000;
57 checkreg ASTAT, (0x2cc00c90 | _VS | _V | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY);
59 dmm32 ASTAT, (0x3880c280 | _VS | _AC1 | _AZ);
60 dmm32 A0.w, 0x00000000;
61 dmm32 A0.x, 0x00000000;
64 R4.L = (A0 -= R6.H * R6.H) (FU);
65 checkreg R4, 0x139a0000;
66 checkreg ASTAT, (0x3880c280 | _VS | _V | _AV0S | _AV0 | _AC1 | _V_COPY | _AZ);
68 dmm32 ASTAT, (0x48408290 | _VS | _AV1S | _AV0S | _AQ | _CC | _AC0_COPY);
69 dmm32 A0.w, 0x6b426a69;
70 dmm32 A0.x, 0xffffffba;
74 R2.L = (A0 -= R3.L * R0.L) (IH);
75 checkreg R2, 0xf62c8000;
76 checkreg A0.w, 0x80000000;
77 checkreg A0.x, 0xffffffff;
78 checkreg ASTAT, (0x48408290 | _VS | _V | _AV1S | _AV0S | _AV0 | _AQ | _CC | _V_COPY | _AC0_COPY);
80 dmm32 ASTAT, (0x7c00c210 | _VS | _AC1 | _AN);
81 dmm32 A1.w, 0x730173e9;
82 dmm32 A1.x, 0xffffffae;
85 R5.H = (A1 -= R4.L * R5.L) (M, IH);
86 checkreg R5, 0x800059e8;
87 checkreg A1.w, 0x80000000;
88 checkreg A1.x, 0xffffffff;
89 checkreg ASTAT, (0x7c00c210 | _VS | _V | _AV1S | _AV1 | _AC1 | _V_COPY | _AN);
91 dmm32 ASTAT, (0x4830c400 | _VS | _V | _AV1S | _AV0S | _AC0 | _CC | _V_COPY | _AZ);
92 dmm32 A0.w, 0x033a05f0;
93 dmm32 A0.x, 0x00000000;
97 R6.L = (A0 -= R4.L * R3.H) (TFU);
98 checkreg R6, 0x80000000;
99 checkreg A0.w, 0x00000000;
100 checkreg A0.x, 0x00000000;
101 checkreg ASTAT, (0x4830c400 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC0 | _CC | _V_COPY | _AZ);