sim/testsuite/sim/bfin/testset2.s

   1 // testset instruction
   2 //TESTSET is an atomic test-and-set.
   3 //If the lock was not set prior to the TESTSET, cc is set, the lock bit is set,
   4 //and this processor gets the lock. If the lock was set
   5 //prior to the TESTSET, cc is cleared, the lock bit is still set,
   6 //but the processor fails to acquire the lock.
   7 # mach: bfin
   8
   9         .include "testutils.inc"
  10
  11         start
  12
  13         loadsym P0, datalabel;
  14
  15         R0 = 0;
  16         CC = R0;
  17         R0 = B [ P0 ] (Z);
  18         DBGA ( R0.L , 0 );
  19         TESTSET ( P0 );
  20         R0 = CC;
  21         DBGA ( R0.L , 1 );
  22         R0 = B [ P0 ] (Z);
  23         DBGA ( R0.L , 0x80 );
  24
  25         R0 = 0;
  26         CC = R0;
  27         TESTSET ( P0 );
  28         R0 = CC;
  29         DBGA ( R0.L , 0 );
  30         R0 = B [ P0 ] (Z);
  31         DBGA ( R0.L , 0x80 );
  32
  33         pass
  34
  35         .data
  36 datalabel:
  37         .dw 0