sim/testsuite/sim/d10v/t-macros.i

   1 # mach: d10v
   2 # output:
   3 # sim: --environment operating
   4
   5         .macro start
   6         .text
   7         .align 2
   8         .globl _start
   9 _start:
  10         ldi r0, 0
  11         .endm
  12
  13
  14         .macro exit47
  15         ldi r4, 1
  16         ldi r0, 47
  17         trap 15
  18         .endm
  19
  20
  21         .macro exit0
  22         ldi r4, 1
  23         ldi r0, 0
  24         trap 15
  25         .endm
  26
  27
  28         .macro exit1
  29         ldi r4, 1
  30         ldi r0, 1
  31         trap 15
  32         .endm
  33
  34
  35         .macro exit2
  36         ldi r4, 1
  37         ldi r0, 2
  38         trap 15
  39         .endm
  40
  41
  42         .macro load reg val
  43         ldi \reg, #\val
  44         .endm
  45
  46
  47         .macro load2w reg hi lo
  48         ld2w \reg, @(1f,r0)
  49         .data
  50         .align 2
  51 1:      .short \hi
  52         .short \lo
  53         .text
  54         .endm
  55
  56
  57         .macro check exit reg val
  58         cmpeqi  \reg, #\val
  59         brf0t 1f
  60 0:      ldi r4, 1
  61         ldi r0, \exit
  62         trap 15
  63 1:
  64         .endm
  65
  66
  67         .macro check2w2 exit reg hi lo
  68         st2w    \reg, @(1f,r0)
  69         ld      r2, @(1f, r0)
  70         cmpeqi  r2, #\hi
  71         brf0f   0f
  72         ld      r2, @(1f + 2, r0)
  73         cmpeqi  r2, #\lo
  74         brf0f   0f
  75         bra     2f
  76 0:      ldi r4, 1
  77         ldi r0, \exit
  78         trap 15
  79         .data
  80         .align 2
  81 1:      .long 0
  82         .text
  83 2:
  84         .endm
  85
  86
  87         .macro loadacc2 acc guard hi lo
  88         ldi     r2, #\lo
  89         mvtaclo r2, \acc
  90         ldi     r2, #\hi
  91         mvtachi r2, \acc
  92         ldi     r2, #\guard
  93         mvtacg  r2, \acc
  94         .endm
  95
  96
  97         .macro checkacc2 exit acc guard hi lo
  98         ldi     r2, #\guard
  99         mvfacg  r3, \acc
 100         cmpeq   r2, r3
 101         brf0f   0f
 102         ldi     r2, #\hi
 103         mvfachi r3, \acc
 104         cmpeq   r2, r3
 105         brf0f   0f
 106         ldi     r2, #\lo
 107         mvfaclo r3, \acc
 108         cmpeq   r2, r3
 109         brf0f   0f
 110         bra     4f
 111 0:      ldi r4, 1
 112         ldi r0, \exit
 113         trap 15
 114 4:
 115         .endm
 116
 117
 118         .macro loadpsw2 val
 119         ldi r2, #\val
 120         mvtc    r2, cr0
 121         .endm
 122
 123
 124         .macro checkpsw2 exit val
 125         mvfc    r2, cr0
 126         cmpeqi  r2, #\val
 127         brf0t   1f
 128         ldi r4, 1
 129         ldi r0, \exit
 130         trap 15
 131 1:
 132         .endm
 133
 134
 135         .macro hello
 136         ;; 4:write (1, string, strlen (string))
 137         ldi r4, 4
 138         ldi r0, 1
 139         ldi r1, 1f
 140         ldi r2, 2f-1f-1
 141         trap 15
 142         .section        .rodata
 143 1:      .string "Hello World!\n"
 144 2:      .align 2
 145         .text
 146         .endm
 147
 148
 149 ;;; Blat our DMAP registers so that they point at on-chip imem
 150         .macro point_dmap_at_imem
 151         .text
 152         ldi r2, MAP_INSN | 0xf
 153         st r2, @(DMAP_REG,r0)
 154         ldi r2, MAP_INSN
 155         st r2, @(IMAP1_REG,r0)
 156         .endm
 157
 158 ;;; Patch VEC so that it jumps back to code that checks PSW
 159 ;;; and then exits with success.
 160         .macro check_interrupt vec psw src
 161 ;;; Patch the interrupt vector's AE entry with a jmp to success
 162         .text
 163         ldi r4, #1f
 164         ldi r5, \vec
 165         ;;
 166         ld2w r2, @(0,r4)
 167         st2w r2, @(0,r5)
 168         ld2w r2, @(4,r4)
 169         st2w r2, @(4,r5)
 170         ;;
 171         bra 9f
 172         nop
 173 ;;; Code that gets patched into the interrupt vector
 174         .data
 175 1:      ldi r1, 2f@word
 176         jmp r1
 177 ;;; Successfull trap jumps back to here
 178         .text
 179 ;;; Verify the PSW
 180 2:      mvfc    r2, cr0
 181         cmpeqi  r2, #\psw
 182         brf0t   3f
 183         nop
 184         exit1
 185 ;;; Verify the original addr
 186 3:      mvfc    r2, bpc
 187         cmpeqi  r2, #\src@word
 188         brf0t   4f
 189         exit2
 190 4:      exit0
 191 ;;; continue as normal
 192 9:
 193         .endm
 194
 195
 196         PSW_SM = 0x8000
 197         PSW_01 = 0x4000
 198         PSW_EA = 0x2000
 199         PSW_DB = 0x1000
 200         PSW_DM = 0x0800
 201         PSW_IE = 0x0400
 202         PSW_RP = 0x0200
 203         PSW_MD = 0x0100
 204         PSW_FX = 0x0080
 205         PSW_ST = 0x0040
 206         PSW_10 = 0x0020
 207         PSW_11 = 0x0010
 208         PSW_F0 = 0x0008
 209         PSW_F1 = 0x0004
 210         PSW_14 = 0x0002
 211         PSW_C  = 0x0001
 212
 213
 214 ;;;
 215
 216         DMAP_MASK = 0x3fff
 217         DMAP_BASE = 0x8000
 218         DMAP_REG = 0xff04
 219
 220         IMAP0_REG = 0xff00
 221         IMAP1_REG = 0xff02
 222
 223         MAP_INSN = 0x1000
 224
 225 ;;;
 226
 227         VEC_RI   = 0x3ff00
 228         VEC_BAE  = 0x3ff04
 229         VEC_RIE  = 0x3ff08
 230         VEC_AE   = 0x3ff0c
 231         VEC_TRAP = 0x3ff10
 232         VEC_DBT  = 0x3ff50
 233         VEC_SDBT = 0x3fff4
 234         VEC_DBI  = 0x3ff58
 235         VEC_EI   = 0x3ff5c