sim/testsuite/sim/fr30/div2.cgs

   1 # fr30 testcase for div2 $Ri
   2 # mach(): fr30
   3
   4         .include "testutils.inc"
   5
   6         START
   7
   8         .text
   9         .global div2
  10 div2:
  11         ; Test div2 $Ri
  12         ; example from the manual -- all status bits 0
  13         mvi_h_gr        0x00ffffff,r2
  14         mvi_h_dr        0x00ffffff,mdh
  15         mvi_h_dr        0x0000000f,mdl
  16         set_dbits       0x0
  17         set_cc          0x00
  18         div2            r2
  19         test_cc         0 1 0 0
  20         test_dbits      0x0
  21         test_h_gr       0x00ffffff,r2
  22         test_h_dr       0x00000000,mdh
  23         test_h_dr       0x0000000f,mdl
  24
  25         ; D0 == 1
  26         mvi_h_dr        0x00ffffff,mdh
  27         set_dbits       0x1
  28         set_cc          0x00
  29         div2            r2
  30         test_cc         0 1 0 0
  31         test_dbits      0x1
  32         test_h_gr       0x00ffffff,r2
  33         test_h_dr       0x00000000,mdh
  34         test_h_dr       0x0000000f,mdl
  35
  36         ; D1 == 1
  37         mvi_h_dr        0x00ffffff,mdh
  38         set_dbits       0x2
  39         set_cc          0x00
  40         div2            r2
  41         test_cc         0 0 0 0
  42         test_dbits      0x2
  43         test_h_gr       0x00ffffff,r2
  44         test_h_dr       0x00ffffff,mdh
  45         test_h_dr       0x0000000f,mdl
  46
  47         ; D0 == 1, D1 == 1
  48         set_dbits       0x3
  49         set_cc          0x00
  50         div2            r2
  51         test_cc         0 0 0 0
  52         test_dbits      0x3
  53         test_h_gr       0x00ffffff,r2
  54         test_h_dr       0x00ffffff,mdh
  55         test_h_dr       0x0000000f,mdl
  56
  57         ; C == 1
  58         mvi_h_dr        0x11ffffee,mdh
  59         mvi_h_gr        0x11ffffef,r2
  60         set_dbits       0x0
  61         set_cc          0x00
  62         div2            r2
  63         test_cc         0 0 0 1
  64         test_dbits      0x0
  65         test_h_gr       0x11ffffef,r2
  66         test_h_dr       0x11ffffee,mdh
  67         test_h_dr       0x0000000f,mdl
  68
  69         ; D0 == 1, C == 1
  70         mvi_h_dr        0x23ffffdc,mdh
  71         mvi_h_gr        0x23ffffdd,r2
  72         set_dbits       0x1
  73         set_cc          0x00
  74         div2            r2
  75         test_cc         0 0 0 1
  76         test_dbits      0x1
  77         test_h_gr       0x23ffffdd,r2
  78         test_h_dr       0x23ffffdc,mdh
  79         test_h_dr       0x0000000f,mdl
  80
  81         ; D1 == 1, C == 1
  82         mvi_h_dr        0xfffffffd,mdh
  83         mvi_h_gr        0x00000004,r2
  84         set_dbits       0x2
  85         set_cc          0x00
  86         div2            r2
  87         test_cc         0 0 0 1
  88         test_dbits      0x2
  89         test_h_gr       0x00000004,r2
  90         test_h_dr       0xfffffffd,mdh
  91         test_h_dr       0x0000000f,mdl
  92
  93         ; D0 == 1, D1 == 1, C == 1
  94         mvi_h_dr        0x00000002,mdh
  95         mvi_h_gr        0xffffffff,r2
  96         set_dbits       0x3
  97         set_cc          0x00
  98         div2            r2
  99         test_cc         0 0 0 1
 100         test_dbits      0x3
 101         test_h_gr       0xffffffff,r2
 102         test_h_dr       0x00000002,mdh
 103         test_h_dr       0x0000000f,mdl
 104
 105         ; remainder is zero
 106         mvi_h_dr        0x00000004,mdh
 107         mvi_h_gr        0x00000004,r2
 108         set_dbits       0x0
 109         set_cc          0x00
 110         div2            r2
 111         test_cc         0 1 0 0
 112         test_dbits      0x0
 113         test_h_gr       0x00000004,r2
 114         test_h_dr       0x00000000,mdh
 115         test_h_dr       0x0000000f,mdl
 116
 117         pass
 118
 119
 120