1 # fr30 testcase for mulh $Rj,$Ri
4 .include "testutils.inc"
13 mvi_h_gr 0xdead0003,r7 ; multiply small numbers
14 mvi_h_gr 0xbeef0002,r8
15 set_cc 0x09 ; Set mask opposite of expected
20 mvi_h_gr 0xdead0001,r7 ; multiply by 1
21 mvi_h_gr 0xbeef0002,r8
22 set_cc 0x08 ; Set mask opposite of expected
27 mvi_h_gr 0xdead0002,r7 ; multiply by 1
28 mvi_h_gr 0xbeef0001,r8
29 set_cc 0x09 ; Set mask opposite of expected
34 mvi_h_gr 0xdead0000,r7 ; multiply by 0
35 mvi_h_gr 0xbeef0002,r8
36 set_cc 0x09 ; Set mask opposite of expected
41 mvi_h_gr 0xdead0002,r7 ; multiply by 0
42 mvi_h_gr 0xbeef0000,r8
43 set_cc 0x08 ; Set mask opposite of expected
48 mvi_h_gr 0xdead3fff,r7 ; 15 bit result
49 mvi_h_gr 0xbeef0002,r8
50 set_cc 0x09 ; Set mask opposite of expected
53 test_h_dr 0x00007ffe,mdl
55 mvi_h_gr 0xdead4000,r7 ; 16 bit result
56 mvi_h_gr 0xbeef0002,r8
57 set_cc 0x0a ; Set mask opposite of expected
60 test_h_dr 0x00008000,mdl
62 mvi_h_gr 0xdead4000,r7 ; 17 bit result
63 mvi_h_gr 0xbeef0004,r8
64 set_cc 0x0b ; Set mask opposite of expected
67 test_h_dr 0x00010000,mdl
69 mvi_h_gr 0xdead7fff,r7 ; max positive result
70 mvi_h_gr 0xbeef7fff,r8
71 set_cc 0x0b ; Set mask opposite of expected
74 test_h_dr 0x3fff0001,mdl
77 mvi_h_gr -3,r7 ; multiply small numbers
79 set_cc 0x05 ; Set mask opposite of expected
84 mvi_h_gr 3,r7 ; multiply small numbers
86 set_cc 0x05 ; Set mask opposite of expected
91 mvi_h_gr 1,r7 ; multiply by 1
93 set_cc 0x04 ; Set mask opposite of expected
98 mvi_h_gr -2,r7 ; multiply by 1
100 set_cc 0x05 ; Set mask opposite of expected
105 mvi_h_gr 0,r7 ; multiply by 0
107 set_cc 0x09 ; Set mask opposite of expected
112 mvi_h_gr -2,r7 ; multiply by 0
114 set_cc 0x08 ; Set mask opposite of expected
119 mvi_h_gr 0xdead2001,r7 ; 15 bit result
121 set_cc 0x05 ; Set mask opposite of expected
124 test_h_dr 0xffffbffe,mdl
126 mvi_h_gr 0xdead4000,r7 ; 16 bit result
128 set_cc 0x04 ; Set mask opposite of expected
131 test_h_dr 0xffff8000,mdl
133 mvi_h_gr 0xdead4001,r7 ; 16 bit result
135 set_cc 0x06 ; Set mask opposite of expected
138 test_h_dr 0xffff7ffe,mdl
140 mvi_h_gr 0xdead4000,r7 ; 17 bit result
142 set_cc 0x07 ; Set mask opposite of expected
145 test_h_dr 0xffff0000,mdl
147 mvi_h_gr 0xdead7fff,r7 ; max negative result
148 mvi_h_gr 0xbeef8000,r8
149 set_cc 0x07 ; Set mask opposite of expected
152 test_h_dr 0xc0008000,mdl
155 mvi_h_gr -3,r7 ; multiply small numbers
157 set_cc 0x09 ; Set mask opposite of expected
162 mvi_h_gr -1,r7 ; multiply by 1
164 set_cc 0x08 ; Set mask opposite of expected
169 mvi_h_gr -2,r7 ; multiply by 1
171 set_cc 0x09 ; Set mask opposite of expected
176 mvi_h_gr 0xdeadc001,r7 ; 15 bit result
178 set_cc 0x09 ; Set mask opposite of expected
181 test_h_dr 0x00007ffe,mdl
183 mvi_h_gr 0xdeadc000,r7 ; 16 bit result
185 set_cc 0x0a ; Set mask opposite of expected
188 test_h_dr 0x00008000,mdl
190 mvi_h_gr 0xdeadc000,r7 ; 17 bit result
192 set_cc 0x0b ; Set mask opposite of expected
195 test_h_dr 0x00010000,mdl
197 mvi_h_gr 0xdead8001,r7 ; almost max positive result
198 mvi_h_gr 0xbeef8001,r8
199 set_cc 0x0b ; Set mask opposite of expected
202 test_h_dr 0x3fff0001,mdl
204 mvi_h_gr 0xdead8000,r7 ; max positive result
205 mvi_h_gr 0xbeef8000,r8
206 set_cc 0x0b ; Set mask opposite of expected
209 test_h_dr 0x40000000,mdl