sim/testsuite/sim/frv/fr400/smu.cgs

   1 # frv testcase for smu $GRi,$GRj
   2 # mach: fr405 fr450
   3
   4         .include "../testutils.inc"
   5
   6         start
   7
   8         .global smu
   9 smu1:
  10         ; Positive operands
  11         set_gr_immed    3,gr7           ; multiply small numbers
  12         set_gr_immed    2,gr8
  13         smu             gr7,gr8
  14         test_gr_immed   3,gr7
  15         test_gr_immed   2,gr8
  16         test_spr_immed  6,iacc0l
  17         test_spr_immed  0,iacc0h
  18 smu2:
  19         set_gr_immed    1,gr7           ; multiply by 1
  20         set_gr_immed    2,gr8
  21         smu             gr7,gr8
  22         test_gr_immed   1,gr7
  23         test_gr_immed   2,gr8
  24         test_spr_immed  2,iacc0l
  25         test_spr_immed  0,iacc0h
  26 smu3:
  27         set_gr_immed    2,gr7           ; multiply by 1
  28         set_gr_immed    1,gr8
  29         smu             gr7,gr8
  30         test_gr_immed   1,gr8
  31         test_gr_immed   2,gr7
  32         test_spr_immed  2,iacc0l
  33         test_spr_immed  0,iacc0h
  34 smu4:
  35         set_gr_immed    0,gr7           ; multiply by 0
  36         set_gr_immed    2,gr8
  37         smu             gr7,gr8
  38         test_gr_immed   2,gr8
  39         test_gr_immed   0,gr7
  40         test_spr_immed  0,iacc0l
  41         test_spr_immed  0,iacc0h
  42 smu5:
  43         set_gr_immed    2,gr7           ; multiply by 0
  44         set_gr_immed    0,gr8
  45         smu             gr7,gr8
  46         test_gr_immed   0,gr8
  47         test_gr_immed   2,gr7
  48         test_spr_immed  0,iacc0l
  49         test_spr_immed  0,iacc0h
  50 smu6:
  51         set_gr_limmed   0x3fff,0xffff,gr7       ; 31 bit result
  52         set_gr_immed    2,gr8
  53         smu             gr7,gr8
  54         test_gr_immed   2,gr8
  55         test_gr_limmed  0x3fff,0xffff,gr7
  56         test_spr_limmed 0x7fff,0xfffe,iacc0l
  57         test_spr_immed  0,iacc0h
  58 smu7:
  59         set_gr_limmed   0x4000,0x0000,gr7       ; 32 bit result
  60         set_gr_immed    2,gr8
  61         smu             gr7,gr8
  62         test_gr_immed   2,gr8
  63         test_gr_limmed  0x4000,0x0000,gr7
  64         test_spr_limmed 0x8000,0x0000,iacc0l
  65         test_spr_immed  0,iacc0h
  66 smu8:
  67         set_gr_limmed   0x4000,0x0000,gr7       ; 33 bit result
  68         set_gr_immed    4,gr8
  69         smu             gr7,gr8
  70         test_gr_immed   4,gr8
  71         test_gr_limmed  0x4000,0x0000,gr7
  72         test_spr_immed  0,iacc0l
  73         test_spr_immed  1,iacc0h
  74 smu9:
  75         set_gr_limmed   0x7fff,0xffff,gr7       ; max positive result
  76         set_gr_limmed   0x7fff,0xffff,gr8
  77         smu             gr7,gr8
  78         test_gr_limmed  0x7fff,0xffff,gr8
  79         test_gr_limmed  0x7fff,0xffff,gr7
  80         test_spr_immed  0x00000001,iacc0l
  81         test_spr_limmed 0x3fff,0xffff,iacc0h
  82 smu10:
  83         ; Mixed operands
  84         set_gr_immed    -3,gr7          ; multiply small numbers
  85         set_gr_immed    2,gr8
  86         smu             gr7,gr8
  87         test_gr_immed   2,gr8
  88         test_gr_immed   -3,gr7
  89         test_spr_immed  -6,iacc0l
  90         test_spr_immed  -1,iacc0h
  91 smu11:
  92         set_gr_immed    3,gr7           ; multiply small numbers
  93         set_gr_immed    -2,gr8
  94         smu             gr7,gr8
  95         test_gr_immed   -2,gr8
  96         test_gr_immed   3,gr7
  97         test_spr_immed  -6,iacc0l
  98         test_spr_immed  -1,iacc0h
  99 smu12:
 100         set_gr_immed    1,gr7           ; multiply by 1
 101         set_gr_immed    -2,gr8
 102         smu             gr7,gr8
 103         test_gr_immed   -2,gr8
 104         test_gr_immed   1,gr7
 105         test_spr_immed  -2,iacc0l
 106         test_spr_immed  -1,iacc0h
 107 smu13:
 108         set_gr_immed    -2,gr7          ; multiply by 1
 109         set_gr_immed    1,gr8
 110         smu             gr7,gr8
 111         test_gr_immed   1,gr8
 112         test_gr_immed   -2,gr7
 113         test_spr_immed  -2,iacc0l
 114         test_spr_immed  -1,iacc0h
 115 smu14:
 116         set_gr_immed    0,gr7           ; multiply by 0
 117         set_gr_immed    -2,gr8
 118         smu             gr7,gr8
 119         test_gr_immed   -2,gr8
 120         test_gr_immed   0,gr7
 121         test_spr_immed  0,iacc0l
 122         test_spr_immed  0,iacc0h
 123 smu15:
 124         set_gr_immed    -2,gr7          ; multiply by 0
 125         set_gr_immed    0,gr8
 126         smu             gr7,gr8
 127         test_gr_immed   0,gr8
 128         test_gr_immed   -2,gr7
 129         test_spr_immed  0,iacc0l
 130         test_spr_immed  0,iacc0h
 131 smu16:
 132         set_gr_limmed   0x2000,0x0001,gr7       ; 31 bit result
 133         set_gr_immed    -2,gr8
 134         smu             gr7,gr8
 135         test_gr_immed   -2,gr8
 136         test_gr_limmed  0x2000,0x0001,gr7
 137         test_spr_limmed 0xbfff,0xfffe,iacc0l
 138         test_spr_limmed 0xffff,0xffff,iacc0h
 139 smu17:
 140         set_gr_limmed   0x4000,0x0000,gr7       ; 32 bit result
 141         set_gr_immed    -2,gr8
 142         smu             gr7,gr8
 143         test_gr_immed   -2,gr8
 144         test_gr_limmed  0x4000,0x0000,gr7
 145         test_spr_limmed 0x8000,0x0000,iacc0l
 146         test_spr_limmed 0xffff,0xffff,iacc0h
 147 smu18:
 148         set_gr_limmed   0x4000,0x0001,gr7       ; 32 bit result
 149         set_gr_immed    -2,gr8
 150         smu             gr7,gr8
 151         test_gr_immed   -2,gr8
 152         test_gr_limmed  0x4000,0x0001,gr7
 153         test_spr_limmed 0x7fff,0xfffe,iacc0l
 154         test_spr_limmed 0xffff,0xffff,iacc0h
 155 smu19:
 156         set_gr_limmed   0x4000,0x0000,gr7       ; 33 bit result
 157         set_gr_immed    -4,gr8
 158         smu             gr7,gr8
 159         test_gr_immed   -4,gr8
 160         test_gr_limmed  0x4000,0x0000,gr7
 161         test_spr_limmed 0x0000,0x0000,iacc0l
 162         test_spr_limmed 0xffff,0xffff,iacc0h
 163 smu20:
 164         set_gr_limmed   0x7fff,0xffff,gr7       ; max negative result
 165         set_gr_limmed   0x8000,0x0000,gr8
 166         smu             gr7,gr8
 167         test_gr_limmed  0x8000,0x0000,gr8
 168         test_gr_limmed  0x7fff,0xffff,gr7
 169         test_spr_limmed 0x8000,0x0000,iacc0l
 170         test_spr_limmed 0xc000,0x0000,iacc0h
 171 smu21:
 172         ; Negative operands
 173         set_gr_immed    -3,gr7          ; multiply small numbers
 174         set_gr_immed    -2,gr8
 175         smu             gr7,gr8
 176         test_gr_immed   -2,gr8
 177         test_gr_immed   -3,gr7
 178         test_spr_immed  6,iacc0l
 179         test_spr_immed  0,iacc0h
 180 smu22:
 181         set_gr_immed    -1,gr7          ; multiply by 1
 182         set_gr_immed    -2,gr8
 183         smu             gr7,gr8
 184         test_gr_immed   -2,gr8
 185         test_gr_immed   -1,gr7
 186         test_spr_immed  2,iacc0l
 187         test_spr_immed  0,iacc0h
 188 smu23:
 189         set_gr_immed    -2,gr7          ; multiply by 1
 190         set_gr_immed    -1,gr8
 191         smu             gr7,gr8
 192         test_gr_immed   -1,gr8
 193         test_gr_immed   -2,gr7
 194         test_spr_immed  2,iacc0l
 195         test_spr_immed  0,iacc0h
 196 smu24:
 197         set_gr_limmed   0xc000,0x0001,gr7       ; 31 bit result
 198         set_gr_immed    -2,gr8
 199         smu             gr7,gr8
 200         test_gr_immed   -2,gr8
 201         test_gr_limmed  0xc000,0x0001,gr7
 202         test_spr_limmed 0x7fff,0xfffe,iacc0l
 203         test_spr_immed  0,iacc0h
 204 smu25:
 205         set_gr_limmed   0xc000,0x0000,gr7       ; 32 bit result
 206         set_gr_immed    -2,gr8
 207         smu             gr7,gr8
 208         test_gr_immed   -2,gr8
 209         test_gr_limmed  0xc000,0x0000,gr7
 210         test_spr_limmed 0x8000,0x0000,iacc0l
 211         test_spr_immed  0,iacc0h
 212 smu26:
 213         set_gr_limmed   0xc000,0x0000,gr7       ; 33 bit result
 214         set_gr_immed    -4,gr8
 215         smu             gr7,gr8
 216         test_gr_immed   -4,gr8
 217         test_gr_limmed  0xc000,0x0000,gr7
 218         test_spr_immed  0x00000000,iacc0l
 219         test_spr_immed  1,iacc0h
 220 smu27:
 221         set_gr_limmed   0x8000,0x0001,gr7       ; almost max positive result
 222         set_gr_limmed   0x8000,0x0001,gr8
 223         smu             gr7,gr8
 224         test_gr_limmed  0x8000,0x0001,gr8
 225         test_gr_limmed  0x8000,0x0001,gr7
 226         test_spr_immed  0x00000001,iacc0l
 227         test_spr_limmed 0x3fff,0xffff,iacc0h
 228 smu28:
 229         set_gr_limmed   0x8000,0x0000,gr7       ; max positive result
 230         set_gr_limmed   0x8000,0x0000,gr8
 231         smu             gr7,gr8
 232         test_gr_limmed  0x8000,0x0000,gr8
 233         test_gr_limmed  0x8000,0x0000,gr7
 234         test_spr_immed  0x00000000,iacc0l
 235         test_spr_limmed 0x4000,0x0000,iacc0h
 236
 237         pass