sim/testsuite/sim/frv/fr550/cmaddhus.cgs

   1 # frv testcase for cmaddhus $FRi,$FRj,$FRj,$CCi,$cond
   2 # mach: all
   3
   4         .include "../testutils.inc"
   5
   6         start
   7
   8         .global cmaddhus
   9 cmaddhus:
  10         set_spr_immed   0x1b1b,cccr
  11
  12         set_fr_iimmed   0x0000,0x0000,fr10
  13         set_fr_iimmed   0x0000,0x0000,fr11
  14         cmaddhus        fr10,fr11,fr12,cc0,1
  15         test_fr_limmed  0x0000,0x0000,fr12
  16         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
  17         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
  18         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
  19         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
  20
  21         set_fr_iimmed   0xdead,0x0000,fr10
  22         set_fr_iimmed   0x0000,0xbeef,fr11
  23         cmaddhus        fr10,fr11,fr12,cc0,1
  24         test_fr_limmed  0xdead,0xbeef,fr12
  25         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
  26         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
  27         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
  28         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
  29
  30         set_fr_iimmed   0x0000,0xdead,fr10
  31         set_fr_iimmed   0xbeef,0x0000,fr11
  32         cmaddhus        fr10,fr11,fr12,cc0,1
  33         test_fr_limmed  0xbeef,0xdead,fr12
  34         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
  35         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
  36         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
  37         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
  38
  39         set_fr_iimmed   0x1234,0x5678,fr10
  40         set_fr_iimmed   0x1111,0x1111,fr11
  41         cmaddhus        fr10,fr11,fr12,cc0,1
  42         test_fr_limmed  0x2345,0x6789,fr12
  43         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
  44         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
  45         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
  46         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
  47
  48         set_fr_iimmed   0x7ffe,0x7ffe,fr10
  49         set_fr_iimmed   0x0002,0x0001,fr11
  50         cmaddhus        fr10,fr11,fr12,cc4,1
  51         test_fr_limmed  0x8000,0x7fff,fr12
  52         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
  53         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
  54         test_spr_bits   1,0,0,msr0              ; msr0.aovf set
  55         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
  56
  57         set_fr_iimmed   0xfffe,0xfffe,fr10
  58         set_fr_iimmed   0x0001,0x0002,fr11
  59         cmaddhus        fr10,fr11,fr12,cc4,1
  60         test_fr_limmed  0xffff,0xffff,fr12
  61         test_spr_bits   0x3c,2,4,msr0           ; msr0.sie is set
  62         test_spr_bits   2,1,1,msr0              ; msr0.ovf set
  63         test_spr_bits   1,0,1,msr0              ; msr0.aovf set
  64         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
  65
  66         set_spr_immed   0,msr0
  67         set_fr_iimmed   0x0002,0x0001,fr10
  68         set_fr_iimmed   0xfffe,0xfffe,fr11
  69         cmaddhus        fr10,fr11,fr12,cc4,1
  70         test_fr_limmed  0xffff,0xffff,fr12
  71         test_spr_bits   0x3c,2,8,msr0           ; msr0.sie is set
  72         test_spr_bits   2,1,1,msr0              ; msr0.ovf set
  73         test_spr_bits   1,0,1,msr0              ; msr0.aovf set
  74         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
  75
  76         set_spr_immed   0,msr0
  77         set_fr_iimmed   0x0001,0x0001,fr10
  78         set_fr_iimmed   0x8000,0x8000,fr11
  79         cmaddhus.p      fr10,fr10,fr12,cc4,1
  80         cmaddhus        fr11,fr11,fr13,cc4,1
  81         test_fr_limmed  0x0002,0x0002,fr12
  82         test_fr_limmed  0xffff,0xffff,fr13
  83         test_spr_bits   0x3c,2,0xc,msr0         ; msr0.sie is set
  84         test_spr_bits   2,1,1,msr0              ; msr0.ovf set
  85         test_spr_bits   1,0,1,msr0              ; msr0.aovf set
  86         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
  87
  88         set_spr_immed   0,msr0
  89         set_fr_iimmed   0x0000,0x0000,fr10
  90         set_fr_iimmed   0x0000,0x0000,fr11
  91         cmaddhus        fr10,fr11,fr12,cc1,0
  92         test_fr_limmed  0x0000,0x0000,fr12
  93         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
  94         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
  95         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
  96         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
  97
  98         set_fr_iimmed   0xdead,0x0000,fr10
  99         set_fr_iimmed   0x0000,0xbeef,fr11
 100         cmaddhus        fr10,fr11,fr12,cc1,0
 101         test_fr_limmed  0xdead,0xbeef,fr12
 102         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 103         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 104         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 105         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 106
 107         set_fr_iimmed   0x0000,0xdead,fr10
 108         set_fr_iimmed   0xbeef,0x0000,fr11
 109         cmaddhus        fr10,fr11,fr12,cc1,0
 110         test_fr_limmed  0xbeef,0xdead,fr12
 111         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 112         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 113         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 114         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 115
 116         set_fr_iimmed   0x1234,0x5678,fr10
 117         set_fr_iimmed   0x1111,0x1111,fr11
 118         cmaddhus        fr10,fr11,fr12,cc1,0
 119         test_fr_limmed  0x2345,0x6789,fr12
 120         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 121         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 122         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 123         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 124
 125         set_fr_iimmed   0x7ffe,0x7ffe,fr10
 126         set_fr_iimmed   0x0002,0x0001,fr11
 127         cmaddhus        fr10,fr11,fr12,cc5,0
 128         test_fr_limmed  0x8000,0x7fff,fr12
 129         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 130         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 131         test_spr_bits   1,0,0,msr0              ; msr0.aovf set
 132         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 133
 134         set_fr_iimmed   0xfffe,0xfffe,fr10
 135         set_fr_iimmed   0x0001,0x0002,fr11
 136         cmaddhus        fr10,fr11,fr12,cc5,0
 137         test_fr_limmed  0xffff,0xffff,fr12
 138         test_spr_bits   0x3c,2,4,msr0           ; msr0.sie is set
 139         test_spr_bits   2,1,1,msr0              ; msr0.ovf set
 140         test_spr_bits   1,0,1,msr0              ; msr0.aovf set
 141         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
 142
 143         set_spr_immed   0,msr0
 144         set_fr_iimmed   0x0002,0x0001,fr10
 145         set_fr_iimmed   0xfffe,0xfffe,fr11
 146         cmaddhus        fr10,fr11,fr12,cc5,0
 147         test_fr_limmed  0xffff,0xffff,fr12
 148         test_spr_bits   0x3c,2,8,msr0           ; msr0.sie is set
 149         test_spr_bits   2,1,1,msr0              ; msr0.ovf set
 150         test_spr_bits   1,0,1,msr0              ; msr0.aovf set
 151         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
 152
 153         set_spr_immed   0,msr0
 154         set_fr_iimmed   0x0001,0x0001,fr10
 155         set_fr_iimmed   0x8000,0x8000,fr11
 156         cmaddhus.p      fr10,fr10,fr12,cc5,0
 157         cmaddhus        fr11,fr11,fr13,cc5,0
 158         test_fr_limmed  0x0002,0x0002,fr12
 159         test_fr_limmed  0xffff,0xffff,fr13
 160         test_spr_bits   0x3c,2,0xc,msr0         ; msr0.sie is set
 161         test_spr_bits   2,1,1,msr0              ; msr0.ovf set
 162         test_spr_bits   1,0,1,msr0              ; msr0.aovf set
 163         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
 164
 165         set_fr_iimmed   0xdead,0xbeef,fr12
 166         set_spr_immed   0,msr0
 167         set_fr_iimmed   0x0000,0x0000,fr10
 168         set_fr_iimmed   0x0000,0x0000,fr11
 169         cmaddhus        fr10,fr11,fr12,cc0,0
 170         test_fr_limmed  0xdead,0xbeef,fr12
 171         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 172         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 173         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 174         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 175
 176         set_fr_iimmed   0xbeef,0x0000,fr10
 177         set_fr_iimmed   0x0000,0xdead,fr11
 178         cmaddhus        fr10,fr11,fr12,cc0,0
 179         test_fr_limmed  0xdead,0xbeef,fr12
 180         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 181         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 182         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 183         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 184
 185         set_fr_iimmed   0x0000,0xdead,fr10
 186         set_fr_iimmed   0xbeef,0x0000,fr11
 187         cmaddhus        fr10,fr11,fr12,cc0,0
 188         test_fr_limmed  0xdead,0xbeef,fr12
 189         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 190         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 191         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 192         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 193
 194         set_fr_iimmed   0x1234,0x5678,fr10
 195         set_fr_iimmed   0x1111,0x1111,fr11
 196         cmaddhus        fr10,fr11,fr12,cc0,0
 197         test_fr_limmed  0xdead,0xbeef,fr12
 198         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 199         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 200         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 201         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 202
 203         set_fr_iimmed   0x7ffe,0x7ffe,fr10
 204         set_fr_iimmed   0x0002,0x0001,fr11
 205         cmaddhus        fr10,fr11,fr12,cc4,0
 206         test_fr_limmed  0xdead,0xbeef,fr12
 207         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 208         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 209         test_spr_bits   1,0,0,msr0              ; msr0.aovf set
 210         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 211
 212         set_fr_iimmed   0xfffe,0xfffe,fr10
 213         set_fr_iimmed   0x0001,0x0002,fr11
 214         cmaddhus        fr10,fr11,fr12,cc4,0
 215         test_fr_limmed  0xdead,0xbeef,fr12
 216         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 217         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 218         test_spr_bits   1,0,0,msr0              ; msr0.aovf set
 219         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 220
 221         set_spr_immed   0,msr0
 222         set_fr_iimmed   0x0002,0x0001,fr10
 223         set_fr_iimmed   0xfffe,0xfffe,fr11
 224         cmaddhus        fr10,fr11,fr12,cc4,0
 225         test_fr_limmed  0xdead,0xbeef,fr12
 226         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 227         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 228         test_spr_bits   1,0,0,msr0              ; msr0.aovf set
 229         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 230
 231         set_fr_iimmed   0xbeef,0xdead,fr13
 232         set_spr_immed   0,msr0
 233         set_fr_iimmed   0x0001,0x0001,fr10
 234         set_fr_iimmed   0x8000,0x8000,fr11
 235         cmaddhus.p      fr10,fr10,fr12,cc4,0
 236         cmaddhus        fr11,fr11,fr13,cc4,0
 237         test_fr_limmed  0xdead,0xbeef,fr12
 238         test_fr_limmed  0xbeef,0xdead,fr13
 239         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 240         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 241         test_spr_bits   1,0,0,msr0              ; msr0.aovf set
 242         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 243
 244         set_fr_iimmed   0xdead,0xbeef,fr12
 245         set_spr_immed   0,msr0
 246         set_fr_iimmed   0x0000,0x0000,fr10
 247         set_fr_iimmed   0x0000,0x0000,fr11
 248         cmaddhus        fr10,fr11,fr12,cc1,1
 249         test_fr_limmed  0xdead,0xbeef,fr12
 250         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 251         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 252         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 253         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 254
 255         set_fr_iimmed   0xbeef,0x0000,fr10
 256         set_fr_iimmed   0x0000,0xdead,fr11
 257         cmaddhus        fr10,fr11,fr12,cc1,1
 258         test_fr_limmed  0xdead,0xbeef,fr12
 259         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 260         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 261         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 262         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 263
 264         set_fr_iimmed   0x0000,0xdead,fr10
 265         set_fr_iimmed   0xbeef,0x0000,fr11
 266         cmaddhus        fr10,fr11,fr12,cc1,1
 267         test_fr_limmed  0xdead,0xbeef,fr12
 268         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 269         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 270         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 271         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 272
 273         set_fr_iimmed   0x1234,0x5678,fr10
 274         set_fr_iimmed   0x1111,0x1111,fr11
 275         cmaddhus        fr10,fr11,fr12,cc1,1
 276         test_fr_limmed  0xdead,0xbeef,fr12
 277         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 278         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 279         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 280         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 281
 282         set_fr_iimmed   0x7ffe,0x7ffe,fr10
 283         set_fr_iimmed   0x0002,0x0001,fr11
 284         cmaddhus        fr10,fr11,fr12,cc5,1
 285         test_fr_limmed  0xdead,0xbeef,fr12
 286         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 287         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 288         test_spr_bits   1,0,0,msr0              ; msr0.aovf set
 289         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 290
 291         set_fr_iimmed   0xfffe,0xfffe,fr10
 292         set_fr_iimmed   0x0001,0x0002,fr11
 293         cmaddhus        fr10,fr11,fr12,cc5,1
 294         test_fr_limmed  0xdead,0xbeef,fr12
 295         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 296         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 297         test_spr_bits   1,0,0,msr0              ; msr0.aovf set
 298         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 299
 300         set_spr_immed   0,msr0
 301         set_fr_iimmed   0x0002,0x0001,fr10
 302         set_fr_iimmed   0xfffe,0xfffe,fr11
 303         cmaddhus        fr10,fr11,fr12,cc5,1
 304         test_fr_limmed  0xdead,0xbeef,fr12
 305         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 306         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 307         test_spr_bits   1,0,0,msr0              ; msr0.aovf set
 308         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 309
 310         set_fr_iimmed   0xbeef,0xdead,fr13
 311         set_spr_immed   0,msr0
 312         set_fr_iimmed   0x0001,0x0001,fr10
 313         set_fr_iimmed   0x8000,0x8000,fr11
 314         cmaddhus.p      fr10,fr10,fr12,cc5,1
 315         cmaddhus        fr11,fr11,fr13,cc5,1
 316         test_fr_limmed  0xdead,0xbeef,fr12
 317         test_fr_limmed  0xbeef,0xdead,fr13
 318         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 319         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 320         test_spr_bits   1,0,0,msr0              ; msr0.aovf set
 321         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 322
 323         set_fr_iimmed   0xdead,0xbeef,fr12
 324         set_spr_immed   0,msr0
 325         set_fr_iimmed   0x0000,0x0000,fr10
 326         set_fr_iimmed   0x0000,0x0000,fr11
 327         cmaddhus        fr10,fr11,fr12,cc2,1
 328         test_fr_limmed  0xdead,0xbeef,fr12
 329         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 330         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 331         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 332         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 333
 334         set_fr_iimmed   0xbeef,0x0000,fr10
 335         set_fr_iimmed   0x0000,0xdead,fr11
 336         cmaddhus        fr10,fr11,fr12,cc2,0
 337         test_fr_limmed  0xdead,0xbeef,fr12
 338         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 339         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 340         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 341         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 342
 343         set_fr_iimmed   0x0000,0xdead,fr10
 344         set_fr_iimmed   0xbeef,0x0000,fr11
 345         cmaddhus        fr10,fr11,fr12,cc2,1
 346         test_fr_limmed  0xdead,0xbeef,fr12
 347         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 348         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 349         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 350         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 351
 352         set_fr_iimmed   0x1234,0x5678,fr10
 353         set_fr_iimmed   0x1111,0x1111,fr11
 354         cmaddhus        fr10,fr11,fr12,cc2,0
 355         test_fr_limmed  0xdead,0xbeef,fr12
 356         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 357         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 358         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 359         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 360
 361         set_fr_iimmed   0x7ffe,0x7ffe,fr10
 362         set_fr_iimmed   0x0002,0x0001,fr11
 363         cmaddhus        fr10,fr11,fr12,cc6,1
 364         test_fr_limmed  0xdead,0xbeef,fr12
 365         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 366         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 367         test_spr_bits   1,0,0,msr0              ; msr0.aovf set
 368         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 369
 370         set_fr_iimmed   0xfffe,0xfffe,fr10
 371         set_fr_iimmed   0x0001,0x0002,fr11
 372         cmaddhus        fr10,fr11,fr12,cc6,0
 373         test_fr_limmed  0xdead,0xbeef,fr12
 374         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 375         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 376         test_spr_bits   1,0,0,msr0              ; msr0.aovf set
 377         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 378
 379         set_spr_immed   0,msr0
 380         set_fr_iimmed   0x0002,0x0001,fr10
 381         set_fr_iimmed   0xfffe,0xfffe,fr11
 382         cmaddhus        fr10,fr11,fr12,cc6,1
 383         test_fr_limmed  0xdead,0xbeef,fr12
 384         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 385         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 386         test_spr_bits   1,0,0,msr0              ; msr0.aovf set
 387         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 388
 389         set_fr_iimmed   0xbeef,0xdead,fr13
 390         set_spr_immed   0,msr0
 391         set_fr_iimmed   0x0001,0x0001,fr10
 392         set_fr_iimmed   0x8000,0x8000,fr11
 393         cmaddhus.p      fr10,fr10,fr12,cc6,0
 394         cmaddhus        fr11,fr11,fr13,cc6,1
 395         test_fr_limmed  0xdead,0xbeef,fr12
 396         test_fr_limmed  0xbeef,0xdead,fr13
 397         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 398         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 399         test_spr_bits   1,0,0,msr0              ; msr0.aovf set
 400         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 401
 402         set_fr_iimmed   0xdead,0xbeef,fr12
 403         set_spr_immed   0,msr0
 404         set_fr_iimmed   0x0000,0x0000,fr10
 405         set_fr_iimmed   0x0000,0x0000,fr11
 406         cmaddhus        fr10,fr11,fr12,cc3,1
 407         test_fr_limmed  0xdead,0xbeef,fr12
 408         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 409         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 410         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 411         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 412
 413         set_fr_iimmed   0xbeef,0x0000,fr10
 414         set_fr_iimmed   0x0000,0xdead,fr11
 415         cmaddhus        fr10,fr11,fr12,cc3,0
 416         test_fr_limmed  0xdead,0xbeef,fr12
 417         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 418         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 419         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 420         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 421
 422         set_fr_iimmed   0x0000,0xdead,fr10
 423         set_fr_iimmed   0xbeef,0x0000,fr11
 424         cmaddhus        fr10,fr11,fr12,cc3,1
 425         test_fr_limmed  0xdead,0xbeef,fr12
 426         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 427         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 428         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 429         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 430
 431         set_fr_iimmed   0x1234,0x5678,fr10
 432         set_fr_iimmed   0x1111,0x1111,fr11
 433         cmaddhus        fr10,fr11,fr12,cc3,0
 434         test_fr_limmed  0xdead,0xbeef,fr12
 435         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 436         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 437         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 438         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 439
 440         set_fr_iimmed   0x7ffe,0x7ffe,fr10
 441         set_fr_iimmed   0x0002,0x0001,fr11
 442         cmaddhus        fr10,fr11,fr12,cc7,1
 443         test_fr_limmed  0xdead,0xbeef,fr12
 444         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 445         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 446         test_spr_bits   1,0,0,msr0              ; msr0.aovf set
 447         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 448
 449         set_fr_iimmed   0xfffe,0xfffe,fr10
 450         set_fr_iimmed   0x0001,0x0002,fr11
 451         cmaddhus        fr10,fr11,fr12,cc7,0
 452         test_fr_limmed  0xdead,0xbeef,fr12
 453         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 454         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 455         test_spr_bits   1,0,0,msr0              ; msr0.aovf set
 456         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 457
 458         set_spr_immed   0,msr0
 459         set_fr_iimmed   0x0002,0x0001,fr10
 460         set_fr_iimmed   0xfffe,0xfffe,fr11
 461         cmaddhus        fr10,fr11,fr12,cc7,1
 462         test_fr_limmed  0xdead,0xbeef,fr12
 463         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 464         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 465         test_spr_bits   1,0,0,msr0              ; msr0.aovf set
 466         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 467
 468         set_fr_iimmed   0xbeef,0xdead,fr13
 469         set_spr_immed   0,msr0
 470         set_fr_iimmed   0x0001,0x0001,fr10
 471         set_fr_iimmed   0x8000,0x8000,fr11
 472         cmaddhus.p      fr10,fr10,fr12,cc7,0
 473         cmaddhus        fr11,fr11,fr13,cc7,1
 474         test_fr_limmed  0xdead,0xbeef,fr12
 475         test_fr_limmed  0xbeef,0xdead,fr13
 476         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 477         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 478         test_spr_bits   1,0,0,msr0              ; msr0.aovf set
 479         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt always set
 480
 481         pass