2003-10-06 Dave Brolley <brolley@redhat.com>
[deliverable/binutils-gdb.git] / sim / testsuite / sim / frv / fr550 / dcpl.cgs
1 # FRV testcase for dcpl GRi,GRj,lock
2 # mach: all
3
4 .include "../testutils.inc"
5
6 start
7
8 .global dcpl
9 dcpl:
10 or_spr_immed 0xc8000000,hsr0 ; caches enabled -- copy-back mode
11
12 ; preload and lock all the lines in set 0 of the data cache
13 set_gr_immed 0x70000,gr10
14 dcpl gr10,gr0,1
15 set_mem_immed 0x11111111,gr10
16 test_mem_immed 0x11111111,gr10
17
18 inc_gr_immed 0x2000,gr10
19 set_gr_immed 1,gr11
20 dcpl gr10,gr11,1
21 set_mem_immed 0x22222222,gr10
22 test_mem_immed 0x22222222,gr10
23
24 inc_gr_immed 0x2000,gr10
25 set_gr_immed 63,gr11
26 dcpl gr10,gr11,1
27 set_mem_immed 0x33333333,gr10
28 test_mem_immed 0x33333333,gr10
29
30 inc_gr_immed 0x2000,gr10
31 set_gr_immed 64,gr11
32 dcpl gr10,gr11,1
33 set_mem_immed 0x44444444,gr10
34 test_mem_immed 0x44444444,gr10
35
36 ; Now write to another address which should be in the same set
37 ; the write should go through to memory, since all the lines in the
38 ; set are locked
39 inc_gr_immed 0x2000,gr10
40 set_mem_immed 0xdeadbeef,gr10
41 test_mem_immed 0xdeadbeef,gr10
42
43 ; Invalidate the data cache. Only the last value stored should have made
44 ; it through to memory
45 set_gr_immed 0x70000,gr10
46 invalidate_data_cache gr10
47 test_mem_immed 0,gr10
48
49 inc_gr_immed 0x2000,gr10
50 invalidate_data_cache gr10
51 test_mem_immed 0,gr10
52
53 inc_gr_immed 0x2000,gr10
54 invalidate_data_cache gr10
55 test_mem_immed 0,gr10
56
57 inc_gr_immed 0x2000,gr10
58 invalidate_data_cache gr10
59 test_mem_immed 0,gr10
60
61 inc_gr_immed 0x2000,gr10
62 invalidate_data_cache gr10
63 test_mem_immed 0xdeadbeef,gr10
64
65 pass
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