sim/testsuite/sim/frv/interrupts/badalign-fr550.cgs

   1 # frv testcase to generate interrupt for st $GRk,@($GRi,$GRj)
   2 # mach: fr550
   3         .include "testutils.inc"
   4
   5         start
   6
   7         .global align
   8 align:
   9         and_spr_immed   -4081,tbr               ; clear tbr.tt
  10         set_gr_spr      tbr,gr17
  11         inc_gr_immed    0x100,gr17              ; address of exception handler
  12         set_bctrlr_0_0  gr17
  13         set_spr_immed   128,lcr
  14         set_psr_et      1
  15         set_gr_immed    0xdeadbeef,gr17
  16         set_gr_immed    0,gr15
  17         inc_gr_immed    2,sp            ; out of alignment
  18
  19         test_spr_bits   1,0,0,isr       ; ISR.EMAM always clear (not used)
  20         sti             gr17,@(sp,0)    ; no exception
  21         sti             gr17,@(sp,4)    ; no exception
  22         ldi             @(sp,0),gr18    ; stored at unaligned address
  23         test_gr_immed   0xdeadbeef,gr18
  24         ldi             @(sp,0),gr19    ; no exception
  25         test_gr_immed   0xdeadbeef,gr19
  26
  27         and_spr_immed   0xfffffffe,isr  ; turn off ISR.EMAM
  28         sti             gr17,@(sp,0)    ; misaligned -- no exception
  29         test_gr_immed   0,gr15
  30
  31         set_gr_gr       sp,gr20
  32         set_gr_immed    1,gr21
  33         set_gr_immed    0x10101010,gr10
  34         nop.p
  35         ldu             @(sp,gr21),gr10 ; misaligned read  no exception
  36         test_gr_immed   0,gr15          ; handler was not called
  37         test_gr_immed   0xadbeefde,gr10 ; gr10 updated
  38         test_gr_immed   1,gr21          ; gr21 not updated
  39         inc_gr_immed    1,gr20
  40         test_gr_gr      gr20,sp         ; sp updated
  41
  42         pass