sim/testsuite/sim/frv/interrupts/fp_exception-fr550.cgs

   1 # frv testcase to generate fp_exception
   2 # mach: fr550
   3         .include "testutils.inc"
   4
   5         float_constants
   6         start
   7         load_float_constants
   8
   9         .global align
  10 align:
  11         ; clear the packing bit if the insn at 'pack:'. We can't simply use
  12         ; '.p' because the assembler will catch the error.
  13         set_gr_mem      pack,gr10
  14         and_gr_immed    0x7fffffff,gr10
  15         set_mem_gr      gr10,pack
  16         set_gr_addr     pack,gr10
  17         flush_data_cache gr10
  18
  19         and_spr_immed   -4081,tbr               ; clear tbr.tt
  20         set_gr_spr      tbr,gr17
  21         inc_gr_immed    0x070,gr17              ; address of exception handler
  22         set_bctrlr_0_0  gr17
  23         inc_gr_immed    0x060,gr17              ; address of exception handler
  24         set_bctrlr_0_0  gr17
  25         set_spr_immed   128,lcr
  26         set_spr_addr    ok1,lr
  27         set_psr_et      1
  28         inc_gr_immed    -4,sp           ; for alignment
  29
  30         set_gr_immed    0,gr20          ; PC increment
  31         set_gr_immed    0,gr15
  32
  33         set_spr_addr    ok3,lr
  34         set_gr_immed    4,gr20          ; PC increment
  35 badst1: stdfi           fr1,@(sp,0)     ; misaligned reg -- slot I0
  36         test_gr_immed   1,gr15
  37
  38         set_spr_addr    ok4,lr
  39         set_gr_immed    8,gr20          ; PC increment
  40         nop.p
  41 badst2: lddfi           @(sp,0),fr9     ; misaligned reg -- slot I1
  42         test_gr_immed   2,gr15
  43
  44         set_spr_addr    ok5,lr
  45         set_gr_immed    20,gr20         ; PC increment
  46         fnegs.p         fr9,fr9
  47         fnegs.p         fr9,fr10
  48         fnegs.p         fr9,fr11
  49 pack:   fnegs           fr10,fr12
  50         fnegs           fr10,fr13       ; packing violation
  51         test_gr_immed   3,gr15
  52
  53         set_spr_addr    ok1,lr
  54         set_gr_immed    4,gr20          ; PC increment
  55 bad:    fmadds          fr16,fr4,fr1    ; unimplemented
  56         test_gr_immed   4,gr15
  57
  58         and_spr_immed   0xfbffffff,fsr0         ; disable div/0 fp_exception
  59         set_fr_iimmed   0x7f7f,0xffff,fr0
  60         set_fr_iimmed   0x0000,0x0000,fr1
  61         fdivs           fr0,fr1,fr2             ; div/0 -- no exception
  62         test_spr_bits   0x100000,20,0x0,fsr0    ; fsr0.qne is never set
  63         test_spr_bits   0xfc00,10,0x4,fsr0      ; fsr0.aexc is still set
  64         test_spr_bits   0xe0000,17,0x0,fsr0     ; fsr0.ftt is clear
  65
  66         set_spr_addr    ok2,lr
  67         set_gr_immed    0,gr20                  ; PC increment
  68         or_spr_immed    0x04000000,fsr0         ; enable div/0 fp_exception
  69         set_fr_iimmed   0xdead,0xbeef,fr2
  70 div0:   fdivs           fr0,fr1,fr2             ; fp_exception - div/0
  71         test_fr_iimmed  0xdeadbeef,fr2          ; fr2 not updated
  72         test_gr_immed   5,gr15
  73
  74         and_spr_immed   0xfdffffff,fsr0         ; disable inexact fp_exception
  75         fsqrts          fr32,fr2                ; inexact -- no exception
  76         test_spr_bits   0x100000,20,0x0,fsr0    ; fsr0.qne is never set
  77         test_spr_bits   0xfc00,10,0x6,fsr0      ; fsr0.aexc is set
  78         test_spr_bits   0xe0000,17,0x0,fsr0     ; fsr0.ftt is clear
  79
  80         set_fr_fr       fr2,fr3                 ; sqrt 2
  81         set_fr_iimmed   0xdead,0xbeef,fr2
  82         set_spr_addr    ok6,lr
  83         or_spr_immed    0x02000000,fsr0         ; enable inexact fp_exception
  84 inxt1:  fsqrts          fr32,fr2                ; fp_exception - inexact
  85         test_gr_immed   6,gr15                  ; handler called
  86         test_fr_fr      fr2,fr3                 ; fr2 updated
  87
  88         set_fr_iimmed   0xdead,0xbeef,fr2
  89         set_spr_addr    ok7,lr
  90 inxt2:  fsqrts          fr32,fr2                ; fp_exception - inexact again
  91         test_gr_immed   7,gr15                  ; handler called
  92         test_fr_fr      fr2,fr3                 ; fr2 updated
  93
  94         pass
  95
  96 ; exception handler 1 -- illegal_instruction: bad insn
  97 ok1:
  98         test_spr_immed  1,esfr1                 ; esr0 active
  99         test_spr_bits   0x3e,1,0x5,esr0         ; esr0.ec is set
 100         test_spr_bits   0x1,0,0x1,esr0          ; esr0.valid is set
 101         bra             ret
 102
 103 ; exception handler 2 - fp_exception: divide by 0
 104 ok2:
 105         test_spr_bits   0x100000,20,0x0,fsr0    ; fsr0.qne is clear
 106         test_spr_bits   0xe0000,17,0x1,fsr0     ; fsr0.ftt is set
 107         test_spr_bits   0xfc00,10,0x4,fsr0      ; fsr0.aexc is still set
 108
 109         test_spr_immed  4,esfr1                 ; esr2 active
 110         test_spr_bits   0x3e,1,0xd,esr2         ; esr2.ec is set
 111         test_spr_bits   0x1,0,0x1,esr2          ; esr2.valid is set
 112         test_spr_addr   div0,epcr2              ; epcr2 is set
 113         bra             ret
 114
 115 ; exception handler 3 - illegal_instruction: register exception
 116 ok3:
 117         test_spr_immed  1,esfr1                 ; esr0 active
 118         test_spr_bits   0x3e,1,0x5,esr0         ; esr0.ec is set
 119         test_spr_bits   0x1,0,0x1,esr0          ; esr0.valid is set
 120         bra             ret
 121
 122 ; exception handler 4 - illegal_instruction: register exception
 123 ok4:
 124         test_spr_immed  1,esfr1                 ; esr0 active
 125         test_spr_bits   0x3e,1,0x5,esr0         ; esr0.ec is set
 126         test_spr_bits   0x1,0,0x1,esr0          ; esr0.valid is set
 127         bra             ret
 128
 129 ; exception handler 5 - illegal_instruction: sequence violation
 130 ok5:
 131         test_spr_immed  1,esfr1                 ; esr0 active
 132         test_spr_bits   0x3e,1,0x5,esr0         ; esr0.ec is set
 133         test_spr_bits   0x1,0,0x1,esr0          ; esr0.valid is set
 134         bra             ret
 135
 136 ; exception handler 6 - fp_exception: inexact
 137 ok6:
 138         test_spr_bits   0x100000,20,0x0,fsr0    ; fsr0.qne is clear
 139         test_spr_bits   0xe0000,17,0x1,fsr0     ; fsr0.ftt is set
 140         test_spr_bits   0xfc00,10,0x6,fsr0      ; fsr0.aexc is still set
 141
 142         test_spr_immed  4,esfr1                 ; esr2 active
 143         test_spr_bits   0x3e,1,0xd,esr2         ; esr2.ec is set
 144         test_spr_bits   0x1,0,0x1,esr2          ; esr2.valid is set
 145         test_spr_addr   inxt1,epcr2             ; epcr2 is set
 146         bra             ret
 147
 148 ; exception handler 7 - fp_exception: inexact again
 149 ok7:
 150         test_spr_bits   0x100000,20,0x0,fsr0    ; fsr0.qne is clear
 151         test_spr_bits   0xe0000,17,0x1,fsr0     ; fsr0.ftt is set
 152         test_spr_bits   0xfc00,10,0x6,fsr0      ; fsr0.aexc is still set
 153
 154         test_spr_immed  4,esfr1                 ; esr2 active
 155         test_spr_bits   0x3e,1,0xd,esr2         ; esr2.ec is set
 156         test_spr_bits   0x1,0,0x1,esr2          ; esr2.valid is set
 157         test_spr_addr   inxt2,epcr2             ; epcr2 is set
 158         bra             ret
 159
 160 ret:
 161         inc_gr_immed    1,gr15
 162         movsg           pcsr,gr60
 163         add             gr60,gr20,gr60
 164         movgs           gr60,pcsr
 165         rett            0
 166         fail
 167